JPH04134975A - Ghost removing device - Google Patents

Abstract

PURPOSE:To recude a circuit scale by providing an area based on a maximum extension quantity to a storage means, and specifying an address by an address output means based on a set delay quantity. CONSTITUTION:A digital video signal is inputted to an input terminal 11, and this input video signal is applied to a serial/parallel converting circuit (SP converting circuit) 31. The SP converting circuit 31 converts the serial video signal into a 2<n> bit parallel signal and applies to a memory device 32. The memory device 32 has the area of 2<n>X2<m> (=the maximum delay quantity), and each area is constituted by the same number of bit as an input signal. Parallel data of 2<n> bit read out from the memory 32 are applied to parallel/ serial converting circuits (PS converting circuit) C1-Cn, and the respective PS converting circuits C1-Cn converts the inputted parallel data into serial data, and outputs to variable delay circuits T1-Tn respectively. Thus, it is possible to reduce a number of steps of delay, and to reduce the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a ghost removal device that removes ghosts contained in television signals.

(Prior Art) FIG. 7 is a block diagram showing a conventional ghost removal device for removing ghosts from a video signal.

A video signal input through an input terminal 1 is applied to an A/D converter 2. The A/D converter 2 converts the input video signal into a digital signal and supplies it to the subtracter 3. The subtracter 3 includes a transversal filter (hereinafter referred to as TF), which will be described later.
A ghost cancellation signal is given from 4), and by subtracting the ghost cancellation signal from the input video signal, a signal from which the ghost component has been removed is output. The output of the subtracter 3 is converted into an analog signal by the D/A converter 5 and output from the output terminal 6, and is also applied to each variable delay circuit 8 of the variable delay circuit group 7.

FIG. 8 is a block diagram showing a specific configuration of the variable delay circuit 8. As shown in FIG.

A digital signal input via input terminal 11 is applied to memory 12 and stored therein. The memory 12 outputs the stored data to an output terminal 14 in response to a control signal from the counter 13. The counter 13 is supplied with delay amount data N and operates as an N-ary counter. The counter 13 uses the system clock CK (period T = 1/4 f
sc (70 ns), fsc counts the color subcarrier frequency (3,579545 MH2), and N
A control signal is outputted to the memory 12 by counting up the clock. That is, the input video signal is output from the memory 12 after being delayed by N unit time (N7 seconds). A delayed signal appearing at the output terminal 14 is applied to each TF4.

FIG. 9 is a block diagram showing the specific configuration of TF4.

TF9 includes tapped coefficient multipliers M1 to M, T-second delay units D a+ to D am, D bl to D bm, and adders A1 to A. Input terminal 1
The digital video signal from the variable delay circuit 8 inputted via the variable delay circuit 5 is applied to each tapped coefficient multiplier Ml to M, and each multiplier Ml to M is given a tap coefficient c1 to C, respectively. .

The tap coefficients C1 to C1 are applied from the coefficient terminal 18 to the nominal multipliers M1 to M via the tap coefficient memory 19. The outputs of the nominal multipliers M1 to M are the delay units Dal to D.
adders A1 to A with a delay of T seconds by am;
given to. The output of the previous stage TF4 is input to the input terminal 16, and the adder A1 adds the output of the previous stage TF and the delayed output from the delay device Dat and provides the result to the delay device Db1. Adders A2 to A, delay devices Dbl to Dbm-1
and the outputs of delay devices D112 to D am are added and output to delay devices D1+2 to D bm.

In this way, the delayed signals output from each of the multipliers M1 to M1 are added and output. The gain of each delayed signal is determined based on the tap coefficients C1 to C1 input from the coefficient terminal 18. An output based on the tap coefficients C+ to C1 appears at the output terminal 17, and the transmission path can be equalized by setting the tap coefficients C1 to C1.

By the way, the filtering time length by TF is determined by the number of taps. For this reason, an extremely large number of taps is required to remove all ghosts, from ghosts with short delay times to ghosts with long delay times. Since the number of taps that can be integrated into one TF, that is, the delay time range that can be equalized is limited, in FIG.
It is removed by F.

This operation will be explained with reference to FIG. FIG. 10 shows the ghost occurrence situation for each receiver installation location.

The situation in which ghosts occur differs depending on the installation location of the receiver6. For example, in FIG. 10(a), there are ghost components 21 with a relatively small delay time from the main signal and ghost components 22 and 23 with a relatively large delay time. is shown to be occurring. For example, assume that each of the ghost components 21 to 23 is removed by T F L to T F 3, respectively. These TFs to TF3 remove ghosts with delay times that are different from the ghost components 21 to 23. For example, in FIG. 10(b), it is shown that three ghost components 24 to 26 with a relatively long delay time from the main signal are generated.
4 to 26 are also removed in T F 1 to T F 3.

Similarly, in FIG. 10(C), two ghost components 27 and 28 with a relatively short delay time from the main signal and a ghost component with a relatively long delay time are mixed, but each of these ghost components 27.28 are also removed by T F s to T F 3.

That is, in FIG. 7, ghosts with a wide range of delay times can be dealt with with a small number of TFs by making the section of the delay time range that can be filtered by each TF 4 variable.

To do this, it is necessary to delay the input video signal by a delay amount corresponding to the delay time of each ghost component and provide it to each TF4.9 For this reason, the output of the subtracter 3 is delayed by the variable delay circuit 8. There is.

All variable delay circuits 8 need to be able to operate with a delay time corresponding to the entire removal range so that they can cope with any situation in which ghosts occur. That is, when the ghost removal range is set to 40 μsec, for example, it is necessary to set all the delay times of the variable delay circuit 8 to 40 μsec. If the scale of each variable delay circuit 8 is expressed as the number of stages in terms of a latch that provides a delay amount per unit time, the delay time per stage is 70 ns, so each variable delay circuit must be configured with 570 stages. be.

In this way, in the device shown in FIG. 7, the number of taps is reduced by varying the filtering section of TF4, thereby reducing the circuit scale. However, since the number of stages of the variable delay circuit 8 is extremely large, the circuit scale is reduced. Furthermore, the ghost occurrence situation at a predetermined position is approximately constant regardless of time changes, so there is almost no need to change the filtering section of TF4. That is, there is almost no need to change the delay amount of each variable delay circuit 8 at the same position, and a predetermined number of stages out of the total number of stages of variable delay circuits 8 remain unused, which is extremely wasteful.

(Problems to be Solved by the Invention) As described above, the conventional ghost removal device described above has a problem in that the circuit scale cannot be sufficiently reduced because the number of stages of variable delay circuits is large.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a ghost removal device that can reduce the circuit scale.

[Structure of the Invention] (Means for Solving the Problems) A ghost removal device according to the present invention includes a serial-parallel conversion circuit that converts a serial input video signal into n (n is a natural number) bit parallel data, and a maximum delay storage means for storing parallel data from the serial-to-parallel conversion circuit and having an area based on the amount of delay; address output means for specifying an address of the storage means according to a set delay amount; and data stored in the storage means. an output means for outputting n bits or more of parallel data; n-1 parallel-to-serial conversion circuits each receiving the parallel data from the output means and converting it into serial data based on a control signal and outputting the serial data; It is equipped with one transversal filter that equalizes the waveform of data from these n-1 parallel-to-serial conversion circuits and outputs the same.

(Function) In the present invention, the storage means has an area based on the maximum delay amount, and when the address output means specifies an address based on the set delay amount, the storage means outputs parallel data with the set delay amount. is read out. The data from the storage means is given to n-1 parallel-serial conversion circuits and serially output at the timing of the control signal, so that n-1 delayed signals are obtained from one storage means.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a variable delay circuit group of a ghost removal device according to a first embodiment of the present invention.

A digital video signal is input to the input terminal 11. This human-powered video signal is processed by a serial-parallel conversion circuit (
(hereinafter referred to as an SP conversion circuit) 31. The SP conversion circuit 31 converts the serial video signal into 21' bit parallel data and supplies it to the memory device 32. The memory device 32 has an area of 2''×2'' (=maximum delay amount), and each area is configured with the same number of bits as the input signal.

The address of the memory device 32 is designated by the address output from the adder 33. The outputs of the address counter 34 and selector 35 are applied to the adder 33. The address counter 34 counts a predetermined tally and counts up at 2". Each data of the addition data group 36 is input to the selector 35. The addition data group 36 consists of the data "O" and the 2" settings. It also has delay amount data. The selector 35 selects O'' of the addition data group 36 when writing to the memory device 32, and selects other setting delay data when reading. A delayed signal with a maximum delay amount of 2″×2″ unit time is obtained from .

The 2''-bit parallel data read from the memory device 32 is applied to parallel-to-serial conversion circuits (hereinafter referred to as PS conversion circuits) C1 to C1.

Each of the PS conversion circuits C1 to C2 converts the input parallel data into serial data and outputs the serial data to the variable delay circuits T1 to T, respectively. Each of the variable delay circuits T+ to T is composed of two stages, and the delay amount is controlled by the delay amount correction signal, and 2fi-1 types of delay signals are outputted to the respective output terminals O! It is designed to output from 0 to 0. For example, when giving delayed signals to three TFs (see FIG. 7), n=2 may be set.

In Figure 2, n=2. FIG. 3 is a block diagram specifically showing the configuration of each circuit when m=8.

The SP conversion circuit 31 is composed of three cascade-connected latches 41 to 43. Latches 41 to 43 latch and output data input by clock ICK. Input data and the output of each latch 41 to 43 are input to the memory device 32 in parallel. 22 X
A memory device 32 having 28 areas reads parallel data from the SP conversion circuit 31 in response to a write enable signal WE. In this case, the count value of the address counter 34 is applied as an address output to the memory device 32 via the adder circuit 33 and the latch 44.

On the other hand, during reading, the memory device 32 outputs 4-bit parallel data to the output bus O by the output enable signal OE.
It is output to each PS conversion circuit C1 to C9 via D. Four latches 45 to 48 are provided on the output side of the memory device 32, and a clock MCK is applied to these latches 45 to 48 to output latched data in parallel. In this case, the count output of the address counter 34 and the data based on the set delay amount from the selector 35 are added by the adder circuit 33 and provided to the memory device W32 as an address output. Depending on the address specification, up to 22X
A delay amount of 28=1024 unit times is obtained.

Each of the PS conversion circuits C1 to C3 is composed of selectors S1 to S3 and latches 49 to 52, and the LSB to M of parallel data from the memory device 32 is
SB is the input terminal of the latch 49 and the selectors S1 to S, respectively.
3 is applied to input terminal 0 of 3.

The outputs of latches 49 to 51 are output to selectors S1 to S3, respectively.
The outputs of selectors S1 to S3 are provided to latches 50 to 52 at the next stage, respectively. P.S.
Each selector s1 to S3 of the conversion circuit cl receives a control signal A.
is given, and the Ps conversion circuit CI receives this control signal A.
Low level (hereinafter referred to as "L") or high level (
Based on the output of the output bus OD (hereinafter referred to as "H"), the outputs of the latches 49 to 51 are selected and output to the latches 50 to 52 at the next stage. Latches 49 to 52 are supplied with a clock OCK and output latched data, and serial data is obtained from latch 52. The configuration of PS conversion circuits C2 and C3 is also PS
The configuration is the same as that of the conversion circuit C1. PS conversion circuit C2,
Each selector S1 to S3 of C3 receives control signals B and C, respectively.
is given. The PS conversion circuits C2 and Cm are configured to output serial data at the timing of the clock OCK after selecting data on the output bus OD using control signals B and C, respectively.

The outputs of the PSS conversion circuits C and C3 are respectively connected to variable delay circuits T.
The signals are output to output terminals 01 to 03 via terminals 1 to T3. Each of the variable delay circuits T1 to T3 includes cascade-connected latches 53 to 55 and a selector S4.
・Each PS conversion circuit C1 to C3
The outputs of the selectors S of the variable delay circuits TI to T3 are respectively
4 and the input terminal of latch 53. Each latch 53
The outputs of latches 54 and 55 are given to the next stage latches 54 and 55 and selector S4. The selector S4 selects the outputs of the PS conversion circuits C1 to C3 and the edges 53 according to the delay amount correction signal.
Any one of the outputs from 55 to 55 is selected and output to output terminals ()+ to 03. By having each selector S4 select an output based on the delay amount correction signal, the delay amount can be changed every unit time. In this way, video signals with three types of delay times can be obtained from the output terminals 01 to o3. This video signal is applied to a TF (not shown) (see FIG. 7).

Next, the operation of the ghost removal device configured as described above will be explained with reference to the timing charts of FIGS. 2 and 3. FIGS. 3(a) to (h) show a clock C with a frequency of 8 fsc and a clock C with a frequency of 4 fsc, respectively.
K shows the data of the digital input video signal, address output, write enable signal WE, output enable signal OE, clock MCK, and output bus OD.
) to (k) indicate the control signals A, B, and C, respectively, FIG. 3(1) indicates the clock OCK, and FIG. 3(m) to (p
) indicate the outputs of the variable delay circuits Tl to T3. In addition, in FIG. 3, the period T of the system clock CK is 1.
/4 f sc (70 n seconds).

The SP conversion circuit 31 is supplied with the signal shown in FIG.
) is input a data string of an input video signal sampled every 70 ns. When the data a to d are latched in each of the latches 43 to 41 of the SP conversion circuit 31, these data are written in parallel to the memory device W32 at the timing of the write enable signal WE (FIG. 3(e)). . The address of the memory device 32 is specified by the address output from the address counter 34 shown in FIG. 3(d).

The data written in the memory device 32 is read out at the timing of the output enable signal OE shown in FIG. 3(f).

The address in this case is specified by the addition output of the output of the address counter 34 and the output of the selector 35, and the output of the address counter 34 and the selector 35 allows a maximum delay of 1024 units of time. When outputting the data written in the memory device 32 without delay, the selector 35 selects "0" from the data group 36.
Select data. That is, address W1 and address 11 shown in FIG. 3(d) are the same, and address W1 shown in FIG.
) data a to d at the timing of clock MCK shown in
are simultaneously output via the output bus OD (Fig. 3 (h
)).

On the other hand, control signals A, B, and C shown in FIGS. 3(i) to (k) are applied to the ps conversion circuits C1 to C3, respectively. During the "L" period of the control signals A, B, and C, each selector S1 to S3 selects data from the output bus OD, and during the "H" period, each selector S1 to S3 selects the output of the latches 49 to 51.

In this embodiment, the control signals A, B, and C are generated with a shift of one clock, and each PS conversion circuit C1 to C3 has one clock.
Data on the output bus OD is taken in by each selector S1 to S3 with a clock shift. Each latch 49 to 5
2 outputs data latched by the clock OCK, and each PS conversion circuit C! From the latch 52 of C3, the clock OC after taking in the data on the output bus OD.
Serial data is sequentially output at timing K. For example, the data shown in FIG. 3(m) is sequentially output from the latch 52 from the PS conversion circuit C+. Control signals A, B, and C are generated at four clock cycles, and the output of each latch 52 is a delay signal that can be changed in units of four clocks. Therefore, variable delay circuits T1 to T3 are provided so that a delayed signal of one clock unit can be output.

Each PS conversion circuit C! Outputs from C3 are given to variable delay circuits T1 to T3. The variable delay circuit Tl selects the outputs of the switches 52 to 55 based on the delay amount correction signal, and outputs the input data as is or after delaying it by 1 to 3 clocks. That is, by selecting the outputs of the latches 52 to 55, the outputs shown in FIG. 3(m) to (p) are selectively outputted to the output terminal 01.

Similarly, from the variable delay circuit T2, the variable delay circuit T+
An output obtained by delaying the output of variable delay circuit T by one clock is output to output terminal 02, and an output obtained by delaying the output of variable delay circuit T by two clocks is output from variable delay circuit T3 to output terminal 03. In this way, three types of delayed signals are obtained from output terminals 01 to 03, and these delayed signals are given to a TF (not shown).Here, the maximum value of the delay amount is 1024 unit time, and the input data consists of 1 bit. It is assumed that It is also assumed that three types of delay signals provided to three TFs are generated. In this case, if the scale of the circuit is represented by the number of stages, corresponding to a latch that provides a delay amount of one unit time, the total number of delay stages required in the conventional example shown in Fig. 7 is 1024X.
3=3072 stages. Three 10-bit counters are also required. In contrast, in this embodiment, the memory device 32 has 1024 stages, and the latches 41 to 43
Since 7 x 4 latches of ゜45 to 48.49 to 55 are used, the total number of delay stages is 1024 + 7 x 410.
It has 52 steps. Also, one 8-bit counter is required. That is, in this embodiment, with the above settings, the circuit scale of the variable delay circuit that provides a delayed signal to the TF can be reduced to about 1/3 compared to the conventional example.

In this way, in this embodiment, parallel data is written in the memory device 32 having an area corresponding to the amount of delay,
Parallel data with a predetermined amount of delay is obtained by appropriately setting the read address, and this parallel data is given to multiple PS conversion circuits to output serial data at a timing based on a control signal, thereby delaying multiple amounts of delay. The number of delay stages is significantly reduced compared to the conventional example, and the circuit scale is reduced.

FIG. 4 is a block diagram showing a variable delay circuit group of a ghost removal device according to a second embodiment of the present invention. In FIG. 4, the same components as in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

In this embodiment, a memory device 60 is used instead of the memory device 32, and the latches 61 to 63 and the PS conversion circuit C
3+1 to C+1-1, variable delay circuit T, +1 to Ta
The difference from the first embodiment is that +1-1 is provided. That is, parallel data from the memory device 60 is given to the PS conversion circuits C1 to C4 via the latch 61, and
The latch 62 is also provided. The output of the latch 62 is passed through the latch 63 to the PS conversion circuit Car++ to c""-t
given to. ps conversion circuit Cゎ+1 to C2''+1-
The outputs of t are respectively C+1 to Te+1-1 under the variable delay circuit.
The signals are outputted to output terminals 0, , ++ to 02""-1 via. Note that the memory device 60 is one capable of high-speed operation with a shorter access time than the memory device 32 of FIG. 1.

By the way, even if the number of delay signals is doubled in the first embodiment, the scale of the circuit does not double, but (2n-1
) delayed signals, (2n-1)
Since it is necessary to prepare PS conversion circuits and configure each PS conversion circuit with 2n stages, the circuit scale becomes relatively large.

In contrast, in this embodiment, a high-speed memory device 60 is used to suppress the increase in circuit scale.

Next, a detailed explanation will be given with reference to FIG. Figure 5 shows n
=2. FIG. 3 is a block diagram showing a specific configuration when m=8.

The addition data group 37 includes data indicating delay amounts of O to 7 unit times. Addition circuit 33 is address counter 3
Adding the output of 4 and the output of selector 35 gives 8 f s
It is provided as an address output to the memory device 60 via the latch 44 operated by the clock of c.

Memory device 60 can be written to and read from at twice the speed of memory device 32 of FIG. Therefore, memory device 6
0, parallel data is output in twice as many cycles as the memory device 32 of FIG. This parallel data is applied to latches 61 and 62 that operate with different clocks.

The latch 61 operates with a clock having a frequency of 8 fsc, and the latch 62 operates with a clock CK having a frequency of 4 fsc. The output of the latch 62 is given to the u-ychiro 3, and the latch 63 corrects the timing of the latch output and outputs it.

The output of latch 61 is connected to four P
The output of the latch 63 is applied to the S conversion circuits C1 to C4 via the output bus OD2.
The signal is applied to three PS conversion circuits C9 to C7 having the same configuration. The outputs of these PS conversion circuits C1 to C7 are sent to output terminals 01 to 0 via variable delay circuits Tl to T7, respectively.
7 is output.

Next, the operation of the embodiment configured in this way will be explained in the sixth section.
This will be explained with reference to the timing chart shown in the figure. Figure 6 (
a) to (j) are a clock with a frequency of 8 f sc, a clock CK with a frequency of 4 f sc, an input video signal, an address output, an output enable signal OE, a write enable signal WE, a memory device, and a clock from 60, respectively. Parallel data, output bus○D! , the output of the latch 62, and the data on the output bus OD 2. FIGS. 6(k) to (n) show the control signals A, B, C, and D, respectively,
0) indicates data appearing at output terminal 01.

The output of the sp conversion circuit 31 is the same as in the first embodiment (
FIG. 6(C)), in this embodiment, the memory device 60
Writing and reading are performed at twice the speed of the first embodiment. That is, as shown in FIG. 6 (g>), the memory device 60 outputs parallel data at 8 fsc cycles.The latch 61 outputs this data to each PS conversion circuit C0 to C4 via the output bus OD1. Furthermore, the latch 62 operates at the same cycle as in the first embodiment and outputs the parallel data to the latch 63.The latch 63 corrects the output timing and outputs the parallel data to each ps conversion circuit via the output bus OD2. Parallel data is given to C5 to C?.

The output of the memory device 60 is divided into two, and four P
Output terminals 01 to 04 are output by S conversion circuits C1 to C4.
outputs four types of delayed signals, and three PS conversion circuits C
It is only necessary to output three types of delayed signals to the output terminals 05 to 07 by using the output terminals 05 to 07 using the PS conversion circuits C8 to C7.
? can be configured with the same number of stages as in FIG.

Other operations are similar to those in the first embodiment. In addition, in FIG. 6, only the control signals A to G given to the PS conversion circuits C1 to C4 are shown, and the control signals E to G given to the PS conversion circuits Cs to C7 are omitted.

As described above, according to this embodiment, the high-speed memory device 60
Since the output is divided and given to the latches 61 and 62 using This suppresses the increase in circuit scale when

Note that the present invention is not limited to the above embodiments, and for example, FIFO (First i
n First 0ut) memory is employed, but a memory having a bidirectional data bus may also be employed.

[Effects of the Invention] As explained above, according to the present invention, there is an effect that the circuit scale can be reduced.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing the configuration of a variable delay circuit group of a ghost removal device according to a first embodiment of the present invention, and □ Fig. 2 shows a specific example of the first embodiment. A block diagram showing the configuration, FIG. 3 is a timing chart for explaining the operation of the first embodiment, and FIG. 4 shows the configuration of the variable delay circuit group of the ghost removal device according to the second embodiment of the present invention. Block diagram shown, No. 5
FIG. 6 is a block diagram showing a specific configuration of the second embodiment, FIG. 6 is a timing chart for explaining the operation of the second embodiment, and FIG. 7 is a block diagram showing a conventional ghost removal device. Fig. 8 is a block diagram showing the variable delay circuit in Fig. 7, Fig. 9 is a block diagram showing the configuration of the TF in Fig. 7, and Fig. 10 shows the ghost occurrence situation for each receiver installation location. It is an explanatory diagram. 31... SP conversion circuit, 32... Memory device, 33
...Adder, 34...Address counter, 35...
- Selector, C1 to C1...PS conversion circuit, Ts to T4...variable delay circuit.

Claims (1)

[Scope of Claims] A serial-to-parallel conversion circuit that converts a serial input video signal to n (n is a natural number) bit parallel data; a storage means for storing data; an address output means for specifying an address of the storage means according to a set delay amount; an output means for outputting the data stored in the storage means as parallel data of n bits or more; n-1 parallel-to-serial conversion circuits each input parallel data from the means, convert it to serial data based on a control signal, and output the data; 1. A ghost removal device comprising: n-1 transversal filters that equalize and output.