JP2819922B2 - Hi-Vision signal processing circuit test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition signal processing circuit test system, and more particularly to a high-definition signal processing circuit test system. The present invention relates to a high-definition signal processing circuit test system having a circuit that bypasses a low-pass filtering unit in a high-definition signal processing circuit that performs processing and outputs.

[0002]

2. Description of the Related Art As a conventional Hi-Vision signal processing circuit test system, there is a system as shown in FIG.
Very high-speed signal processing is required in a high-definition signal processing circuit test system. For example, in the MUSE system, which is one of the transmission systems in HDTV, a maximum of 48.
Signal processing at 6 MHz is required. Since such a very high-speed signal processing is required, great care must be taken in forming a Hi-Vision signal processing circuit test system. For example, even the delay time of a data selector inserted when creating a detour circuit of a data path cannot be ignored.

[0003] An example of a conventional Hi-Vision signal processing circuit test system shown in FIG. 5 shows a test system for a low band replacement circuit, which is one of the Hi-Vision signal processing circuit test systems. In FIG. 5, a data flip-flop (hereinafter, referred to as DFF) 3 outputs a Hi-Vision signal A input from an input terminal 1 in synchronization with a system clock in response to a subtraction input of a delay adjustment circuit 6 and a subtractor 5, and a DFF 4 outputs The HDTV signal B input from the input terminal 2 is output in synchronization with the system clock with respect to the subtracted input of the subtracter 5. The Hi-Vision signal B is subtracted by the subtractor 5
Is subtracted by the Hi-Vision signal A to become a signal C. The signal C is multiplied by a coefficient based on the control signal input from the input terminal 4 in the coefficient unit 7 to become a signal D.
The signal D is outputted as a signal E to the adder 9 in synchronization with the system clock by the DFF 17 after only the low-frequency component is extracted by the low-pass filtering circuit (hereinafter referred to as LPF) 8 and at the same time as the signal b of the selector 11. Entered in the input. Signal E
Is a subtractor 5, a coefficient unit 7, an LPF
After being added to the HDTV signal A delayed by the same amount as the sum of the delay amounts in the DFF 8 and the DFF 17 in the adder 9, the signal is input to the a input of the selector 11 by the DFF 12 via the limiter 10 in synchronization with the system clock. . The selector 11 selects the input a during the normal operation and the input b during the test according to the test signal input from the input terminal 15 and makes the output terminal 13 conductive.

FIG. 6 is a circuit diagram showing an example of the LPF 8. As shown in FIG. 6, the LPF 8 has an input terminal 40, DF
F41A to 41R, adders 42A to 42F, coefficient unit 43
A to 43F and an output terminal 44. DFF
41A to 41C, adders 42A to 42B and coefficient unit 43
A to 43B constitute a third-order LPF, and DFFs 41D to 4D
1H, adders 42C to 42D and coefficient units 43C to 43D
Constitutes a fifth-order LPF, and DFFs 41I to 41R, adders 42E to 42F, and coefficient units 43E to 43F form a ninth-order LF.
A PF is constructed, and a 15th-order LPF is constructed as a whole. However, the coefficient units 43A to 43F are practically omitted because they can usually be realized by bit shift.

In the conventional high-vision signal processing circuit test system, the operation speed is required to be as high as 48.6 MHz, so that only two stages of logic can be executed by one stage of DFF, and it is difficult to insert even a selector. Therefore, a selector is inserted after the DFF 12 as a result.

[0006]

However, in the conventional HDTV signal processing circuit test system described above, only the LPF cannot be bypassed in the original flow of signal processing. The test efficiency is increased, but the adder 9 is not improved. In image processing, judgment is often made after viewing the actual image after mounting on the board, but the original signal processing becomes completely impossible at the time of testing with the conventional high-definition signal processing circuit test system. There is a problem that it is impossible to judge while looking at the picture. Further, the conventional high-vision signal processing circuit test system has a problem that a test control input terminal is required separately.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has been made in consideration of the above-described problems. The purpose is to provide a system.

[0008]

A high-definition signal processing circuit test system according to the present invention multiplies each of two high-definition input signals by a coefficient in accordance with an external control signal and performs low-pass filtering. In a high-definition signal processing circuit for performing a mixing process and outputting, a first data flip-flop for inputting a first high-definition signal from a first input terminal and a second data flip-flop for inputting a second high-definition signal from a second input terminal , A subtractor for subtracting the first HDTV signal from the second HDTV signal, and multiplying an output signal of the subtractor by a coefficient corresponding to a control signal input from a third input terminal. A coefficient unit, a low-pass filtering circuit for low-pass filtering the output signal of the coefficient unit, and a signal in the low-pass filtering circuit for outputting the output signal of the coefficient unit. A first delay adjusting circuit for delaying by the same time as the delay time, an output signal of the low-pass filter circuit in response to a control signal input from a fourth input terminal via a serial bus interface circuit, and A selection circuit for switching and outputting the output signal of the delay adjustment circuit; and a delay amount of each of the subtractor, the coefficient unit, the low-pass filtering circuit, and the selection circuit for outputting the output signal of the first data flip-flop. A second delay adjusting circuit for delaying by the same time as the sum of the two, an adder for adding the output signal of the second delay adjusting circuit and the output signal of the selecting circuit, and a limiter for the output signal of the adder. A limiter circuit for performing processing; and a third data flip-flop for outputting an output signal of the limiter circuit to an output terminal.

[0009]

In the HDTV signal processing circuit test system according to the present invention, the coefficient unit multiplies each of the first and second HDTV input signals by a coefficient in accordance with the control signal inputted from the third input terminal. The low-pass filtering circuit performs low-pass filtering on the output signal of the coefficient unit. The first delay adjustment circuit is provided in parallel with the low-pass filter circuit and delays the input signal by the same time as the signal delay time in the low-pass filter circuit. The selection circuit outputs an output signal of the low-pass filter circuit during a normal operation and an output signal of the first delay adjustment circuit during a test in response to a control signal input from the fourth input terminal via the serial bus interface circuit. Is output. In the high-definition signal processing circuit test system according to the present invention, the bypass circuit can be set without affecting the delay time of the original signal processing circuit, and the test can be performed without breaking the original signal processing circuit configuration. Since the system can be constructed, the test efficiency for the HDTV signal processing circuit can be improved.

[0010]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a high-vision signal processing circuit test system according to a first embodiment of the present invention. In FIG. 1, components having the same functions as those of the conventional HDTV signal processing circuit test system shown in FIG. 5 are denoted by the same reference numerals.

In the Hi-Vision signal processing circuit test system according to the first embodiment shown in FIG. 1, components different from those of the conventional example shown in FIG. 5 will be described below. A delay adjustment circuit 18 is provided in parallel with the LPF 8, and the output of the LPF 8 is connected to the a input of the selector 20.
The output of 8 is connected to the b input of the selector 20. The control terminal of the selector 20 is connected to the output of the serial bus interface circuit 16 whose input is connected to the input terminal 15, and the output of the selector 20 is connected to the input of the adder 9. The output of the DFF 12 is connected to the output terminal 13.

FIG. 3 is a circuit diagram showing details of the selector 20 in the HDTV signal processing circuit test system according to the embodiment of the present invention. As shown in FIG.
0 indicates n input terminals 210 to 21n-1, n input terminals 220 to 22n-1, input terminals 23 and 24, and n DFF2s.
50-25n-1, (nm) DFFs 26m-26n-1,
n clocked inverters 270 to 27n-1, n clocked inverters 280 to 28n-1, n inverters 290 to 29n-1, inverters 30 to 35, and n output terminals 360 to 36n-1 Have. Where n and m
Is a natural number having a relationship of [n>m> 0].

The m input terminals 210 to 21m-1 are connected via m clocked inverters 270 to 27m-1, respectively. The m input terminals 220 to 22m-1 are connected to m clocked inverters 280 to 280m, respectively. M DFFs 250 to 2 through 28m-1
Connected to 5m-1 data input, DFF250 ~ 25m-1
Are connected to m output terminals 360 to 36m-1 via inverters 290 to 29m-1 to provide m D terminals.
M sets of selectors of the type selected before the FF are configured.

Also, (nm) input terminals 21m to 21n
-1 are (nm) DFFs 25n to 25m-1 and (n
(M) clocked inverters 27m to 27n-1 and (nm) input terminals 22m to 22n-1 are connected to (nm) DFFs 26n to 26m-1 and (n-m), respectively. m) connected to the inverters 29m to 29n-1 via the clocked inverters 28m to 28n-1;
The output of -1 is connected to (nm) output terminals 36m to 36n-1, thereby constituting a (nm) set of selectors of a type for selecting data after the DFF.

Next, the operation of the high-vision signal processing circuit test system according to the first embodiment configured as described above will be described. The DFF 3 outputs the HDTV signal A input from the input terminal 1 in synchronization with the system clock with respect to the delay adjustment circuit 6A and the subtraction input of the subtractor 5, and the DFF4 subtracts the HDTV signal B input from the input terminal 2 into a subtractor. 5 is output in synchronization with the system clock for the subtracted input. The Hi-Vision signal B is subtracted by the subtractor 5
Is subtracted by the Hi-Vision signal A to become a signal C. The signal C is multiplied by a coefficient based on the control signal input from the input terminal 14 in the coefficient unit 7 to become a signal D. The signal D is input to the delay adjustment circuit 18 at the same time as being input to the LPF 8. The signal D input to the LPF 8
Is the signal E which is obtained by extracting only the low-frequency component and becomes the signal E.
0 is input to the a input. The signal D input to the delay adjustment circuit 18 is delayed by the same time as the signal D is delayed in the LPF 8 and input to the b input of the selector 20. The signal E is supplied to the subtractor 5 by the delay adjustment circuit 6A.
After being added by the adder 9 to the HDTV signal A delayed by the delay adjusting circuit 6A by the same amount as the sum of the delay amounts in the coefficient unit 7, the LPF 8 and the selector 20, the DFF 12 synchronizes with the system clock via the limiter 10. And output to the output terminal 13. The selector 20 receives an input signal a during normal operation according to a test signal input from the input terminal 15 via the serial bus interface circuit 16.
And input b at the time of the test.

FIG. 4 is a graph showing the delay time when the selector shown in FIG. 3 is inserted between two stages of adders. The delay time of the adder is the time from when the lowest full adder generates a carry and when the carry propagates to generate a sum signal at the highest order. There is time to rise, and conversely, the higher bits have more time from the rise of the clock of the DFF to the input of data to the adder.

Therefore, the data output of the adder is used to calculate the DF of the next stage.
There is enough time before the clock of F rises m-
Select up to the first bit before inputting the DFF.
By selecting after m-bit output after the output of the DFF, a bypass circuit can be inserted without affecting the delay time of the signal processing circuit by selecting m bits or more after the output of the DFF from the output of F to the input of the adder of the next stage.

In the first embodiment, the control of the HDTV signal processing circuit test system is performed via a serial bus. In the MUSE system, which is one of the high-definition signal processing circuits, a three-wire serial bus is used for system control. In the first embodiment, the test control input can be shared with the serial bus. In addition, in the first embodiment, since only the LPF can be bypassed from the signal processing system, the actual video can be obtained by setting the test mode via the serial bus after the construction of the Hi-Vision signal processing circuit. You can evaluate the circuit while looking at it.

FIG. 2 is a block diagram showing a high-vision signal processing circuit test system according to a second embodiment of the present invention. In the Hi-Vision signal processing circuit test system according to the second embodiment, the components different from those of the first embodiment shown in FIG. 1 can control the delay amount of the delay adjustment circuit 6A shown in FIG. 1 by a serial bus. This is a part replaced by the delay adjustment circuit 6B. This allows for testing
By setting the delay amount of the signal A to be smaller by the amount of the LPF, signal processing that bypasses only the LPF can be performed without the delay adjustment circuit 18 required in the first embodiment.

[0021]

As described above, according to the Hi-Vision signal processing circuit test system of the present invention, each of the two Hi-Vision input signals is multiplied by a coefficient in response to an external control signal, and the low-pass filtering is performed. In a high-definition signal processing circuit that performs a mixing process and then outputs a signal, n sets of data input terminals, n sets of selectors, and n sets of data flip-flops are provided as selection circuits for setting a bypass circuit for the low-pass filter circuit. And n sets of output terminals,
The lower m-bit signal of the bit input signal is output through a data flip-flop after performing a selection process, and the upper nm-bit signal is subjected to a selection process after passing through a data flip-flop. As a result, in the high-definition signal processing circuit test system according to the present invention, the bypass circuit can be set without affecting the delay time of the original signal processing circuit, and the test system can be constructed without breaking the original signal processing circuit configuration. The test efficiency for the high-definition signal processing circuit can be improved.

Further, in the high-vision signal processing circuit test system according to the present invention, the control of the high-vision signal processing circuit test system is performed using a serial bus similar to that used in the high-vision signal processing system. When the system is constructed, the test control input can be shared with the input of the serial bus, so that only the LPF can be bypassed from the signal processing system. Can be evaluated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a Hi-Vision signal processing circuit test system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a Hi-Vision signal processing circuit test system according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing details of a selector in the HDTV signal processing circuit test system according to the embodiment of the present invention.

4 is a graph showing a delay time when the selector shown in FIG. 3 is inserted between two stages of adders.

FIG. 5 is a block diagram showing an example of a conventional Hi-Vision signal processing circuit test system.

FIG. 6 is a block diagram illustrating details of a low-pass filter circuit illustrated in FIG. 5;

[Explanation of symbols]

 3, 4, 12; data flip-flop 5; subtractor 6A, 6B, 18; delay adjustment circuit 7; coefficient unit 8; low-pass filter circuit 9; adder 10; limiter 16; serial bus interface circuit 20;

Claims (3)

(57) [Claims] 1. A high-definition signal processing circuit for multiplying each of two high-definition input signals in accordance with a control signal input from the outside, performing low-pass filtering, performing mixing processing, and outputting the result, A first data flip-flop for inputting a first Hi-Vision signal from a terminal, a second data flip-flop for inputting a second Hi-Vision signal from a second input terminal, and the first data flip-flop from the second Hi-Vision signal; Subtracter for subtracting the HDTV signal, a coefficient multiplier for multiplying an output signal of the subtractor by a coefficient corresponding to a control signal inputted from a third input terminal, and a low-pass filtering process for an output signal of the coefficient multiplier Low-pass filtering circuit,
A first delay adjustment circuit for delaying the output signal of the coefficient unit by the same time as a signal delay time in the low-pass filter circuit, and a control signal input from a fourth input terminal via a serial bus interface circuit. A selection circuit that switches and outputs an output signal of the low-pass filter circuit and an output signal of the first delay adjustment circuit; and outputs the output signal of the first data flip-flop to the subtractor, the coefficient unit, A second delay adjustment circuit that delays by the same amount of time as the sum of the respective delay amounts of the low-pass filter circuit and the selection circuit, and adds the output signal of the second delay adjustment circuit and the output signal of the selection circuit An adder that performs a limiter process on an output signal of the adder; and a third data flip-flop that outputs an output signal of the limiter circuit to an output terminal. HDTV signal processing circuit test system, characterized in that it comprises. 2. The low-pass filtering circuit includes a plurality of data flip-flops and a plurality of adders, and outputs an output of one of the plurality of adders to an output of the low-pass filtering circuit. The selection circuit has n sets of data input terminals, n sets of selectors, n sets of data flip-flops, and n output terminals, and an n-bit input signal input from the n sets of data input terminals. Out of the n sets of selectors, the lower m bits of the signals are subjected to selection processing through the m sets of selectors in the n sets of selectors, and then the n pieces of data through the m sets of data flip-flops in the n sets of data flip-flops. The upper (nm) bits of the n-bit input signal output from m output terminals of the output terminals are:
(Nm) in the n sets of data flip-flops
The data is input to the (nm) sets of selectors of the n sets of selectors via the set of data flip-flops, and is subjected to selection processing, and is output from the (nm) output terminals of the n output terminals. 2. The HDTV signal processing circuit test system according to claim 1, wherein: 3. The second delay adjusting circuit according to claim 1, wherein a delay amount is externally controlled via the serial bus interface circuit, and the first delay control circuit is not required. 3. The HDTV signal processing circuit test system according to item 2.