JP3045079B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for a waveform equalizer and the like, and more particularly, to a digital filter having a test circuit for testing an integrator.

[0002]

2. Description of the Related Art Conventionally, as a technique for correcting the deterioration of a signal at the time of signal transmission, the degree of signal deterioration is determined from an input signal, and an appropriate coefficient is automatically set to perform a filtering process. There is a technique called automatic waveform equalization that corrects the waveform. This type of waveform equalization technology is based on QAM (Quu
addrture Amplitude Modula
) is an essential technique for obtaining a stable demodulated signal.

[0003] In the automatic waveform equalization technique, it is necessary to generate coefficients necessary for a filtering process from an input signal. Several methods have been proposed as means for generating this coefficient. As a very general method, there is a method of generating a coefficient by integrating an error signal. As this kind of technology, for example, a document “Al00 MHz, 5 MBaudQ”
AM Decision-Feedback Equa
riser for DigitaI Televisi
on Applications "(RBJ
i et al., Proc. of 1994 IEEE Int
international Solid-State Ci
rcuit Conference, p52, p5
3, p255). Further, in order to realize the generation of the coefficient by a circuit, a method of integrating only the sign of the error signal by a counter is often adopted.

FIG. 9 is a block diagram showing a configuration of a waveform equalizer in QAM. In FIG. 9, the input terminal 31
The in-phase signal component I input from the adder 33a,
3b, the in-phase signal component Dii fed back via the transversal filter 30a and the quadrature signal component Diq fed back via the transversal filter 30b are added together, and output as a waveform-equalized signal Di from an output terminal 32a. You. The waveform-equalized signal Di is fed back to the transversal filters 30a and 30c.

Similarly, the quadrature signal component Q input from the input terminal 31b is fed back by the adders 33c and 33d through the in-phase signal component Dqi fed back through the transversal filter 30c and the transversal filter 30d. Quadrature signal component Dq
q, and the waveform-equalized signal D is output from the output terminal 32b.
Output as q. Further, the waveform equalized signal Dq is
The feedback is provided to the transversal filters 30b and 30d.

The error detection circuit 34a extracts an error signal Ei from the waveform-equalized signal Di and supplies it to the transversal filters 30a and 30c. Error detection circuit 34b
Extracts the error signal Eq from the waveform-equalized signal Dq and supplies it to the transversal filters 30b and 30d.

As described above, a QAM signal has two signal components, an in-phase component and a quadrature component. Therefore, the waveform equalizer has a two-dimensional configuration as shown in FIG.

FIG. 10 is a block diagram showing a configuration of a transversal filter constituting the waveform equalizer of FIG. In the example shown in the figure, the number of taps is three for simplicity. Input data is input from the data input terminal 110 to the DFF
The signal is input to the multiplied inputs of the multipliers 51 to 53 of each tap via 80. The miscalculation signal is sent to the error data input terminal 160
From the taps 41 to 4 via the DFF 170
3 and integrated.

The outputs of the counters 41 to 43 are input to multiplier inputs of multipliers 51 to 53 as coefficients, and are multiplied by the input signals. Outputs of the multipliers 51 to 53 are added to adders 61 to 63.
Is added to the input signal from the previous tap, and delayed by DFFs 71 to 73 for realizing a unit delay,
Output to the next tap or output terminal 150.

Here, the coefficient needs to be updated for each tap, but since the signal processing rate is as high as 5 MHz to 40 MHz, it is necessary to have a counter for each tap due to the problem of processing speed. As described above, QAM is a two-dimensional filter, and one tap requires a circuit corresponding to four taps of a one-dimensional filter, and the same applies to a counter. Therefore, the configuration example of FIG. 9 also requires 3 taps × 4 = 12 counters.

Incidentally, the waveform equalizer shown in FIG.
As one of the problems in the case of I, there is a problem of testing a large number of counters as constituent elements. The visualization of the counter output is most effective for improving the failure detection rate. However, as a conventional method, there is a method for realizing this using a test bus. FIG. 11 shows the configuration of a conventional digital filter test circuit.

FIG. 3 shows a test control circuit 10, 3-state buffers 31 to 33, a test control input terminal 100, a test bus 131, and a test circuit for extracting a counter output to the transversal filter shown in FIG. An output terminal 130 is added. In FIG. 11, the outputs of the counters 41 to 43 are 3
It is connected to the inputs of the −state buffers 31 to 33 and is controlled by control signals G1 to G3 from the test control circuit 10.

The operation of the digital filter test circuit in the conventional waveform equalizer will be described with reference to the timing chart of FIG. When testing the output of the counter 41, the control signal G1 is changed to “enable”, G2,
By setting G3 to “disable”, 3-stat
e-buffer 31 is turned on, 3-state buffer 3
2. Turn off 33. As a result, the output of the counter 41 is transmitted to the test output terminal 130 via the test bus 131.
Output from Similarly, when testing the counter 42, the control signal G2 is set to "enable" and the control signals G1 and G3 are set to "disable", thereby setting the 3-state.
The buffer 32 is turned on, and the 3-state buffer 3
1, 33 are turned off. As a result, the output of the counter 42 is sent to the test output terminal 130 via the test bus 131.
Output from Thus, the counters 41 to 43 can be individually tested.

[0014]

The test circuit for a digital filter in the above-mentioned conventional waveform equalizer includes a first circuit.
As a problem, when a test bus is used for a circuit configuration, there is a problem that the test bus hinders an improvement in the integration degree of an LSI. The reason is that in the recent LSI manufacturing process, the increase in the number of wires and the length of the wires has a greater effect on the integration degree of the LSI than the increase in the number of elements. This is because a wiring having the same width as the number of output bits of the counter commonly connected from each tap at the time of layout is required.

A second problem is that the use of a test bus hinders a high-speed test. The reason for this is that the number of counters to be tested becomes large, so that the length of the test bus becomes long, and the load that must be driven due to being connected to a large number of 3-state buffers becomes very large, so that the bus becomes faster. This is because it is difficult to drive with a high speed and is not suitable for high-speed real-time processing as in the QAM system.

An object of the present invention is to provide a digital filter having a test circuit capable of easily testing an integrator, for example, a counter at each tap of the digital filter without increasing the chip area.

Another object of the present invention is to facilitate testing at an actual operating speed, which has been difficult with the conventional method, and to provide an LSI.
It is an object of the present invention to provide a digital filter equipped with a test circuit capable of improving the reliability of the digital filter.

[0018]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a waveform equalizer used in digital modulation / demodulation technology and the like.
An integrator for generating a coefficient among digital filters used in a device and the like; a delay circuit for providing a unit delay to an input signal from a previous stage and outputting a signal given the unit delay to a next stage; A plurality of adders configured by cascading n taps each including a multiplier for multiplying an output signal of a delay circuit and a coefficient generated by the integrator, and adding the outputs of the taps. In the transversal digital filter provided, each of the n taps is located between the delay circuit and the multiplier, and the output of the integrator of one predetermined tap is taken out as it is, and the other taps are taken out. Is provided with a test means for setting the output of "0" to "0".

According to a second aspect of the present invention, in the digital filter, the test means fixes a gate input signal to a predetermined value according to a control signal, and a control circuit for controlling the gate circuit. One or more registers for storing signals are provided, wherein the plurality of registers are connected in series and have a shift register configuration controlled by a common clock.

According to a third aspect of the present invention, in the digital filter, the integrator is a counter, and a reset signal for the counter is supplied from the register.

Another object of the present invention to achieve the above object is as follows:
For waveform equalizers used in digital modulation / demodulation technology, etc.
Among the digital filters used, an integrator for generating a coefficient, a multiplier for multiplying an input signal by a coefficient generated by the integrator, an output signal of the multiplier and an input from a previous stage
In a transversal digital filter configured by cascading n taps each including an adder for adding a signal and a delay circuit for giving a unit delay to the signal of the adder, Are provided between the input signal and the multiplier, and a test means for taking out the output of the integrator of one predetermined tap as it is and setting the output of the other tap to "0" is provided. It is characterized by the following.

In the digital filter according to the present invention, the test means may include a gate circuit in which each of the n taps fixes an input signal of the multiplier to a predetermined value in accordance with a control signal; One or more registers for storing a control signal for controlling the gate circuit,
A shift register is provided between the input signal and the multiplier, wherein the plurality of registers are connected in series and have a shift register configuration controlled by a common clock.

According to a sixth aspect of the present invention, in the digital filter, the integrator is a counter, and a reset signal for the counter is supplied from the register.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a transversal filter equipped with a digital filter test circuit according to a first embodiment of the present invention.

As shown in the figure, the digital transversal filter 300 of this embodiment in which n taps are cascaded has n taps 201 to 20n, respectively.
A delay circuit 3 that delays input data input via a preceding tap by a unit delay and outputs the delayed data to a next tap.
51-35n and integrators 401-40n for generating coefficients
And multipliers 51 to 5n for multiplying the input data with the coefficients generated by the integrators 401 to 40n;
Adders 62 to 6n for adding the outputs of 20n.

Data input to tap 201 is input from data input terminal 110, and error data input to integrators 401 to 40n is input from error data input terminal 160 via delay circuit 370. Also, tap 20
The outputs of 1 to 20n are added by adders 62 to 6n and output via output terminal 150 as the final output of transversal filter 300.

Further, the digital filter 3 of the present embodiment
Reference numeral 00 denotes a gate which is inserted between the data input terminal 110 and the multipliers 51 to 5n for each of the taps 201 to 20n and which can not only output the input data as it is but also fix it to arbitrary data according to a control signal. Circuit 22
1 to 22n, and registers 211 to 21n for storing control signals for controlling the gate circuits 221 to 22n.

When the integrators 401 to 40n are tested, the registers 211 to 21n synchronize the control signal input from the control data terminal 410 with the control clock input from the control clock input terminal 420. A shift register configuration for shifting from 211 to 212 and from 212 to 213 is adopted. As a result, there is no need for a configuration in which the outputs of the integrators 401 to 40n are extracted from the dedicated terminals using the test bus, unlike the related art shown in FIG.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

When testing the integrators 401 to 40n,
First, the registers 211 to 21n are all “disable
If "e", the register 211 captures the "enable" signal in synchronization with the rising edge of the clock SC input from the control clock input terminal 420, and "enables" the control signal A1.
01 is in the test enable state. Here, assuming that the signal B1 output from the gate circuit 221 is fixed to, for example, “1”, the output C1 of the integrator 401 is
Is multiplied by “1”, and D1 = C1 is output as it is. At this time, in the other taps 202 to 20n, the registers 212 to 21n shift the signals, and the control signals A2 to An become “disable”. Since the outputs of the gate circuits 222 to 22n are fixed to "0", the outputs D2 to Dn of the multipliers 51 to 5n are all "0". Therefore, in adders 62-6n, tap 20
The output of 1 and “1” are added to the outputs “0” of the other taps 202 to 20n, and the output of the tap 201 is output from the output terminal 150 without delay.

Next, a more specific configuration example and an operation example of the present embodiment will be described with reference to FIGS.

Referring to FIG. 3, transversal filter 301 has three taps for simplicity, and integrator 4
01 to 403 are configured by counters 41 to 43, and include a test control circuit 230 for supplying a test control signal SD and a test control clock SC, and an input terminal 100 for inputting a control signal for controlling the test control circuit 230, The reset signals of the counters 41 to 43 are transmitted to the shift register 211.
~ 213.

Referring to the timing chart of FIG.
Transversal filter 30 configured as described above
1, the test control signal SD generated by the test control circuit 230 is supplied to the register 211 at the rising edge of the test control clock SC also generated by the test control circuit 230.
Then, the output of the gate circuit 221 is fixed at "1" (fix1), and the counter 41 is reset to start counting.

The output D1 of the multiplier 51 is supplied to the gate circuit 22.
Since the result is the product of the output B1 of 1 and the output C1 of the counter 41, D1 = B1 * C1 = 1 * C1 = C1, and the output of the counter 41 becomes the output D1 as it is.

At this time, the other gate circuits 212 and 213
Is fixed to "0", the outputs D2 and D3 of the multipliers 52 and 53 are output to the counter 4 by the same operation as described above.
It becomes "0" irrespective of the values of the outputs C2 and C3 of 2, 43. Therefore, the adder 62 outputs the output D1 of the multiplier 51,
The adder 63 outputs the output of the adder 62 as it is. Thus, the output of the counter 41 is output from the output terminal 150 to the outside of the filter 301 via the DFF 90.

At the next rise of the test control clock SC, the output signal A1 of the register 211
And the gate circuit 222 is fixed at "1", and the counter 42 is reset to start counting.

The output D2 of the multiplier 52 is supplied to the gate circuit 22.
2 and the output C2 of the counter 42, so that D2 = B2 * C2 = 1 * C2 = C2, and the output of the counter 42 becomes the output D2 as it is.

At this time, the next control data (fix0) is taken into the register 211, and the gate circuit 221 is fixed at "0". Therefore, the output of the multiplier 51 also becomes “0”. Therefore, the output of the adder 62 outputs the value of D2 as it is.

As described above, the test control clock S
Registers that fix the output of the gate circuit to "1" are sequentially shifted in synchronization with C, and the output of each counter can be sequentially output to the outside of the filter.

FIG. 5 is a block diagram showing a configuration of a transversal filter equipped with a digital filter test circuit according to a second embodiment of the present invention.

As shown in the figure, the digital transversal filter 302 of this embodiment in which n taps are cascade-connected has n taps 261 to 26n respectively.
An integrator 401 to 40n for generating a coefficient;
Multipliers 51 to 5n for multiplying input coefficients by the generated coefficients of 〜 to 40n, adders 62 to 6n for adding data sent from the previous tap and data output from the multipliers 51 to 5n, Delay circuits 371 to 37n for delaying the outputs of the adders 62 to 6n by a unit time are provided.

Data input to tap 261 is input from data input terminal 110 via delay circuit 380, and error data input to integrators 401 to 40n is input from error data input terminal 160 via delay circuit 370. Is entered. The output of the tap 26n is output as the final output of the transversal filter 302 via the output terminal 150.

Further, the digital filter 3 of the present embodiment
Reference numeral 02 denotes a gate which is inserted between the data input terminal 110 and the multipliers 51 to 5n for each of the taps 261 to 26n and which can not only output the input data as it is but also fix it to arbitrary data according to a control signal. Circuit 22
1 to 22n, and registers 211 to 21n for storing control signals for controlling the gate circuits 221 to 22n.

When the integrators 401 to 40n are tested, the registers 211 to 21n synchronize the control signal input from the control data terminal 410 with the control clock input from the control clock input terminal 420. A shift register configuration for shifting from 211 to 212 and from 212 to 213 is adopted. As a result, there is no need for a configuration in which the outputs of the integrators 401 to 40n are extracted from the dedicated terminals using the test bus, unlike the related art shown in FIG.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

When testing the integrators 401 to 40n,
First, the registers 211 to 21n are all “disable
If "e", the register 211 captures the "enable" signal in synchronization with the rising edge of the clock SC input from the control clock input terminal 420, and "enables" the control signal A1.
01 is in the test enable state. Here, assuming that the signal B1 output from the gate circuit 221 is fixed to, for example, “1”, the output C1 of the integrator 401 is
Is multiplied by “1”, D1 = C1 and the delay circuit 37
It is delayed by 1 and output as it is. At this time, in the other taps 262 to 26n, the registers 212 to 21
n shifts the signal, and the control signals A2 to An
ble "a. The output of the gate circuit 222~22n is""to be fixed to the output D2~Dn multiplier 51~5n are all" 0 0 ". Thus, the adder
At 62, the touch delayed by the delay
The output “1” of the loop 261 is added to the output “0” of the multiplier 52.
After being calculated, the delay is delayed by the delay circuit 372 and the tap is performed.
262. Similarly, data is delayed one after another.
The output of the tap 261 is output from the output terminal 150 with a delay of (n-1) clocks .

Next, with reference to FIGS. 7 and 8, a more specific configuration example and operation example of this embodiment will be described.

Referring to FIG. 7, transversal filter 303 has three taps for simplicity, and integrator 4
01 to 403 are configured by counters 41 to 43, and include a test control circuit 230 for supplying a test control signal SD and a test control clock SC, and an input terminal 100 for inputting a control signal for controlling the test control circuit 230, The reset signals of the counters 41 to 43 are transmitted to the shift register 211.
~ 213.

Referring to the timing chart of FIG.
Transversal filter 30 configured as described above
3, the test control signal SD generated by the test control circuit 230 is supplied to the register 211 at the rising edge of the test control clock SC also generated by the test control circuit 230.
Then, the output of the gate circuit 221 is fixed at "1" (fix1), and the counter 41 is reset to start counting.

The output D 1 of the multiplier 51 is supplied to the gate circuit 22.
1 and the output C1 of the counter 41, so that D1 = B1 * C1 = 1 * C1 = C1, the output of the counter 41 becomes the output D1, and the clock CK
The output E1 of the DFF 71 is delayed by one clock.

At this time, the other gate circuits 212 and 213
Is fixed to "0", the outputs D2 and D3 of the multipliers 52 and 53 are output to the counter 4 by the same operation as described above.
It becomes "0" irrespective of the values of the outputs C2 and C3 of 2, 43. Therefore, the adder 62 outputs the output E1 of the DFF 71,
The adder 63 outputs the output E2 of the DFF 72 as it is. Thus, the output of the counter 41 is output from the output terminal 150 to the outside of the filter 303.

At the next rise of the test control clock SC, the output signal A1 of the register 211
And the gate circuit 222 is fixed at "1", and the counter 42 is reset to start counting.

The output D2 of the multiplier 52 is supplied to the gate circuit 22.
2 and the output C2 of the counter 42, so that D2 = B2 * C2 = 1 * C2 = C2, and the output of the counter 42 becomes D2 as it is.

At this time, the next control data (fix0) is taken into the register 211, and the gate circuit 221 is fixed at "0". Therefore, the output of the DFF 71 also becomes “0” with a delay of one clock of the clock CK. For this reason, the output of the adder 62 becomes E1 + D2 for the first two clocks from the rise of the control clock SC, and thereafter, the output of D
2 is output as it is.

As described above, the test control clock S
Registers that fix the output of the gate circuit to "1" are sequentially shifted in synchronization with C, and the output of each counter can be sequentially output to the outside of the filter.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0058]

As described above, according to the digital filter of the present invention, an ordinary signal path can be used without using a test bus in a test circuit. Further, since the control signal is input by the shift register, the number of wirings for the control signal can be reduced. For this reason,
This has the effect of reducing the number of test circuit wirings, preventing an increase in chip area, and improving the degree of integration of the LSI.

Further, since the output of the circuit under test is output using the actual signal path, there is an effect that the test at the actual operation speed is facilitated and the reliability of the LSI can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to a first embodiment of the present invention.

FIG. 2 is a time chart showing an operation at the time of a test of the first embodiment.

FIG. 3 is a block diagram illustrating a more specific configuration example of the first embodiment.

FIG. 4 is a flowchart showing an operation at the time of testing the digital filter of FIG. 3;

FIG. 5 is a block diagram showing a configuration of a digital filter according to a second embodiment of the present invention.

FIG. 6 is a time chart showing an operation at the time of a test in the second embodiment.

FIG. 7 is a block diagram showing a more specific configuration example of the second embodiment.

8 is a flowchart showing an operation of the digital filter of FIG. 7 at the time of a test.

FIG. 9 is a block diagram showing a configuration of a waveform equalizer to which a digital filter is applied.

FIG. 10 is a block diagram illustrating a configuration example of a digital filter.

FIG. 11 is a block diagram showing a configuration of a digital filter equipped with a conventional test circuit.

FIG. 12 is a flowchart showing an operation at the time of testing a conventional digital filter.

[Explanation of symbols]

41-4n counter 51-5n multiplier 61-6n adder 71-7n DFF 80 DFF 90 DFF 201-20n tap 211-21n shift register 221-22n gate circuit 230 test control circuit 241-243 tap 251-25n DFF 261- 26n taps 271 to 273 taps 300, 301, 302, 303 Transversal filters 351 to 35n, 370 to 37n, 380 Delay circuit 401 to 40n Integrator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03H 15/00 H03H 17/02 601 H03H 17/02 681 H03H 17/06 635 H03H 21/00

Claims (6)

(57) [Claims] 1. A wave used in a digital modulation / demodulation technique or the like.
Among digital filters used in a shape equalizer, etc., an integrator for generating a coefficient, and a delay circuit for giving a unit delay to an input signal from a previous stage and outputting a signal given the unit delay to a next stage. And n multipliers each having a multiplier for multiplying an output signal of the delay circuit by a coefficient generated by the integrator are configured by cascade connection,
In a transversal digital filter including a plurality of adders for adding outputs of the taps, each of the n taps is located between the delay circuit and the multiplier. A digital filter comprising test means for taking out the output of an integrator of a predetermined one tap as it is and setting the output of another tap to "0". 2. A test circuit comprising: a gate circuit for fixing an input signal of the multiplier to a predetermined value according to a control signal; and one or more control circuits for storing a control signal for controlling the gate circuit 2. The digital filter according to claim 1, wherein the plurality of registers are connected in series, and have a shift register configuration controlled by a common clock. 3. 3. The digital filter according to claim 2, wherein the integrator is a counter, and a reset signal for the counter is supplied from the register. 4. A wave used in a digital modulation / demodulation technique or the like.
Among digital filters used for the shape equalizer and the like, an integrator for generating a coefficient, a multiplier for multiplying an input signal by a coefficient generated by the integrator, and an output signal of the multiplier.
In a transversal digital filter configured by cascading n taps each including an adder for adding an input signal from the preceding stage and a delay circuit for giving a unit delay to the signal of the adder, , Each of the n taps is located between the input signal and the multiplier, and takes out the output of the integrator of one predetermined tap as it is and outputs the output of the other tap to “ A digital filter comprising a test means for setting 0 ". 5. The test means includes: a gate circuit in which each of the n taps fixes an input signal of the multiplier to a predetermined value according to a control signal; and a control circuit for controlling the gate circuit. One or more registers for storing signals are inserted between the input signal and the multiplier, and the plurality of registers are connected in series and controlled by a common clock. The digital filter according to claim 4, wherein the digital filter has a register configuration. 6. The digital filter according to claim 5, wherein said integrator is a counter, and a reset signal of said counter is supplied from said register.