JPS6074812A - Digital filter - Google Patents

Abstract

PURPOSE:To filter the data having a short sampling cycle by cascading two unit groups in terms of an addition circuit and adding a compensating circuit which delays the input data. CONSTITUTION:Product/sum arithmetic circuits 21, 23 and 25 having taps to which odd-numbered coefficient data h1, h3 and h5 are supplied are cascaded in terms of an adder to form the 1st unit circuit group. While product/sum circuits 22 and 24 having taps to which even-numbered data h2 and h4 are supplied are also cascaded in terms of an adder to form the 2nd unit circuit group. Then the input of addition of the circuit 25 is set at 0, the output of the circuit 21 is used as an input of addition of the circuit 24. The input data supplied to the 1st unit circuit group is delayed via a correcting circuit 31 and then supplied to the 2nd unit circuit group. Then the data is extracted out of the circuit 22. Thus it is possible to form a digital filter by using product/sum circuits and then to filter the data having a short sampling cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Features" The present invention relates to a digital filter constructed using a product-sum operation circuit as a unit.

"Background technology and its problems" The invention is applicable to FIR digital filters.

The FIR digital filter has a sampling period of T,
The input time series is x (nT), and the impulse response (hereinafter,
When hi (referred to as coefficient data) is hi (i=1 to N), an output time series y(nT) having the following relationship is generated.

As a specific configuration of the FIR digital filter.

A transversal type is known in which input data taken out from between register stages is multiplied by a predetermined coefficient and the outputs of a plurality of multiplication products are added. This transversal configuration is not suitable for a configuration in which the same basic circuits are arranged side by side, that is, a configuration in which the hardware can be simplified. Therefore, it is preferable to use a digital filter having a one-transition expansion configuration as shown in FIG.

Another configuration of the F-engine R digital filter.

A memory for storing input data and one multiplier.

Equipped with one adder and a microprocessor.

There is a now stored program system configuration in which the digital filter calculations are performed by a program. This configuration resembles a digital audio signal.

It is used when the operating speed of a digital calculation device is faster than the sampling period. However, when the sampling period and the operating speed of the digital calculation device are similar, such as with digital video signals,
Configuration registration using the stored program method cannot be used.

Therefore, as shown in FIG.
A multiplier 1 is supplied with C, and an adder 2 is supplied with the output of the multiplier 1 and the addition power C.

A digital filter is constructed by connecting a plurality of product-sum calculation circuits 10 in series with respect to the adder 2. configured. The digital filter shown in FIG.

This is the configuration when (Nl=5) taps, and five product-sum operation circuits 11, 12, 13, 14, and 15 are connected in cascade with respect to the adder 2.

Since the product-sum operation circuit has a large gate scale, its propagation delay time is large, and in order to achieve high-speed operation, pipeline processing is not performed. One input A.

Registers 16 and 17 are inserted into the supply path of B, and a register 18 is inserted into the supply path of addition power C.
The product-sum calculation circuit 20 enables high-speed operation.

Consider a case in which a plurality of this kind of product-sum operation circuit 207i: adder 2 are connected in cascade to form a digital filter. Registers 16 and 17 for inputs A and B or registers internal to multiplier 1 (not shown) become delay elements common to all taps of the digital filter. Therefore, the delay caused by the stiff register is fixed and does not cause any inconvenience when constructing a digital filter. However, register No. 18 related to input C, when the product-sum calculation circuits 20 are connected together, Even if they are connected, a problem arises in which filter calculations are not performed correctly. This register 18 is necessary to eliminate the influence of unstable factors such as wiring and ensure reliable operation. In Fig. 4, 21, 23.25 are products having taps to which odd-numbered coefficient data h□+h31 h are respectively supplied. A sum calculation circuit is shown, and 22.degree. 24 is a product-sum calculation circuit having taps to which even-numbered coefficient data h2, h, and kata are respectively supplied.

These product-sum calculation circuits 21 to 25 each receive multiplication inputs c,
: Although it has a corresponding register 16, it is simply omitted. The register 17 contains coefficient data h, ~h5
Since is a predetermined value, it is not necessary that the somatic property 1/7 t
, Ibar This omission of registers 16 and 17 also applies in the following description.

The product-sum calculation circuits 21, 23, and 25 are cascade-connected with respect to the adder, the addition input of the product-sum calculation circuit 25 is set to 0, and the addition output of the product-sum calculation circuit 21 is sent to the adder 27 via the register 26. Supplied. The product-sum calculation circuits 22 and 24 are cascade-connected with respect to the adders g,n.*The addition input of the product-sum calculation circuit 24 is set to 0, and the addition output of the product-sum calculation circuit 22 is connected to the register 28 and the register °.

The output signal is supplied to the adder 27 via the input signal 29. Input data is commonly supplied to all the product-sum calculation circuits 21 to 25, and output data is taken out from the register 30. The registers 26, 28, 29, and 30 are pipeline registers of the adder 27, and are provided to correct a delay difference between the two product-sum operation circuit groups.

It will be explained below that the digital filters shown in FIGS. 1 and 4 are equivalent.

First, the digital filter shown in FIG. 1 will be explained.

The input data passes through one stage of registers before it is multiplied by the coefficient data h1 and outputted.

Input data passes through two stages of registers before being multiplied by coefficient data h2 and output.

Input data passes through three stages of registers before being multiplied by coefficient data h3 and output.

Similarly, input data passes through one stage of registers before being multiplied by coefficient data hi and outputting.

As mentioned above, input data and coefficient data h1 (1-1 to
5) are multiplied by 2 and output by 1 clock.

Next, the digital filter shown in FIG. 4 will be explained.

The input data passes through three stages of registers before it is multiplied by the coefficient data h1 and output.

The input data passes through four stages of registers f before it is multiplied by the coefficient data h2 and output.

The input data passes through five stages of registers until it is multiplied by the coefficient data h3 and output.

Similarly, the input data passes through (i+2) stages of registers before being multiplied with the coefficient data h1 and outputted.

The multiplication results here are all added up in the end, so this is different from the digital filter in Figure 1.

The only difference is that the two-stage register, ie, the fixed delay amount of two clock cycles, increases, and the digital filter Lt shown in FIG. 4 is equivalent to the digital filter shown in FIG. 1.

The digital filter having the configuration shown in FIG. 4 corrects the influence of the register 18 included in each of the product-sum calculation circuits 21 to 25 with a simple circuit configuration (registers 26.2B, 29.30 and adder 27). I can do it.

``Object of the Invention'' This invention provides that when a digital filter is configured using a plurality of product-sum operation circuits having pipeline registers,
The object of the present invention is to provide a digital filter equipped with a correction circuit having a simpler configuration without using an adder circuit.

``Summary of the Invention'' The present invention is a digital filter including a plurality of unit circuits each including one or more product-sum operation circuits each having a pipeline register. This circuit consists of a first unit circuit group formed by cascading a plurality of odd-numbered unit circuits with respect to an adder circuit, a first unit circuit group formed by cascade-connecting a plurality of even-numbered unit circuits with respect to an adder circuit, and a second unit circuit group connected in cascade with respect to the unit circuit group and the adder circuit;

It is characterized by comprising a correction circuit that delays input data supplied from one of the first unit circuit group and the second unit circuit group to the other so that the calculation of the digital filter is performed correctly. .

"Embodiment" An embodiment of the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a (N=5) tap FIR digital filter.

In FIG. 5, 21, 22, 23, 24 and 25 are product-sum operation circuits each having a pipeline register.

Odd-numbered coefficient data hInh3. Product-sum operation circuits 21, 23, and 25 having taps to which h5 is supplied are connected in cascade with respect to the adder to form a first unit circuit group.

Product-sum calculation circuits 22 and 24 having taps that supply even-numbered coefficient data h2+h4 are connected in cascade with respect to the adder to form a second unit circuit group 20〇Product-sum calculation circuit of the first unit circuit group The addition input of 25 is 0, and the output of the product-sum calculation circuit 21 is the product-sum calculation circuit 2 of the second unit circuit group.
Addition input of 4 and '2! nru. Supply p to the first unit circuit group
Correction circuit 3 consisting of five stages of registers
A second unit circuit group is supplied through the second unit circuit 1. Output data is taken out from the product-sum operation circuit 22 of the second unit circuit group.

In one embodiment of the present invention, when the multiplication data of input data and coefficient data hi (i=1 to 5) is output,
It passes through the following stages of registers.

Input data passes through five stages of registers before being multiplied by coefficient data h1 and output.

The input data passes through six stages of registers before being multiplied by the coefficient data h2 and output.

The input data passes through seven stages of registers before being multiplied by coefficient data h3 and output.

Similarly, the input data passes through (1+4) stages of registers before it is multiplied with the coefficient data h1 and outputted.

In this way, in this embodiment, the products obtained by multiplying the input data and each of the coefficient data hi (i=1 to 5) are taken out to the output one clock at a time. Therefore, this embodiment is equivalent to the digital filter shown in FIG.

Of course, the present invention can be applied only when the number of taps N is not 5. FIG. 6 shows a more general configuration of an embodiment P of the present invention. In FIG. 6, 35 is the first unit circuit group.

36 is the second unit circuit group, 37 is the first unit circuit group 35
A coefficient data input 38 is made up of odd-numbered coefficient data that is not supplied to the second unit circuit group 36, and a coefficient data input 38 is made up of even-numbered coefficient data that is supplied to the second unit circuit group 36.

In this embodiment, the coefficient data h1 is defined as (1=1 to N), so the odd-numbered coefficient data is hl +
h3 s hll..., and the even-numbered coefficient data is h2. h, ...... However, when the coefficient data hi is defined as (i=0 to N-1), the odd-numbered coefficient data is the same. , h2. ...Next.

The even-numbered coefficient data becomes, h, . . . .

Furthermore, the first unit circuit group 35 and the second unit circuit group 36 may be connected in the reverse order of this embodiment.

FIG. 7 shows another example of the correction circuit 31. This correction circuit 31 includes a shift register 39 and a selector 40 that selects the number of taps derived from the shift register 39.
The amount of delay can be set by a control signal to the selector 40. The correction circuit 31 having the configuration shown in FIG. 7 is constructed entirely on a common board.
Deori.

Various correction delay amounts can be generated depending on the number of taps and the like.

Another embodiment of the present invention will be described with reference to FIGS. 8 and 9. As shown in FIG. 8, this other embodiment includes product-sum operation circuits 11', 12 .
13.14 are connected in cascade for adder circuits, each with a common input A and separate inputs B'I + B2 * B3 +
The unit circuit is a product-sum arithmetic circuit 50 which supplies the power C to the cascade connection and also supplies the power C to the addition of the cascade connection via the register 18.

A digital filter using, for example, five of these product-sum calculation circuits 50, as shown in FIG. Even-numbered product-sum operation circuits 52 and 54 are cascade-connected to a second unit circuit group in which the adder circuits are cascade-connected, and input data is supplied to the first unit circuit group.

Correction circuit 56'fr: The configuration is completed by supplying the signal to the second unit circuit group via the correction circuit 56'fr.

"Effects of the Invention" According to the present invention, a digital filter can be constructed using a Fn product-sum operation circuit that performs pipeline processing, and it is possible to construct a digital filter using an Fn product-sum operation circuit that performs pipeline processing. It is possible to realize a digital filter that can filter. However, the present invention has the advantage that the configuration of one circuit is simple and only requires adding a correction circuit for correcting the amount of delay.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a digital filter to which the present invention can be applied, FIGS. 2 and 3 are block diagrams showing an example of a product-sum calculation circuit and another example P, and FIG. A block diagram of a digital filter used for explaining this invention, FIG. 5 is a block diagram of an embodiment of this invention, and FIG.
The figure is a block diagram showing the basic configuration of one embodiment of the present invention, FIG. 7 is a block diagram of another example of the correction circuit in one embodiment of the present invention, and FIG. 8 is a block diagram of another example of the correction circuit in one embodiment of the present invention. A block diagram of a unit circuit, FIG. 9 is a block diagram of another embodiment of the present invention. 10-15.20-25.50-55...product-sum calculation circuit, 31.56...correction circuit, 35...
. . . 1st unit circuit group, 36 . . . 2nd unit circuit group. Agent Masato Sugiura

Claims (1)

[Claims] A multiplier to which input data and coefficient data are supplied via a register, and an output of the multiplier and a register via the register.
A digital filter is provided with a plurality of unit circuits consisting of one or more of the following circuits, each consisting of an adder circuit to which the adder signal input is supplied and a register to which the output of the adder circuit is supplied. . a first unit circuit group formed by cascading a plurality of odd-numbered unit circuits with respect to the adder circuit; A plurality of even-numbered unit circuits are connected in cascade with respect to the adder circuit, and a second unit circuit group is further connected in cascade with respect to the first unit circuit group and the adder circuit, and the first unit circuit is connected in cascade with respect to the adder circuit. and a correction plane circuit for delaying the input data supplied from one of the second displacement circuit group to the other so that the calculation of the digital filter is performed correctly. .