JPH05236518A - System for testing high-definition television signal processing circuit - Google Patents

Abstract

PURPOSE:To improve the test efficiency of a high-definition television signal processing circuit. CONSTITUTION:A DFF 3 outputs a high-definition television signal A to a delay adjusting circuit 6A and the subtrahend input of a subtractor 5. A DFF 4 outputs a high-definition television signal B to the minuend input of a subtractor 5. A coefficient device 7 multiplies the output of the subtractor 5 by a coefficient based on the control signal inputted from an input terminal 14 and outputs a signal D. The signal D is inputted to the input (a) of a selector 20 through not only an LPF 8 but also a delay adjusting circuit 18. In accordance with the test signal inputted from an input terminal 15 through a serial bus interface circuit 16, the selector 20 selects the input (a) in the case of normal operation and selects an input (b) in the case of test. The output of the selector 20 is added to the high-definition television signal A outputted from the delay adjusting circuit 6A by an adder 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition signal processing circuit test system, and in particular, it mixes two high-definition input signals by applying a coefficient to each of the two high-definition input signals and subjecting them to low-pass filtering. The present invention relates to a high-definition signal processing circuit test system having a circuit that bypasses a low-pass filtering processing unit in a high-definition signal processing circuit that performs processing and outputs.

[0002]

2. Description of the Related Art As a conventional high-definition signal processing circuit test system, there is a system as shown in FIG.
The high-definition signal processing circuit test system requires extremely high-speed signal processing. For example, the MUSE method which is one of the transmission methods in HDTV has a maximum of 48.
Signal processing at 6 MHz is required. Since very high-speed signal processing is required as described above, sufficient attention must be paid to the formation of a high-definition signal processing circuit test system. For example, even the delay time of the data selector inserted when creating the detour circuit of the data path cannot be ignored.

An example of a conventional high-definition signal processing circuit test system shown in FIG. 5 is a low-frequency replacement circuit test system which is one of the high-definition signal processing circuit test systems. In FIG. 5, the data flip-flop (hereinafter referred to as DFF) 3 outputs the high-definition signal A input from the input terminal 1 to the delay adjustment circuit 6 and the subtraction input of the subtracter 5 in synchronization with the system clock, and the DFF 4 The high-definition signal B input from the input terminal 2 is output to the subtracted input of the subtractor 5 in synchronization with the system clock. HDTV signal B is subtracted by subtractor 5
In, the signal is subtracted from the high-definition signal A and becomes the signal C. The signal C is multiplied by a coefficient based on the control signal input from the input terminal 4 in the coefficient multiplier 7, and becomes a signal D.
A low-pass filter (hereinafter referred to as LPF) 8 extracts only the low-frequency component of the signal D, and then the DFF 17 outputs it as a signal E to the adder 9 in synchronization with the system clock. Entered in the input. Signal E
Is a delay adjustment circuit 6 for subtracter 5, coefficient unit 7, LPF
8 and the high-definition signal A delayed by the same amount as the total delay amount in the DFF 17 are added in the adder 9 and then input to the a input of the selector 11 by the DFF 12 via the limiter 10 in synchronization with the system clock. .. The selector 11 selects the input a in the normal operation and the input b in the test according to the test signal input from the input terminal 15 and connects them to the output terminal 13.

FIG. 6 is a circuit diagram showing an example of the LPF 8. As shown in FIG. 6, the LPF 8 has an input terminal 40, DF
F41A to 41R, adders 42A to 42F, coefficient unit 43
A to 43F and the output terminal 44. DFF
41A to 41C, adders 42A to 42B and coefficient unit 43
A to 43B constitute a third-order LPF, and DFF 41D to 4
1H, adders 42C to 42D and coefficient units 43C to 43D
Constitutes a fifth-order LPF, and the DFFs 41I to 41R, the adders 42E to 42F, and the coefficient units 43E to 43F form a ninth-order LF.
A PF is configured, and a 15th-order LPF is configured as a whole. However, since the coefficient units 43A to 43F can be usually realized by bit shift, they are omitted in practice.

In the conventional high-definition signal processing circuit test system, the operating speed is required to be as high as 48.6 MHz, so that the logic that can be executed by one DFF stage is about two stages, and it is difficult to insert even a selector. Therefore, as a result, a selector is inserted after the DFF 12.

[0006]

However, in the above-described conventional high-definition signal processing circuit test system, only the LPF cannot be bypassed in the original flow of signal processing, so that the subtracter 5 and the coefficient unit 7 cannot be bypassed. Although the test efficiency is improved, the adder 9 is not improved. In image processing, after mounting on a board, judgment is often made while looking at the actual image. However, since the original signal processing is completely impossible at the time of testing with the conventional high-definition signal processing circuit test system, There is a problem that it is impossible to judge while looking at a picture. Furthermore, the conventional high-definition signal processing circuit test system requires a separate test control input terminal.

The present invention has been made in view of the above problems, and it is possible to increase the test efficiency of a high-definition signal processing circuit and evaluate the circuit while viewing an actual image. The purpose is to provide a system.

[0008]

A high-definition signal processing circuit test system according to the present invention performs a low-pass filtering process after multiplying each of two high-definition input signals by a coefficient in response to an external control signal input. In a high-definition signal processing circuit which performs mixed processing and outputs, a first data flip-flop for inputting a first high-definition signal from a first input terminal and a second data flip-flop for inputting a second high-definition signal from a second input terminal Data flip-flop, a subtractor for subtracting the first high-definition signal from the second high-definition signal, and the output signal of the subtractor is multiplied by a coefficient according to the control signal input from the third input terminal. A coefficient unit, a low-pass filtering circuit for low-pass filtering the output signal of the coefficient unit, and a signal for outputting the output signal of the coefficient unit in the low-pass filtering circuit. A first delay adjustment circuit that delays by the same time as the delay time, and an output signal of the low-pass filter circuit and the first delay adjustment circuit according to a control signal input from a fourth input terminal via a serial bus interface circuit. A selection circuit for switching and outputting the output signal of the delay adjustment circuit, and a delay amount of each of the subtractor, the coefficient unit, the low-pass filtering circuit, and the selection circuit for the output signal of the first data flip-flop. Second delay adjusting circuit for delaying the same time as the sum of the above, an adder for adding the output signal of the second delay adjusting circuit and the output signal of the selecting circuit, and a limiter for the output signal of the adder A limiter circuit for processing and a third data flip-flop for outputting an output signal of the limiter circuit to an output terminal are provided.

[0009]

In the high-definition signal processing circuit test system according to the present invention, the coefficient multiplier multiplies each of the first and second high-definition input signals by a coefficient in accordance with the control signal input from the third input terminal. The low-pass filtering circuit performs low-pass filtering processing on the output signal of the coefficient unit. The first delay adjustment circuit is provided in parallel with the low-pass filtering circuit and delays the input signal by the same time as the signal delay time in the low-pass filtering circuit. The selection circuit outputs the output signal of the low-pass filter circuit during the normal operation and the output signal of the first delay adjustment circuit during the test according to the control signal input from the fourth input terminal through the serial bus interface circuit. Is output. With this selection circuit or the like, in the high-definition signal processing circuit test system according to the present invention, the detour circuit can be set without affecting the delay time of the original signal processing circuit, and the test can be performed without destroying the original configuration of the signal processing circuit. Since the system can be constructed, the test efficiency for the HDTV signal processing circuit can be improved.

[0010]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a high-definition signal processing circuit test system according to a first embodiment of the present invention. In FIG. 1, components having the same functions as those of the conventional high-definition signal processing circuit test system shown in FIG. 5 are designated by the same reference numerals.

In the HDTV signal processing circuit test system according to the first embodiment shown in FIG. 1, components different from those of the conventional example shown in FIG. 5 will be described below. A delay adjustment circuit 18 is provided in parallel with the LPF 8, the output of the LPF 8 is connected to the a input of the selector 20, and the delay adjustment circuit 1
The output of 8 is connected to the b input of the selector 20. The control terminal of the selector 20 is connected to the output of the serial bus interface circuit 16 whose input is connected to the input terminal 15, and the output of the selector 20 is connected to the input of the adder 9. The output of the DFF 12 is connected to the output terminal 13.

FIG. 3 is a circuit diagram showing details of the selector 20 in the high-definition signal processing circuit test system according to the embodiment of the present invention. Selector 2 as shown in FIG.
0 is n input terminals 210 to 21n-1, n input terminals 220 to 22n-1, input terminals 23 and 24, and n DFF2.
50 to 25n-1, (nm) DFFs 26m to 26n-1,
n clocked inverters 270 to 27n-1, n clocked inverters 280 to 28n-1, n inverters 290 to 29n-1, inverters 30 to 35 and n output terminals 360 to 36n-1. I have it. Where n and m
Is a natural number having a relationship of [n>m> 0].

The m input terminals 210 to 21m-1 are respectively connected to the m clocked inverters 270 to 27m-1, and the m input terminals 220 to 22m-1 are respectively connected to the m clocked inverters 280 to 280. M m DFFs 250 to 2 through 28m-1
Connected to 5m-1 data input, DFF250 ~ 25m-1
Output is connected to m output terminals 360 to 36m-1 via inverters 290 to 29m-1, so that m D
M types of selectors that are selected before the FF are configured.

Further, (nm) input terminals 21m to 21n
-1 is (nm) DFFs 25n to 25m-1 and (n), respectively.
-M) through the clocked inverters 27m to 27n-1, the (nm) input terminals 22m to 22n-1 are connected to (nm) DFFs 26n to 26m-1 and (n-m), respectively. m) connected to the inverters 29m to 29n-1 via the clocked inverters 28m to 28n-1, and the inverters 29m to 29n.
The output of -1 is connected to the (n-m) output terminals 36m to 36n-1 to form a (n-m) set of selectors of the type that selects data after the DFF.

Next, the operation of the high-definition signal processing circuit test system according to the first embodiment constructed as described above will be described. The DFF 3 outputs the high-definition signal A input from the input terminal 1 to the delay adjustment circuit 6A and the subtraction input of the subtractor 5 in synchronization with the system clock, and the DFF 4 subtracts the high-definition signal B input from the input terminal 2 from the subtractor. It outputs to the subtracted input of 5 in synchronization with the system clock. HDTV signal B is subtracted by subtractor 5
In, the signal is subtracted from the high-definition signal A and becomes the signal C. The signal C is multiplied by a coefficient based on the control signal input from the input terminal 14 in the coefficient unit 7, and becomes a signal D. The signal D is input to the LPF 8 and the delay adjustment circuit 18 at the same time. Signal D input to LPF8
Is the signal E by extracting only the low frequency component and the selector 2
0 is input to the a input. The signal D input to the delay adjustment circuit 18 is delayed by the same time as the signal D is delayed in the LPF 8 and input to the b input of the selector 20. The signal E is supplied to the subtractor 5 by the delay adjusting circuit 6A.
The high-definition signal A delayed by the delay adjusting circuit 6A is added by the adder 9 by the same amount as the sum of the delay amounts in the coefficient unit 7, the LPF 8 and the selector 20, and then added to the system clock by the DFF 12 via the limiter 10. Is output to the output terminal 13. The selector 20 receives an input a during normal operation in response to a test signal input from the input terminal 15 via the serial bus interface circuit 16.
, And input b is selected during the test.

FIG. 4 is a graph showing the delay time when the selector shown in FIG. 3 is inserted between two stages of adders. The delay time of the adder is the time from when the lowest full adder generates a carry and when the carry propagates to generate the sum signal at the highest order. Therefore, the lower the bit, the data output to the DFF clock. There is a margin in the time until the rise, and conversely, the higher the bit, the margin in the time from the rise of the DFF clock to the data input of the adder.

Therefore, from the data output of the adder to the DF of the next stage
There is leeway in the time required for the F clock to rise m-
Select up to the first bit before inputting DFF
By selecting m bits or more after the output of DFF from which the time from the output of F to the input of the adder of the next stage has a margin after DFF output, the bypass circuit can be inserted without affecting the delay time of the signal processing circuit.

Also, in the first embodiment, the control of the high-definition signal processing circuit test system is performed via the serial bus. In the MUSE system, which is one of the high-definition signal processing circuits, a 3-wire type serial bus is used for system control. In the first embodiment, the test control input can be shared with the serial bus. Not only that, in the first embodiment, only the LPF can be bypassed from the signal processing system. Therefore, after constructing the high-definition signal processing circuit, the actual mode is set by setting the test mode via the serial bus. You can evaluate the circuit while watching.

FIG. 2 is a block diagram showing a high-definition signal processing circuit test system according to a second embodiment of the present invention. In the HDTV signal processing circuit test system according to the second embodiment, the components different from those of the first embodiment shown in FIG. 1 can control the delay amount of the delay adjusting circuit 6A shown in FIG. 1 by a serial bus. This is a portion replaced with the delay adjustment circuit 6B. As a result, when testing,
By setting the delay amount of the signal A to be smaller by the LPF, it is possible to perform signal processing that bypasses only the LPF without the delay adjustment circuit 18 required in the first embodiment.

[0021]

As described above, according to the high-definition signal processing circuit test system of the present invention, a low-pass filtering process is performed by multiplying each of the two high-definition input signals by a coefficient in response to an external control signal input. In a high-definition signal processing circuit that performs post-mixing processing and outputs, n sets of data input terminals, n sets of selectors, and n sets of data flip-flops are used as selection circuits for setting a bypass circuit for the low-pass filtering circuit. And n sets of output terminals,
The lower m bits of the bit input signal are selected and then output through the data flip-flop, and the upper nm bits of the signal are processed through the data flip flop and then selected. As a result, in the high-definition signal processing circuit test system according to the present invention, the detour circuit can be set without affecting the delay time of the original signal processing circuit, and the test system can be constructed without destroying the original configuration of the signal processing circuit. Therefore, it is possible to improve the test efficiency for the high-definition signal processing circuit.

Further, in the high-definition signal processing circuit test system according to the present invention, the control of the high-definition signal processing circuit test system is performed using the same serial bus as that used in the high-definition signal processing system. At the time of system construction, the test control input can be shared with the input of the serial bus, and it becomes possible to bypass only the LPF from the signal processing system. By setting the test mode via the serial bus, the circuit Can be evaluated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a high-definition signal processing circuit test system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a high-definition signal processing circuit test system according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing details of a selector in the high-definition signal processing circuit test system according to the embodiment of the present invention.

FIG. 4 is a graph showing a delay time when the selector shown in FIG. 3 is inserted between two stages of adders.

FIG. 5 is a block diagram showing an example of a conventional high-definition signal processing circuit test system.

6 is a block diagram showing details of the low-pass filter circuit shown in FIG. 5. FIG.

[Explanation of symbols]

 3, 4 and 12; Data flip-flop 5; Subtractor 6A, 6B, 18; Delay adjustment circuit 7; Coefficient unit 8; Low-pass filter circuit 9; Adder 10; Limiter 16; Serial bus interface circuit 20; Selector

Claims (3)

[Claims] 1. A high-definition signal processing circuit for outputting a low-pass filtering process after multiplying each of two high-definition input signals by a coefficient according to a control signal input from the outside, and then performing a mixing process to output the first input signal. A first data flip-flop for inputting a first high-definition signal from a terminal, a second data flip-flop for inputting a second high-definition signal from a second input terminal, and the first data flip-flop for inputting a second high-definition signal Subtractor for subtracting the high-definition HD signal, a coefficient unit for multiplying the output signal of this subtractor by a coefficient according to the control signal input from the third input terminal, and a low-pass filtering process for the output signal of this coefficient unit. Low-pass filtering circuit
According to a first delay adjusting circuit that delays the output signal of the coefficient unit by the same time as the signal delay time in the low-pass filtering circuit, and a control signal input from the fourth input terminal through the serial bus interface circuit. Selecting circuit for switching and outputting the output signal of the low-pass filtering circuit and the output signal of the first delay adjusting circuit, and the output signal of the first data flip-flop for the subtractor, the coefficient unit, A second delay adjusting circuit that delays by the same amount of time as the total of the delay amounts of the low-pass filtering circuit and the selecting circuit, and an output signal of the second delay adjusting circuit and an output signal of the selecting circuit are added. A limiter circuit for limiting the output signal of the adder, and a third data flip-flop for outputting the output signal of the limiter circuit to an output terminal. HDTV signal processing circuit test system, characterized in that it comprises. 2. The low-pass filtering circuit has a plurality of data flip-flops and a plurality of adders, and the output of one of the plurality of adders is the output of the low-pass filtering circuit. The selection circuit has n sets of data input terminals, n sets of selectors, n sets of data flip-flops, and n output terminals, and an n-bit input signal input from the n sets of data input terminals. The lower m bits of the signals are subjected to a selection process through the m sets of selectors in the n sets of selectors, and then the n number of the data flip-flops in the n sets of data flip-flops. The signal of the upper (n−m) bits of the n-bit input signal output from the m output terminals of the output terminals is
(N−m) in the n sets of data flip-flops
The data is input to the (n−m) sets of selectors in the n sets of selectors via the set of data flip-flops, selection processing is performed, and output from the (n−m) output terminals of the n output terminals. The high-definition signal processing circuit test system according to claim 1, wherein: 3. The second delay adjustment circuit is externally controlled in delay amount via the serial bus interface circuit, and the first delay control circuit is not required. The high-definition signal processing circuit test system described in 2.