JPS627750B2 - - Google Patents

Info

Publication number
JPS627750B2
JPS627750B2 JP56203712A JP20371281A JPS627750B2 JP S627750 B2 JPS627750 B2 JP S627750B2 JP 56203712 A JP56203712 A JP 56203712A JP 20371281 A JP20371281 A JP 20371281A JP S627750 B2 JPS627750 B2 JP S627750B2
Authority
JP
Japan
Prior art keywords
circuit
signal
outputs
ghost
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56203712A
Other languages
Japanese (ja)
Other versions
JPS57123772A (en
Inventor
Yoshizumi Eto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56203712A priority Critical patent/JPS57123772A/en
Publication of JPS57123772A publication Critical patent/JPS57123772A/en
Publication of JPS627750B2 publication Critical patent/JPS627750B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H04N5/211Ghost signal cancellation

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Noise Elimination (AREA)

Description

【発明の詳細な説明】 本発明はゴースト除去装置、すなわち、テレビ
ジヨン信号の如き画像信号において、本来の画像
信号の他に、一定時間遅れた、正極性、逆極性の
画像信号が発生し、いわゆるゴースト画像が生じ
る。この一定時間遅れのゴースト成分を除去する
装置に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a ghost removal device, that is, in an image signal such as a television signal, in addition to the original image signal, image signals of positive polarity and reverse polarity that are delayed by a certain period of time are generated. A so-called ghost image occurs. The present invention relates to a device for removing ghost components delayed by a certain period of time.

テレビジヨン信号などを受信すると第1図に示
すようなゴーストを伴なう場合がある。すなわ
ち、振幅1のインパルス信号があつた際に、時間
τだけ遅れて振幅a1(i=1,2,……)のゴ
ーストが生じる。
When a television signal or the like is received, ghosts as shown in FIG. 1 may occur. That is, when an impulse signal with an amplitude of 1 is received, a ghost with an amplitude a 1 (i=1, 2, . . . ) occurs with a delay of time τ 1 .

第2図に公知のフイードバツク形ゴースト除去
装置を示す。端子1の入力信号中の垂直帰線期間
中に含まれるステツプ信号から、微分回路2によ
り第1図に示したインパルス応答が求まる。イン
パルス応答のうちゴースト成分のみがシフトレジ
スタ3に供給され、遅れ時間τに対応した段に
振幅a1が記憶される。一方、出力端子4の信号は
シフトレジスタ5に供給され、シフトレジスタ
3,5の各段の値の積がかけ算回路6J(J=
a,…,x,y,z)で得られ、たし算回路7で
その総和が得られる。入力信号とたし算回路7の
出力の差がひき算回路8で得られゴーストを除去
された出力信号となる。上記の公知例において
は、たとえばかけ算回路6Jに非直線歪がある
と、ゴーストを正確に除去できない欠点がある。
したがつて、本発明の目的は上述の如き従来のゴ
ースト除去装置を改良し、各回路に非線形歪があ
つても最終的には正しくゴーストを除去できる装
置を実現することである。
FIG. 2 shows a known feedback type ghost removal device. The impulse response shown in FIG. 1 is determined by the differentiating circuit 2 from the step signal included in the vertical retrace period of the input signal to the terminal 1. Only the ghost component of the impulse response is supplied to the shift register 3, and the amplitude a 1 is stored in the stage corresponding to the delay time τ 1 . On the other hand, the signal at the output terminal 4 is supplied to the shift register 5, and the product of the values of each stage of the shift registers 3 and 5 is the multiplication circuit 6J (J=
a, . . . , x, y, z), and the addition circuit 7 obtains the sum. The difference between the input signal and the output of the addition circuit 7 is obtained by the subtraction circuit 8, resulting in an output signal from which ghosts have been removed. In the above-mentioned known example, if the multiplication circuit 6J has non-linear distortion, for example, there is a drawback that ghosts cannot be accurately removed.
Therefore, an object of the present invention is to improve the conventional ghost removal apparatus as described above, and to realize an apparatus that can ultimately correctly remove ghosts even if each circuit has nonlinear distortion.

本発明は上記目的を達成するため、ゴースト除
去装置を、画像信号と、ゴースト成分からなる第
1信号とを入力し、この両信号を合成することに
よつて上記画像信号からゴースト成分の除去され
た第2画像信号を出力する手段と、この第2画像
信号を入力し、この信号中に含まれるゴースト成
分のインパルス応答の累積値を係数として上記第
1信号を出力するトランスバーサルフイルタとで
構成したことを特徴とする。
In order to achieve the above object, the present invention inputs an image signal and a first signal consisting of a ghost component to a ghost removal device, and removes the ghost component from the image signal by combining both signals. and a transversal filter that receives the second image signal and outputs the first signal using the cumulative value of the impulse response of the ghost component included in the signal as a coefficient. It is characterized by what it did.

以下実施例によつて、本発明を詳細に説明す
る。第3図は本発明によるゴースト除去装置の一
実施例の構成を示すブロツク図である。同図にお
いて、第2図と同一機能の回路は同一符号を付し
てある。第2図の例と異なり、出力信号中のステ
ツプ信号より微分回路2でインパルス応答を得
る。インパルス応答のうち、ゴースト成分の各時
刻の値はスイツチ回路9で累積回路10J(J=
a,……,x,y,z)に供給される。累積回路
は現在の入力値とこれまでの出力値の和を新しい
出力値とするものである。累積回路の出力とシフ
トレジスタ5の出力値の各段の積の総和をかけ算
回路6J、たし算回路7より得、入力信号との差
をひき算回路8で得て出力信号とする。本発明に
おいては、かけ算回路の出力信号が正しいゴース
トに対応せず、出力端子4にゴーストが残留した
場合でも、その残留ゴーストのインパルス応答が
累積回路10Jに再び与えられるために、最終的
には残留ゴーストは0となる。すなわち、累積回
路の入力は0で、各段の出力がa1となり定常状態
となる。
The present invention will be explained in detail below with reference to Examples. FIG. 3 is a block diagram showing the configuration of one embodiment of the ghost removal device according to the present invention. In this figure, circuits having the same functions as those in FIG. 2 are given the same reference numerals. Unlike the example shown in FIG. 2, an impulse response is obtained by the differentiating circuit 2 from the step signal in the output signal. Of the impulse response, the value of the ghost component at each time is determined by the switch circuit 9 and the accumulation circuit 10J (J=
a, ..., x, y, z). The accumulator circuit uses the sum of the current input value and previous output values as a new output value. The sum of the products of each stage of the output of the accumulation circuit and the output value of the shift register 5 is obtained from a multiplication circuit 6J and an addition circuit 7, and the difference with the input signal is obtained from a subtraction circuit 8, which is used as an output signal. In the present invention, even if the output signal of the multiplication circuit does not correspond to a correct ghost and a ghost remains at the output terminal 4, the impulse response of the residual ghost is given again to the accumulation circuit 10J, so that the final The remaining ghost will be 0. That is, the input to the accumulator circuit is 0, and the output of each stage is a1 , resulting in a steady state.

第3図において累積回路10Jの出力を一度シ
フトレジスタ3に供給し、第2図のようにかけ算
回路に供給してもよい。何故ならば、シフトレジ
スタ3,5、かけ算回路6J、たし算回路7は通
常トランスバーサルフイルタと呼ばれ1チツプに
集積化しやすいからである。
In FIG. 3, the output of the accumulation circuit 10J may be supplied once to the shift register 3, and then supplied to the multiplication circuit as shown in FIG. This is because the shift registers 3 and 5, multiplication circuit 6J, and addition circuit 7 are usually called transversal filters and can be easily integrated into one chip.

第4図は本発明によるゴースト除去装置の他の
実施例の構成を示す図で、同図において第2図、
第3図と同一機能の回路は同一符号を付してあ
る。本実施例においては、シフトレジスタ3の最
終出力と微分回路2の出力とをたし算回路11で
加算し、シフトレジスタ3の入力とする。この場
合には、1個のたし算回路でシフトレジスタ3に
累積値a1が得られ、構成が容易になると同時に、
上述のような集積化にも適している長所がある。
FIG. 4 is a diagram showing the configuration of another embodiment of the ghost removal device according to the present invention, in which FIG.
Circuits having the same functions as those in FIG. 3 are given the same reference numerals. In this embodiment, the final output of the shift register 3 and the output of the differentiator circuit 2 are added together by an adder circuit 11, and the result is input to the shift register 3. In this case, the cumulative value a 1 can be obtained in the shift register 3 with one addition circuit, and at the same time, the configuration becomes easy.
It has the advantage of being suitable for integration as described above.

また、シフトレジスタ3がアナログ形で、長時
間後には保持値が減衰する場合でも、第4図の実
施例に示すように巡回させておけば、微分回路2
より減衰を補正する値が自動的に供給される長所
もある。
Furthermore, even if the shift register 3 is an analog type and the held value attenuates after a long period of time, if the shift register 3 is circulated as shown in the embodiment of FIG.
Another advantage is that a value that further corrects attenuation is automatically supplied.

上記実施例の回路は、入出力端子1および4の
信号をアナログ信号にすれば、アナログ回路に、
又、デイジタル信号にすれば、デイジタル回路と
なる。
The circuit of the above embodiment can be converted into an analog circuit by converting the signals of input/output terminals 1 and 4 into analog signals.
Moreover, if it is converted into a digital signal, it becomes a digital circuit.

また、入出力信号がアナログ信号であつても、
シフトレジスタ3、累積回路10などの保持時間
を長くするために、この部分のみデイジタル回路
とし、その前後に、A/DあるいはD/A変換器
を設置することも可能である。
Also, even if the input/output signals are analog signals,
In order to lengthen the holding time of the shift register 3, the accumulation circuit 10, etc., it is also possible to make only these parts digital circuits and install A/D or D/A converters before and after them.

以上述べたように、本発明によれば、ゴースト
除去装置内の非線形回路の精度を緩和することが
できるという効果を有する。
As described above, according to the present invention, it is possible to reduce the accuracy of the nonlinear circuit in the ghost removal device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はゴースト信号の説明のための波形図、
第2図は従来のゴースト除去装置の構成を示す回
路図、第3図および第4図はいずれも、本発明に
よる、ゴースト除去装置の実施例の構成を示す回
路図である。 1……入力端子、4……出力端子、2……微分
回路、3,5……シフトレジスタ、6……かけ算
器、7,8……加算器、8……減算器、9……ス
イツチ回路、10……累積回路。
Figure 1 is a waveform diagram for explaining the ghost signal.
FIG. 2 is a circuit diagram showing the configuration of a conventional ghost removal device, and FIGS. 3 and 4 are both circuit diagrams showing the configuration of an embodiment of the ghost removal device according to the present invention. 1...Input terminal, 4...Output terminal, 2...Differentiating circuit, 3, 5...Shift register, 6...Multiplier, 7, 8...Adder, 8...Subtractor, 9...Switch Circuit, 10...cumulative circuit.

Claims (1)

【特許請求の範囲】 1 画像信号と、ゴースト成分からなる第1信号
とを入力し、この両信号を合成することによつて
上記画像信号からゴースト成分の除去された第2
画像信号を出力する手段と、 この第2画像信号を入力し、この信号中に含ま
れるゴースト成分のインパルス応答の累積値を係
数として上記第1信号を出力するトランスバーサ
ルフイルタとからなることを特徴とするゴースト
除去装置。 2 特許請求の範囲第1項において、前記トラン
スバーサルフイルタは、前記第2画像信号を入力
し、各段毎にその値を出力するシフトレジスタ
と、前記第2画像信号に含まれるゴースト成分の
インパルス応答を出力する第1回路と、この第1
回路からのインパルス応答の各時刻の値を各段毎
に累積して出力する第2回路と、上記シフトレジ
スタ及び第2回路の各段の値の積をそれぞれ出力
する第3回路と、この第3回路の出力の総和を前
記第1信号として出力する第4回路とからなるこ
とを特徴とするゴースト除去装置。 3 特許請求の範囲第2項において、前記累積回
路は、前記インパルス応答の各時刻の値の累積値
を入力し、各段毎にその値を出力するシフトレジ
スタと、このシフトレジスタの最終段の値と前記
第1回路からのインパルス応答の値とを加算して
上記累積値を出力するたし算回路とからなること
を特徴とするゴースト除去装置。
[Claims] 1. A second signal from which the ghost component has been removed from the image signal by inputting an image signal and a first signal consisting of a ghost component and combining both signals.
It is characterized by comprising means for outputting an image signal, and a transversal filter that receives the second image signal and outputs the first signal using the cumulative value of the impulse response of the ghost component included in the signal as a coefficient. Ghost removal device. 2. In claim 1, the transversal filter includes a shift register that inputs the second image signal and outputs the value at each stage, and an impulse of a ghost component included in the second image signal. a first circuit that outputs a response;
a second circuit that accumulates and outputs the values at each time of the impulse response from the circuit for each stage; a third circuit that outputs the product of the values of each stage of the shift register and the second circuit; and a fourth circuit that outputs the sum of the outputs of the three circuits as the first signal. 3. In claim 2, the accumulation circuit includes a shift register that inputs the cumulative value of the impulse response at each time and outputs the value at each stage, and a final stage of the shift register. A ghost removal device comprising: an addition circuit that adds the value and the value of the impulse response from the first circuit and outputs the cumulative value.
JP56203712A 1981-12-18 1981-12-18 Ghost elimination device Granted JPS57123772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56203712A JPS57123772A (en) 1981-12-18 1981-12-18 Ghost elimination device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56203712A JPS57123772A (en) 1981-12-18 1981-12-18 Ghost elimination device

Publications (2)

Publication Number Publication Date
JPS57123772A JPS57123772A (en) 1982-08-02
JPS627750B2 true JPS627750B2 (en) 1987-02-19

Family

ID=16478595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56203712A Granted JPS57123772A (en) 1981-12-18 1981-12-18 Ghost elimination device

Country Status (1)

Country Link
JP (1) JPS57123772A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166447U (en) * 1988-05-10 1989-11-21

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994017600A1 (en) * 1993-01-19 1994-08-04 Ntt Mobile Communications Network Inc. Method for removing interference wave, receiver and communication system which use the method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227975A (en) * 1975-08-26 1977-03-02 Toyoda Mach Works Ltd Programmed feed control device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227975A (en) * 1975-08-26 1977-03-02 Toyoda Mach Works Ltd Programmed feed control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166447U (en) * 1988-05-10 1989-11-21

Also Published As

Publication number Publication date
JPS57123772A (en) 1982-08-02

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