JPS63179541A - Evaluation of semiconductor element - Google Patents

Evaluation of semiconductor element

Info

Publication number
JPS63179541A
JPS63179541A JP1005787A JP1005787A JPS63179541A JP S63179541 A JPS63179541 A JP S63179541A JP 1005787 A JP1005787 A JP 1005787A JP 1005787 A JP1005787 A JP 1005787A JP S63179541 A JPS63179541 A JP S63179541A
Authority
JP
Japan
Prior art keywords
electrode
oxide film
wiring metals
currents
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1005787A
Other languages
Japanese (ja)
Inventor
Tsuneo Ajioka
味岡 恒夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1005787A priority Critical patent/JPS63179541A/en
Publication of JPS63179541A publication Critical patent/JPS63179541A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To facilitate the analysis of a minute region, by measuring currents flowing through a plurality of wiring metals, which are attached on an electrode, and detecting a place, where the currents are generated in the electrode. CONSTITUTION:An oxide film 2 is formed on a semiconductor substrate. An electrode (gate electrode) 3 is formed on the oxide film 2. Field oxide films 12 are formed on both sides of the gate electrode 3. Thereafter, wiring metals 13 are individually contacted with the four corners of the gate electrode 3 so that pads are formed on the field oxide film 12. Ammeters 14-17 are individually connected to the wiring metals 13. The wiring metals 14-17 are grounded through the ammeters 14-17. Then currents through the wiring metals 13 are measured. Thus the generation of the currents in the electrode 3 is detected. In this way the analysis and clarification of the minute region of the electrode can be made easy.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はMO8型半導体又はショットキを半導体素子の
評価法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for evaluating MO8 type semiconductor or Schottky semiconductor devices.

(従来の技術) 従来、この種の評価法は特開昭54−102978号公
報及び特開昭54−26667号公報に開示されるもの
がある。
(Prior Art) Conventionally, this type of evaluation method is disclosed in Japanese Patent Application Laid-open No. 54-102978 and Japanese Patent Application Laid-open No. 54-26667.

以下、この評価法を、第4図(イ)及び(ロ)に基づい
て説明する。先ず、第4図(イ)はMOSキャノンター
のリーク電流の評価法を説明する断面図である。
This evaluation method will be explained below based on FIGS. 4(a) and 4(b). First, FIG. 4(A) is a cross-sectional view illustrating a method for evaluating leakage current of a MOS canontor.

即ち、半導体基板1上にその一部を酸化させて酸化膜2
を形成した後、該酸化膜2上にf−上電極3を形成して
MOSキャパシターを形成する。更に、該電極3に電源
4を接続し、前記基板lは電流計5を介して接地する。
That is, a part of the semiconductor substrate 1 is oxidized to form an oxide film 2.
After forming, an f- upper electrode 3 is formed on the oxide film 2 to form a MOS capacitor. Further, a power source 4 is connected to the electrode 3, and the substrate 1 is grounded via an ammeter 5.

而して、前記電源4によシミ極3に電圧を印加し乍ら、
前記電流計5により酸化膜2を通して基板lに通電する
リーク電流を測定していた。次に、第4図(ロ)はMo
sトランジスタの酸化膜2に基板1よす電子や正孔がア
バランシェ注入される際、酸化膜2を介して通電する電
流の評価法を説明する断面図である。即ち、半導体基板
1上に酸化膜2及び電極3を順次形成して成るMOSキ
ャパシターの両側にソース領域6とドレイン領域7とを
形成し、前記基板1とト。
While applying voltage to the stain electrode 3 from the power source 4,
The ammeter 5 was used to measure the leakage current flowing to the substrate 1 through the oxide film 2. Next, Figure 4 (b) shows Mo
FIG. 2 is a cross-sectional view illustrating a method for evaluating the current flowing through the oxide film 2 when electrons and holes from the substrate 1 are avalanche-injected into the oxide film 2 of the s-transistor. That is, a source region 6 and a drain region 7 are formed on both sides of a MOS capacitor formed by sequentially forming an oxide film 2 and an electrode 3 on a semiconductor substrate 1, and the substrate 1 and the drain region 7 are connected to each other.

レイン領域7とに電源8と9とを夫々接続すると共に、
前記ソース領域6を接地し且つ酸化膜2も電流計10を
介して接地する。斯くして、前記電源8及び9によりド
レイン領域7と基板1とに電圧を印加すると、ソース領
域とげレイン領域との間に掛かる電圧により基板1内に
形成される空乏層11において、アバランシェ現象によ
る電子と正孔とのペアができる。これによって、生起さ
れる電流を酸化膜2を介して前記電流計10によシ検出
していた。
While connecting power supplies 8 and 9 to the rain region 7, respectively,
The source region 6 is grounded, and the oxide film 2 is also grounded via an ammeter 10. In this way, when a voltage is applied between the drain region 7 and the substrate 1 by the power supplies 8 and 9, the depletion layer 11 formed in the substrate 1 due to the voltage applied between the source region and the drain region is caused by an avalanche phenomenon. A pair is created between an electron and a hole. As a result, the current generated is detected by the ammeter 10 through the oxide film 2.

(発明が解決しようとする問題点〕 然し乍ら、従来の半導体素子の評価法においては、ダー
ト電極3に入った全ての電流を測定していたので、該電
流の発生箇所が把握できず、微小領域の分析ができなか
った。その九め、電流発生に係る原因究明や機構の解析
ができないという問題点があった。
(Problems to be Solved by the Invention) However, in the conventional semiconductor device evaluation method, all of the current that entered the dart electrode 3 was measured, so the location where the current was generated could not be ascertained, and Ninth, there was a problem in that it was not possible to investigate the cause or analyze the mechanism related to current generation.

本発明の目的は上述の問題点に鑑み、半導体素子の微小
領域よp発生する電流の測定ができる半導体素子評価法
を提供するものである。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device evaluation method that can measure the current generated in a minute region of a semiconductor device.

(問題点を解決するための手段) 本発明は上述の目的を達成するため、半導体基板1の電
極3上に複数の配線金属13を取シ付け、該各配線金属
13の電流を測定することにより前記電極3内の電流の
発生箇所を検知するものである。
(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention includes mounting a plurality of wiring metals 13 on the electrode 3 of the semiconductor substrate 1 and measuring the current of each wiring metal 13. This is to detect the location where the current is generated within the electrode 3.

(作用) 本発明においては、複数の配線金属を流れる電流を個別
に測定して、該電流の発生箇所の検知をするので、電極
の微小領域の分析解明が容易にされる。
(Function) In the present invention, the currents flowing through a plurality of wiring metals are individually measured and the locations where the currents are generated are detected, thereby facilitating the analysis and elucidation of minute regions of the electrodes.

(実施例) 以下、本発明に係る一実施例を従来例と同一構成部分に
は同一符号を付して図面に基づいて説明する。第1図は
半導体素子での測定方法を説明する断面図であシ、第2
図は半導体素子での測定方法を説明する平面図及び第3
図は測定方法の原理を示す説明図である。
(Embodiment) Hereinafter, an embodiment of the present invention will be described based on the drawings, with the same components as those of the conventional example being denoted by the same reference numerals. Figure 1 is a cross-sectional view illustrating the measurement method for semiconductor devices.
The figure is a plan view and a third
The figure is an explanatory diagram showing the principle of the measurement method.

即ち、半導体素子の評価法は、半導体基板1上に酸化膜
2を形成し、該酸化膜2上に電極(y−計電極)3を形
成する。次いで、該ダート電極3の両側にフィールド酸
化膜12を形成し友後、配線金属13を前記f−1電極
3の四方に個別に接触させると共に、前記フィールド酸
化膜12上において、/々ラッド成る如く形成する。そ
の際、r−計電極3は配線金属13よシも抵抗値の高い
ものが望ましく、一般的には、r−計電極3にはリンド
ーグポリシリコンが使用され、配線金属13にはアルミ
配線が用いられる。又、配線金属13の各々には電流計
14.15,16.17を個別に接続し、前記各配線金
属13は電流計14.15゜16.17を介して夫々接
地させる。
That is, in the method for evaluating a semiconductor element, an oxide film 2 is formed on a semiconductor substrate 1, and an electrode (y-meter electrode) 3 is formed on the oxide film 2. Next, a field oxide film 12 is formed on both sides of the dirt electrode 3, and then wiring metal 13 is brought into contact with each of the four sides of the f-1 electrode 3, and on the field oxide film 12, a metal layer 12 is formed on each side. form like this. In this case, it is desirable that the r-meter electrode 3 has a higher resistance value than the wiring metal 13. Generally, Lindog polysilicon is used for the r-meter electrode 3, and aluminum wiring is used for the wiring metal 13. is used. Furthermore, ammeters 14.15 and 16.17 are individually connected to each of the wiring metals 13, and each of the wiring metals 13 is grounded through the ammeters 14.15 and 16.17, respectively.

従って、例えば、第2図に示す如く、r−計電極3のX
点においてリークが起つ九とする。この場合、X点から
各配線金属13までの距離を4+11.4+ ’4とし
、更に、その抵抗をRt 、& 、 Rs 、 R4と
し、f−)電極3の比抵抗をρGとすると、R1” I
dGll(1) R,oc pG4               (2
)& ocpG/a               (
3)&■−〇!4               (4
)の各式が成立する。よって、Q) 、 (2) 、 
(3) 、 (4)式よシ抵抗R8,烏、 R,、R4
は距離/、 、 /オe z、 a 14に比例する。
Therefore, for example, as shown in FIG.
Assume that the leak occurs at point 9. In this case, if the distance from point X to each wiring metal 13 is 4+11.4+'4, and the resistance is Rt, &, Rs, R4, and the specific resistance of f-) electrode 3 is ρG, then R1'' I
dGll(1) R,oc pG4(2
) & ocpG/a (
3)&■-〇! 4 (4
) holds true. Therefore, Q), (2),
(3), (4) Resistance R8, R,, R4
is proportional to the distance /, , /oez,a14.

又、配線金属13の抵抗をrl l rl m rl 
t r4とし、配線金属13の比抵抗ρmとr−計電極
3の比抵抗ρGとの間に、 ρ贋くρG(5) の関係が成立すれば、(5)式より次式が成立する。
Also, the resistance of the wiring metal 13 is rl l rl m rl
If t r4 is established between the specific resistance ρm of the wiring metal 13 and the specific resistance ρG of the r-meter electrode 3, then the following equation holds from equation (5). .

f、 Qll l”、#vr3−r4−Q      
     (6)而して、各配線金属13中を通電する
電流をil。
f, Qll l", #vr3-r4-Q
(6) Then, the current flowing through each wiring metal 13 is il.

t、 111 s t4とすると、 11+ it + is + it冨1(7)Rs i
s ” R11! = Rs fa = & it  
       (8)が成立する。斯くして、(1) 
e (2) 、 (3) 、 (4) 、 (6) 、
 (7) 。
t, 111 s t4, then 11+ it + is + it wealth 1 (7) Rs i
s ” R11! = Rs fa = & it
(8) holds true. Thus, (1)
e (2), (3), (4), (6),
(7).

(8)式よシ次式が成り立つ。Equation (8) holds the following equation.

1+ it = lx is = Is i、−= /
414(9)よって、i、 s it l t、 a 
14の値を電流計14.15゜16.17により測定し
て、(9)式よシl!t t t、 14 #ムを求め
れば、X点が特定できる。この様にして、r−)電極3
内の微小領域の分析解明が可UKなる。
1+ it = lx is = Is i, -= /
414(9) Therefore, i, s it l t, a
The value of 14 is measured using an ammeter 14.15°16.17, and the formula (9) is expressed as ! If t t t, 14 #m is calculated, the X point can be specified. In this way, r-) electrode 3
It becomes possible to analyze and elucidate minute areas within the area.

(発明の効果) 以上説明した様に本発明によれば、電極上に取シ付けた
複数の配線金属を流れる電流を測定して、電極内の電流
の発生箇所を検知するので、微小領域の分析ができるた
め、リーク電流発生の原因究明や耐圧等の機構の解明が
できる等により前記の問題を解決し得る。
(Effects of the Invention) As explained above, according to the present invention, the current flowing through a plurality of wiring metals attached to the electrode is measured and the location where the current is generated within the electrode is detected. Since analysis is possible, the above-mentioned problems can be solved by investigating the cause of leakage current generation and elucidating mechanisms such as withstand voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明に係る一実施例を示すもので
、第1図は本発明方法を説明する断面図第2図は本発明
方法を説明する平面図、第3図は本発明方法の原理を示
す説明図、第4図(イ)及び(=−)は従来方法を説明
する断面図である。 1・・・半導体基板、3・・・電極(f−上電極)、1
3・・・配線金属。 本党縛眉f:左説明15モ92
1 to 3 show one embodiment of the present invention. FIG. 1 is a cross-sectional view explaining the method of the present invention. FIG. 2 is a plan view explaining the method of the present invention. FIGS. 4A and 4B are cross-sectional views illustrating the conventional method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Electrode (f-upper electrode), 1
3... Wiring metal. Main party bound eyebrow f: left explanation 15mo 92

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の電極上に複数の配線金属を取り付け、該各
配線金属の電流を測定することにより前記電極内の電流
の発生箇所を検知することを特徴とする半導体素子評価
法。
1. A method for evaluating a semiconductor device, comprising: attaching a plurality of wiring metals on an electrode of a semiconductor substrate; and detecting a location where a current is generated in the electrode by measuring the current of each wiring metal.
JP1005787A 1987-01-21 1987-01-21 Evaluation of semiconductor element Pending JPS63179541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1005787A JPS63179541A (en) 1987-01-21 1987-01-21 Evaluation of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1005787A JPS63179541A (en) 1987-01-21 1987-01-21 Evaluation of semiconductor element

Publications (1)

Publication Number Publication Date
JPS63179541A true JPS63179541A (en) 1988-07-23

Family

ID=11739758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1005787A Pending JPS63179541A (en) 1987-01-21 1987-01-21 Evaluation of semiconductor element

Country Status (1)

Country Link
JP (1) JPS63179541A (en)

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