JPS63178346U - - Google Patents
Info
- Publication number
- JPS63178346U JPS63178346U JP7040587U JP7040587U JPS63178346U JP S63178346 U JPS63178346 U JP S63178346U JP 7040587 U JP7040587 U JP 7040587U JP 7040587 U JP7040587 U JP 7040587U JP S63178346 U JPS63178346 U JP S63178346U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- header
- element holding
- hold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図乃至第４図は本考案半導体装置の一つの
実施例を説明するためのもので、第１図は断面図
、第２図は分解斜視図、第３図は製造に用いるリ
ードフレームの斜視図、第４図は半導体装置の従
来例の一を示す分解斜視図である。
符号の説明、１……ヘツダー、２…リード、３
……半導体素子保持リード、５……半導体素子、
６……抜け止め用突起、７……曲折部。
1 to 4 are for explaining one embodiment of the semiconductor device of the present invention. FIG. 1 is a sectional view, FIG. 2 is an exploded perspective view, and FIG. 3 is a lead frame used for manufacturing. FIG. 4 is an exploded perspective view showing a conventional example of a semiconductor device. Explanation of symbols, 1...Header, 2...Lead, 3
...Semiconductor element holding lead, 5...Semiconductor element,
6... Retention protrusion, 7... Bent portion.
Claims (1)
する半導体素子保持リードと、半導体素子を保持
しないリードとが貫通状に併設された半導体装置
であつて、 上記半導体素子保持リードのヘツダー内の部分
の外側面に抜け止め用突起が一体に形成され、 上記半導体素子を保持しないリードのヘツダー
内の上記抜け止め用突起と対応する部分が上記半
導体素子保持リードとの間隔を一定に保つように
曲折されてなる ことを特徴とする半導体装置。[Scope of Claim for Utility Model Registration] A semiconductor device in which a header made of an insulating material is provided with a semiconductor element holding lead that holds a semiconductor element and a lead that does not hold a semiconductor element in a penetrating manner, the semiconductor element holding lead as described above. A retaining protrusion is integrally formed on the outer surface of a portion inside the header of the lead, and a portion of the lead that does not hold the semiconductor element that corresponds to the retaining protrusion in the header maintains a constant distance from the semiconductor element holding lead. 1. A semiconductor device characterized by being bent so as to maintain its shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040587U JPS63178346U (en) | 1987-05-12 | 1987-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040587U JPS63178346U (en) | 1987-05-12 | 1987-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63178346U true JPS63178346U (en) | 1988-11-18 |
Family
ID=30912010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7040587U Pending JPS63178346U (en) | 1987-05-12 | 1987-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63178346U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310889A (en) * | 2006-08-01 | 2006-11-09 | Matsushita Electric Ind Co Ltd | Method of manufacturing chip-type semiconductor laser device |
-
1987
- 1987-05-12 JP JP7040587U patent/JPS63178346U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310889A (en) * | 2006-08-01 | 2006-11-09 | Matsushita Electric Ind Co Ltd | Method of manufacturing chip-type semiconductor laser device |
| JP4569537B2 (en) * | 2006-08-01 | 2010-10-27 | パナソニック株式会社 | Manufacturing method of chip-type semiconductor laser device |