JPS63178345U - - Google Patents
Info
- Publication number
- JPS63178345U JPS63178345U JP7040487U JP7040487U JPS63178345U JP S63178345 U JPS63178345 U JP S63178345U JP 7040487 U JP7040487 U JP 7040487U JP 7040487 U JP7040487 U JP 7040487U JP S63178345 U JPS63178345 U JP S63178345U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element support
- support lead
- lead
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000011810 insulating material Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図乃至第４図は本考案半導体装置の一つの
実施例を説明するためのもので、第１図は断面図
、第２図は第１図の２−２線に沿う断面図、第３
図は分解斜視図、第４図は半導体装置の製造に使
用するリードフレームの斜視図、第５図は本考案
半導体装置の変形例を示す断面図、第６図は従来
例を示す分解斜視図である。
符号の説明、１……ヘツダー、２……リード、
２ａ……半導体素子支持リード、４……半導体素
子。
1 to 4 are for explaining one embodiment of the semiconductor device of the present invention, in which FIG. 1 is a sectional view, FIG. 2 is a sectional view taken along line 2-2 in FIG. 1, and FIG. 3
The figure is an exploded perspective view, FIG. 4 is a perspective view of a lead frame used for manufacturing a semiconductor device, FIG. 5 is a sectional view showing a modified example of the semiconductor device of the present invention, and FIG. 6 is an exploded perspective view showing a conventional example. It is. Explanation of symbols, 1...Header, 2...Lead,
2a...Semiconductor element support lead, 4...Semiconductor element.
Claims (1)
ードを含む複数本のリードが貫通状に保持され、 上記半導体素子支持リードの上端側の部分が該
リードの裏面側に折り曲げられ、更にその折り曲
げられた部分が折り返され、その折り返された部
分の先端部が該半導体素子支持リードの裏面に固
定され、 上記半導体素子支持リードの上端部に半導体素
子が固定されてなる ことを特徴とする半導体装置。[Claim for Utility Model Registration] A header made of an insulating material holds a plurality of leads including a semiconductor element support lead in a penetrating manner, and the upper end portion of the semiconductor element support lead is bent toward the back side of the lead. , the bent portion is further folded back, the tip of the folded portion is fixed to the back surface of the semiconductor element support lead, and the semiconductor element is fixed to the upper end of the semiconductor element support lead. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040487U JPS63178345U (en) | 1987-05-12 | 1987-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040487U JPS63178345U (en) | 1987-05-12 | 1987-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63178345U true JPS63178345U (en) | 1988-11-18 |
Family
ID=30912008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7040487U Pending JPS63178345U (en) | 1987-05-12 | 1987-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63178345U (en) |
-
1987
- 1987-05-12 JP JP7040487U patent/JPS63178345U/ja active Pending