JPS63177573A - Superconducting transistor - Google Patents

Superconducting transistor

Info

Publication number
JPS63177573A
JPS63177573A JP62008182A JP818287A JPS63177573A JP S63177573 A JPS63177573 A JP S63177573A JP 62008182 A JP62008182 A JP 62008182A JP 818287 A JP818287 A JP 818287A JP S63177573 A JPS63177573 A JP S63177573A
Authority
JP
Japan
Prior art keywords
electron
semiconductor layer
superconducting
layer
increased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62008182A
Other languages
Japanese (ja)
Other versions
JP2651143B2 (en
Inventor
Mutsuko Hatano
睦子 波多野
Juichi Nishino
西野 壽一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62008182A priority Critical patent/JP2651143B2/en
Publication of JPS63177573A publication Critical patent/JPS63177573A/en
Application granted granted Critical
Publication of JP2651143B2 publication Critical patent/JP2651143B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Inorganic Compounds Of Heavy Metals (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce the noise and realize a high speed operation and a high gain by a method wherein a device is operated while it is maintained at a temperature not higher than 77K and an electromagnetic wave such as a light, an ultraviolet ray, an infrared radiation, and an X-ray is applied to control the characteristics. CONSTITUTION:A device is maintained at a cryogenic condition (4.2K) in liquid helium and a light signal 8 with a wavelength of 632.8 nm is applied through an optical fiber 11. By this light application, an exciting phenomenon is induced in an electron supplying layer 3 and the surface electron concentration and the electron mobility of secondary electron gas are increased. Therefore, superconducting electron pairs penetrate into a semiconductor channel layer 2 from source and drain electrodes 5 and 6 which are superconductors and a superconducting current flows between the source and drain electrodes. On the other hand, the resistances between the source and a gate and between the gate and the drain are reduced and the cut-off frequency of the transistor is increased and the noise level is declined. Moreover, the switching speed, expressed by a time constant, is also increased. The increased electrons are maintained even if the application of the electromagnetic wave is discontinued as long as the temperature is maintained at as low as 77K or lower.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は極低温で動作する超伝導トランジスタに係り、
特に電磁波を照射してトランジスタ特性を調整するのに
好適な超伝導トランジスタに関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a superconducting transistor that operates at extremely low temperatures;
In particular, the present invention relates to a superconducting transistor suitable for adjusting transistor characteristics by irradiating electromagnetic waves.

〔従来の技術〕[Conventional technology]

従来の半導体分野で開発されている高電子移動度トラン
ジスタは、特開昭56−94779号及び特開昭57−
7165号公報に記載されており、第5図に示すような
構造をもっている。このトランジスタは、半絶縁性半導
体基板1上に成長させた電子親和力の大きな半導体層(
チャネル層)2と、その上に成長させた電子親和力の小
さな半導体層(fl!子供給層)3とにより形成される
一つのへテロ接合の近傍の半導体層3側に生じる電子蓄
積層(二次元電子ガス)4の電子濃度を制御電極7に印
加する電圧で制御して、制御電極7を挟んで設けたソー
ス電極5とドレイン電極6の間に電子蓄積層4に−よっ
て形成される導電路のインピーダンスを制御するもので
ある。ソース、ドレイン電極5,6は通常、金・ゲルマ
ニウム/金などの材料からなり。
High electron mobility transistors that have been developed in the conventional semiconductor field are disclosed in Japanese Patent Application Laid-open No. 56-94779 and Japanese Patent Application Laid-open No. 57-
It is described in Japanese Patent No. 7165 and has a structure as shown in FIG. This transistor consists of a semiconductor layer (with high electron affinity) grown on a semi-insulating semiconductor substrate 1.
An electron storage layer (two layers) formed on the semiconductor layer 3 side near one heterojunction formed by a channel layer) 2 and a semiconductor layer (fl! child supply layer) 3 with a small electron affinity grown thereon. The electron concentration of the dimensional electron gas) 4 is controlled by the voltage applied to the control electrode 7, and the conductivity is formed by the electron storage layer 4 between the source electrode 5 and the drain electrode 6, which are provided with the control electrode 7 in between. This controls the impedance of the path. The source and drain electrodes 5 and 6 are usually made of a material such as gold/germanium/gold.

蒸着などによって形成するが、形成後に450℃程度の
熱処理を施して電子供給層3を貫通してチャネル層2の
上部まで合金化して合金化層lOを形成し、これを介し
てソース、ドレイン電極5,6とチャネル層2を接続し
ている。
It is formed by vapor deposition, etc., but after formation, it is heat-treated at about 450°C to penetrate through the electron supply layer 3 and alloy up to the upper part of the channel layer 2 to form an alloyed layer IO, and through this, the source and drain electrodes are formed. 5 and 6 and the channel layer 2 are connected.

一方、超伝導体と半導体を組み合せた超伝導トランジス
タについては、ティー・ディー・クランク(T、 D、
 C1ank)によってジャーナル・オブ・アプライド
・フィジックス、51巻、 2736頁(1980年)
 (Journal of Applied Phys
ics)において論じられている。このトランジスタは
、半導体層に接して設けられた2つの超伝導電極間に流
れる超伝導電流の値を該両電極間に設けた制御電極に印
加した電圧によって超伝導近接効果を変化させて制御す
るものである。
On the other hand, regarding superconducting transistors that combine superconductors and semiconductors, T.D. Crank (T, D,
Journal of Applied Physics, Volume 51, Page 2736 (1980)
(Journal of Applied Phys.
ics). This transistor controls the value of superconducting current flowing between two superconducting electrodes provided in contact with a semiconductor layer by changing the superconducting proximity effect using a voltage applied to a control electrode provided between the two electrodes. It is something.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来技術における高電子移動度トランジスタにおいては
、蓄積電子群(二次元電子ガス)の電子濃度は制御電極
7に電圧を印加すると増大するという効果は有するが、
ペテロ接合近傍に存在するイオン化された不純物にもと
づく不純物散乱に影響される。電子親和力の小さな半導
体層、すなわち電子供給層3に含有される不純物による
散乱の影響を低減して電子移動度を大きくするには、電
子蓄積層4の電子面積濃度を増加する、つまり、電子供
給層3の不純物濃度を大きくすればよい。
In the conventional high electron mobility transistor, the electron concentration of the stored electron group (two-dimensional electron gas) increases when a voltage is applied to the control electrode 7, but
It is affected by impurity scattering due to ionized impurities present near the Peter junction. In order to increase electron mobility by reducing the influence of scattering due to impurities contained in the semiconductor layer with low electron affinity, that is, the electron supply layer 3, the electron areal concentration of the electron storage layer 4 is increased, that is, the electron supply layer 3 The impurity concentration of layer 3 may be increased.

しかし、電子供給層3の不純物濃度を大きくすると、合
金化層10形成時の高温熱処理工程などによってチャネ
ル層2中に拡散する不純物濃度も増大するので、結果と
してチャネル層2中の不純物散乱の影響が大きくなり、
電子移動度は低下する。
However, when the impurity concentration of the electron supply layer 3 is increased, the impurity concentration diffused into the channel layer 2 due to the high temperature heat treatment process etc. during the formation of the alloyed layer 10 also increases, resulting in the influence of impurity scattering in the channel layer 2. becomes larger,
Electron mobility decreases.

そのため電子供給層3中の不純物濃度を無制限に大きく
することができず、時定数(1/CR)が小さくなり、
遮断周波数が低下し、雑音の影響を受けやすいという欠
点があった。したがって、デバイスのスイッチング速度
の高速化、利得の高利得化は困難であるという問題があ
った。
Therefore, the impurity concentration in the electron supply layer 3 cannot be increased indefinitely, and the time constant (1/CR) becomes small.
The drawback was that the cutoff frequency was lower and it was more susceptible to noise. Therefore, there has been a problem in that it is difficult to increase the switching speed and increase the gain of the device.

一方、超伝導近接効果を用いた超伝導トランジスタを作
製する際には、半導体基板上に一定の距離Qだけ離して
対向させた一対の超伝導電極を設け、この対向部間に制
御電極を設けている。このような素子構造では、上記距
離円は半導体中のコヒーレンス長さξの5〜10倍の約
0.3−以下に選ぶ必要があり、したがって、このよう
な素子は作製上の問題点があった。また、制御電極の容
量が大きくなり、高速化、高利得化が困難であった。
On the other hand, when fabricating a superconducting transistor using the superconducting proximity effect, a pair of superconducting electrodes facing each other with a certain distance Q apart is provided on a semiconductor substrate, and a control electrode is provided between the opposing parts. ing. In such an element structure, the distance circle needs to be selected to be approximately 0.3- or less, which is 5 to 10 times the coherence length ξ in the semiconductor, and therefore, such an element has problems in manufacturing. Ta. Furthermore, the capacitance of the control electrode becomes large, making it difficult to achieve high speed and high gain.

本発明の目的は、上記問題点を解決し、高スィッチング
速度、高利得特性を有する超伝導トランジスタを提供す
ることにある。
An object of the present invention is to solve the above problems and provide a superconducting transistor having high switching speed and high gain characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、半絶縁性半導体基板上に形成された第1の
半導体層と、該第1の半導体層上に所定の幅で形成され
、該第1の半導体層より電子親和力の小さな第2の半導
体層と、該第2の半導体層の両側に露出している前記第
1の半導体層上に形成された超伝導体膜からなるソ、−
ス電極およびドレイン電極と、該ソース電極およびドレ
イン電極の間の前記第2の半導体層上に形成された超伝
導体膜からなるゲート電極とからなる超伝導素子であっ
て、該素子を77に以下の温度に保持した状態で動作さ
せ前記ゲート電極に光、紫外線、赤外線。
The above object includes a first semiconductor layer formed on a semi-insulating semiconductor substrate, and a second semiconductor layer formed on the first semiconductor layer with a predetermined width and having a smaller electron affinity than the first semiconductor layer. - A semiconductor layer comprising a semiconductor layer and a superconductor film formed on the first semiconductor layer exposed on both sides of the second semiconductor layer.
77. A superconducting element comprising a source electrode, a drain electrode, and a gate electrode made of a superconductor film formed on the second semiconductor layer between the source electrode and the drain electrode. The gate electrode is operated while being maintained at a temperature below, and the gate electrode is exposed to light, ultraviolet rays, and infrared rays.

X線等の電磁波を照射して特性を制御することによって
達成される。
This is achieved by controlling the characteristics by irradiating electromagnetic waves such as X-rays.

〔作用〕[Effect]

電子親和力の異なる2種の半導体からなる層の間の界面
にはポテンシャルバリヤが発生するので、電子はその界
面近傍に滞留して電子蓄積層(2次元電子ガス)を発生
させる。この電子蓄積層の電子移動度は、不純物散乱効
果が小さくなる低温において大きい値を示す。室温から
液体ヘリウム温度(4,2K)に冷却すると、100倍
以上の改善がみられる。この様子を第゛4図に示す。同
図から。
Since a potential barrier is generated at the interface between layers made of two types of semiconductors having different electron affinities, electrons stay near the interface and generate an electron storage layer (two-dimensional electron gas). The electron mobility of this electron storage layer exhibits a large value at low temperatures where the impurity scattering effect becomes small. Cooling from room temperature to liquid helium temperature (4.2 K) shows an improvement of more than 100 times. This situation is shown in Figure 4. From the same figure.

300に→77に→5K(液体ヘリウム温度)に冷却す
ると、同じ電子濃度における電子移動度は増大する。一
方、電子供給層に波長637.anmの光を照射すると
、照射エネルギによって電子供給層中で励起現象が発生
し、電子蓄積層中の電子面濃度の増加を促がす。増加し
た電子は電磁波の照射を停止した後も約77に以下の低
温である限り保持される。この様子を第3図に示す、電
子濃度が増加すれば導電路の抵抗は減少し、結果として
、回路の時定数を減少し、遮断周波数を高くし、雑音を
低減できる。
When cooling from 300 to 77 to 5K (liquid helium temperature), the electron mobility increases at the same electron concentration. On the other hand, the electron supply layer has a wavelength of 637. When irradiated with amm light, an excitation phenomenon occurs in the electron supply layer due to the irradiation energy, promoting an increase in the electron surface concentration in the electron storage layer. Even after the electromagnetic wave irradiation is stopped, the increased electrons are retained as long as the temperature remains below 77°C. This situation is shown in FIG. 3. As the electron concentration increases, the resistance of the conductive path decreases, and as a result, the time constant of the circuit can be decreased, the cut-off frequency can be increased, and the noise can be reduced.

〔実施例〕〔Example〕

以下、本発明を実施例に基き詳細に説明する。 Hereinafter, the present invention will be explained in detail based on Examples.

第1図は本発明の第1の実施例である超伝導トランジス
タの断面図である。図において、1はクロム(Cr)等
を含有する半絶縁性の砒化ガリウム(GaAs)からな
る基板であり、2はこの上に結晶格子整合させて形成さ
れ、極低温において機能する不純物を実質的に含有しな
い(不純物濃度l XIO”an−”以下)砒化ガリウ
ム(GaAs)の単結晶層であり、チャネル層を構成し
、3はチャネル層2上に結晶格子整合させて形成された
n型のアルミニウムガリウム砒素(An GaAs)層
からなる単結晶層であり、電子供給層を構成する。本実
施例においては、電子供給層3のn型不純物濃度は2 
X 10” am−”であり、チャネル層2と電子供給
層3の厚さはそれぞれ600nmと1100nである。
FIG. 1 is a sectional view of a superconducting transistor which is a first embodiment of the present invention. In the figure, 1 is a substrate made of semi-insulating gallium arsenide (GaAs) containing chromium (Cr), etc., and 2 is a substrate made of semi-insulating gallium arsenide (GaAs), which is formed on this by crystal lattice matching, and substantially eliminates impurities that function at extremely low temperatures. (Impurity concentration l This is a single crystal layer made of aluminum gallium arsenide (An GaAs) and constitutes an electron supply layer. In this example, the n-type impurity concentration of the electron supply layer 3 is 2.
X 10"am-", and the thicknesses of the channel layer 2 and electron supply layer 3 are 600 nm and 1100 nm, respectively.

この結晶プロファイルにおいては、ヘテロ接合界面近傍
に電子面濃度が3XIQ11an−”である電子蓄積層
(二次元電子ガス)4が発生する。5,6は所定幅の電
子供給層3を挟んでチャネル層2上に形成され、超伝導
体であるNb膜からなる入出力電極(ソース、ドレイン
電極)であり、これらと電子蓄積層4はオーミック的に
接続されている。
In this crystal profile, an electron storage layer (two-dimensional electron gas) 4 with an electron surface concentration of 3XIQ11an-'' is generated near the heterojunction interface. These are input/output electrodes (source and drain electrodes) formed on Nb film, which is a superconductor, and are ohmically connected to the electron storage layer 4.

7はソース、ドレイン電極5,6間の電子供給層3上に
設けられたNb膜からなる制御電極(ゲート電極)であ
り、ショットキバリヤゲートとして機能する。制御電極
7は光ファイバ11で送られてきた光信号8を透過しう
る程度の厚さを有する必要があり、本実施例のNb膜の
場合、1100n以下である。
Reference numeral 7 denotes a control electrode (gate electrode) made of a Nb film provided on the electron supply layer 3 between the source and drain electrodes 5 and 6, and functions as a Schottky barrier gate. The control electrode 7 must have a thickness sufficient to transmit the optical signal 8 sent through the optical fiber 11, and in the case of the Nb film of this embodiment, the thickness is 1100 nm or less.

以上の構造を有する素子を液体ヘリウム中の極低温(4
,2K)に保持し、制御電極7に光ファイバ11を用い
て波長632.anmの光信号8を入射する。
The device with the above structure was placed in liquid helium at an extremely low temperature (4
, 2K), and using the optical fiber 11 as the control electrode 7, the wavelength 632. An optical signal 8 of amm is input.

この光照射により電子供給層3中において励起現象が発
生し、二次元電子ガスの電子面濃度と電子移動度とが増
大する。このため、超伝導体であるソース、ドレイン電
極5,6から半導体のチャネル層2中に超伝導電子対が
染み出し、ソース、ドレイン電極5,6間に超伝導電流
が流れる。言い換えれば、電子面濃度と電子移動度が増
大したことにより、半導体層中の超伝導電子存在確率が
大きくなる。一方、ソース、ゲート間、ゲート、ドレイ
ン間の抵抗は減少し、このトランジスタの遮断周波数が
上昇し、雑音レベルが低下する。また、時定数で効く、
スイッチング速度も速くなる。この効果は約77に以下
の低い温度に保持されているかぎり、十分長時間維持さ
れる。
This light irradiation causes an excitation phenomenon in the electron supply layer 3, increasing the electron surface concentration and electron mobility of the two-dimensional electron gas. Therefore, superconducting electron pairs leak out from the source and drain electrodes 5 and 6 which are superconductors into the semiconductor channel layer 2, and a superconducting current flows between the source and drain electrodes 5 and 6. In other words, as the electron surface concentration and electron mobility increase, the probability of superconducting electrons existing in the semiconductor layer increases. On the other hand, the resistance between source and gate and between gate and drain decreases, increasing the cut-off frequency of this transistor and lowering the noise level. Also, it works with a time constant,
Switching speed is also faster. This effect is maintained for a sufficiently long time as long as the temperature is kept low, below about 77°C.

第2図は本発明の第2の実施例である超伝導トランジス
タの断面図である。本実施例では第1図に示した素子に
おいて、電子供給層3と超伝導電極5,6が接触する界
面に絶縁膜9を設けたものである。この絶縁膜9は電子
供給層3の自己酸化膜で、その厚さは20nmである。
FIG. 2 is a sectional view of a superconducting transistor which is a second embodiment of the present invention. In this embodiment, an insulating film 9 is provided at the interface where the electron supply layer 3 and the superconducting electrodes 5 and 6 are in contact with each other in the device shown in FIG. This insulating film 9 is a self-oxidized film of the electron supply layer 3, and its thickness is 20 nm.

このような構造をもった超伝導素子は、半導体層を介し
てソース5、ドレイン6間を流れる電流は、チャネルM
2のみを通る。したがって、効率が上り、利得も向上す
る。
In a superconducting element having such a structure, a current flowing between the source 5 and the drain 6 via the semiconductor layer flows through the channel M.
Pass only through 2. Therefore, efficiency is increased and gain is also improved.

つぎに、本発明の超伝導トランジスタの製造方法につい
て説明するeCr等をドープした半絶縁性のG a A
 s単結晶基板1上に不純物濃度lXl017■−3以
下の低キャリヤ濃度を有するチャネル層2としてのGa
As層を約60On−の厚さに形成する。
Next, the method for manufacturing the superconducting transistor of the present invention will be explained using semi-insulating G a A doped with eCr etc.
Ga as a channel layer 2 having an impurity concentration lXl017■-3 or lower carrier concentration on a single crystal substrate 1
An As layer is formed to a thickness of about 60 On-.

その上にn型の不純物を有する厚さ1100nのAl2
XGa1−xAs (x =0.3)層よりなる電子供
給層3を形成する。以上の工程は、モレキュラービーム
・エピタキシャル(MBE)成長法によって形成するこ
とができる。ついで、電子供給層3を所定の幅だけ残し
て、その両側をチャネル層2に達するまでプラズマエツ
チング法を用いて除去する。ここで、第2図に示した本
発明の第2の実施例に示した構造の素子の場合、残存し
ている電子供給層3の両側に熱酸化法によって厚さ約2
0nmの絶縁膜9を形成する。続いて、先のエツチング
工程で除去した電子供給層部分に厚さ1100nのNb
膜からなる電極5,6を蒸着法により形成し、チャネル
層2とオーミック的に接続し、ソース、ドレイン電極5
,6を形成する。最後に、電子供給層3上にショットキ
接合を介して厚さ1100nのNbよりなる制御電極7
を形成した。このようにして本発明のトランジスタを製
造した。
1100n thick Al2 with n-type impurities on it
An electron supply layer 3 made of an XGa1-xAs (x = 0.3) layer is formed. The above steps can be formed by a molecular beam epitaxial (MBE) growth method. Then, leaving a predetermined width of the electron supply layer 3, both sides thereof are removed by plasma etching until the channel layer 2 is reached. In the case of the device having the structure shown in the second embodiment of the present invention shown in FIG.
An insulating film 9 with a thickness of 0 nm is formed. Next, Nb with a thickness of 1100 nm is etched on the electron supply layer that was removed in the previous etching process.
Electrodes 5 and 6 made of films are formed by a vapor deposition method, are ohmically connected to the channel layer 2, and are connected to the source and drain electrodes 5.
, 6. Finally, a control electrode 7 made of Nb with a thickness of 1100 nm is placed on the electron supply layer 3 via a Schottky junction.
was formed. In this manner, the transistor of the present invention was manufactured.

以上の実施例では光源として発光ダイオードを用いたが
、この代りに半導体レーザを用いてもよい。また、超伝
導材料としては、Nbを用いたが、NbN、Nb3Ge
、Nb、Sn、Nb5AQ等のNb化合物、BaLaC
uOなとの超伝導体あるいはpb−Au、Pb−In−
Au、Pb−B1等のpb金合金有機物を含む有機超伝
導体、などを用いた場合でも同様の効果が得られる。
In the above embodiments, a light emitting diode was used as the light source, but a semiconductor laser may be used instead. In addition, although Nb was used as the superconducting material, NbN, Nb3Ge
, Nb, Sn, Nb compounds such as Nb5AQ, BaLaC
Superconductors such as uO or pb-Au, Pb-In-
Similar effects can be obtained even when an organic superconductor containing a pb gold alloy organic material such as Au or Pb-B1 is used.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電子蓄積層の電子面濃度を十分に大き
くでき、不純物散乱の影響を増大することなく電子移動
度が増加するので、超伝導電流は効果的に流れ、わずか
な電磁波の照射によって、この電流を制御できる超伝導
トランジスタを提供でき、また導電路の抵抗を小さくで
きるので、このトランジスタの遮断周波数は上昇し、雑
音が低減でき、高速、高利得化されるなどの効果がある
According to the present invention, the electron surface concentration of the electron storage layer can be sufficiently increased, and the electron mobility increases without increasing the influence of impurity scattering, so superconducting current flows effectively and only a small amount of electromagnetic wave irradiation is required. This makes it possible to provide a superconducting transistor that can control this current, and also to reduce the resistance of the conductive path, which increases the cutoff frequency of this transistor, reduces noise, and increases speed and gain. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の超伝導トランジスタの実施例
の断面図、第3図は本発明の超伝導トランジスタの電子
供給層に光信号を照射した場合の電子濃度対光照射量の
関係を示すグラフ、第4図は本発明の超伝導トランジス
タにおいて、光照射した場合と照射しない場合における
温度をパラメータとした電子移動度対電子面濃度の関係
を示すグラフ、第5図は従来の高電子移動度トランジス
タの断面図である。 図において、 1・・・半絶縁性半導体基板 2・・・チャネル層3・
・・電子供給層     4・・・電子蓄積層5・・・
ソース電極     6・・・ドレイン電極7・・・制
御電極      8・・・光信号9・・・絶縁膜  
     10・・・合金化層11・・・光ファイバ 代理人弁理士  中 村 純之助 才1図 第3図 面濃渡(cm−2)
Figures 1 and 2 are cross-sectional views of embodiments of the superconducting transistor of the present invention, and Figure 3 shows the electron concentration versus light irradiation amount when an optical signal is irradiated to the electron supply layer of the superconducting transistor of the present invention. FIG. 4 is a graph showing the relationship between electron mobility and electron surface concentration using temperature as a parameter in the case of light irradiation and in the case of no irradiation in the superconducting transistor of the present invention. FIG. FIG. 2 is a cross-sectional view of a high electron mobility transistor. In the figure, 1... Semi-insulating semiconductor substrate 2... Channel layer 3.
...Electron supply layer 4...Electron storage layer 5...
Source electrode 6...Drain electrode 7...Control electrode 8...Optical signal 9...Insulating film
10... Alloyed layer 11... Optical fiber agent Junnosuke Nakamura 1 Figure 3 Nowata (cm-2)

Claims (1)

【特許請求の範囲】 1、半絶縁性の半導体基板上に形成された第1の半導体
層と該第1の半導体層上に所定の幅で形成され、該第1
の半導体層より電子親和力の小さな第2の半導体層と該
第2の半導体層の両側に露出している前記第1の半導体
層上に形成された超伝導体膜からなるソース電極および
ドレイン電極と該ソース電極およびドレイン電極の間の
前記第2の半導体層上に形成された超伝導体膜からなる
ゲート電極とからなる超伝導素子であって、該素子を7
7K以下の温度に保持した状態で前記ゲート電極に電磁
波を照射しうるようになっていることを特徴とする超電
導トランジスタ。 2、特許請求の範囲第1項記載の超伝導トランジスタに
おいて、前記ソース電極およびドレイン電極が前記第2
の半導体層と絶縁膜を介して接していることを特徴とす
る超伝導トランジスタ。 3、特許請求の範囲第1項または第2項記載の超伝導ト
ランジスタにおいて、前記ゲート電極は前記電磁波に対
して透過性を有することを特徴とする超伝導トランジス
タ。
[Claims] 1. A first semiconductor layer formed on a semi-insulating semiconductor substrate; and a first semiconductor layer formed on the first semiconductor layer with a predetermined width;
a second semiconductor layer having a smaller electron affinity than the semiconductor layer; and a source electrode and a drain electrode made of a superconductor film formed on the first semiconductor layer exposed on both sides of the second semiconductor layer. a gate electrode made of a superconductor film formed on the second semiconductor layer between the source electrode and the drain electrode;
A superconducting transistor characterized in that the gate electrode can be irradiated with electromagnetic waves while being maintained at a temperature of 7K or less. 2. In the superconducting transistor according to claim 1, the source electrode and the drain electrode are connected to the second
A superconducting transistor characterized by being in contact with a semiconductor layer via an insulating film. 3. A superconducting transistor according to claim 1 or 2, wherein the gate electrode is transparent to the electromagnetic waves.
JP62008182A 1987-01-19 1987-01-19 Superconducting transistor Expired - Lifetime JP2651143B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62008182A JP2651143B2 (en) 1987-01-19 1987-01-19 Superconducting transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62008182A JP2651143B2 (en) 1987-01-19 1987-01-19 Superconducting transistor

Publications (2)

Publication Number Publication Date
JPS63177573A true JPS63177573A (en) 1988-07-21
JP2651143B2 JP2651143B2 (en) 1997-09-10

Family

ID=11686164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62008182A Expired - Lifetime JP2651143B2 (en) 1987-01-19 1987-01-19 Superconducting transistor

Country Status (1)

Country Link
JP (1) JP2651143B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123486A (en) * 1987-11-06 1989-05-16 Mitsubishi Electric Corp Superconducting device
JP2004119821A (en) * 2002-09-27 2004-04-15 Fujitsu Ltd Forming method of ohmic electrode

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893378A (en) * 1981-11-30 1983-06-03 Fujitsu Ltd Manufacture of semiconductor device
JPS5893377A (en) * 1981-11-30 1983-06-03 Fujitsu Ltd Semiconductor device
JPS59103389A (en) * 1982-12-04 1984-06-14 Nippon Telegr & Teleph Corp <Ntt> Superconductive element and manufacture thereof
JPS6135574A (en) * 1984-07-27 1986-02-20 Hitachi Ltd Superconductive phototransistor
JPS61171179A (en) * 1985-01-24 1986-08-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor coupled superconductive element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893378A (en) * 1981-11-30 1983-06-03 Fujitsu Ltd Manufacture of semiconductor device
JPS5893377A (en) * 1981-11-30 1983-06-03 Fujitsu Ltd Semiconductor device
JPS59103389A (en) * 1982-12-04 1984-06-14 Nippon Telegr & Teleph Corp <Ntt> Superconductive element and manufacture thereof
JPS6135574A (en) * 1984-07-27 1986-02-20 Hitachi Ltd Superconductive phototransistor
JPS61171179A (en) * 1985-01-24 1986-08-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor coupled superconductive element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123486A (en) * 1987-11-06 1989-05-16 Mitsubishi Electric Corp Superconducting device
JP2004119821A (en) * 2002-09-27 2004-04-15 Fujitsu Ltd Forming method of ohmic electrode

Also Published As

Publication number Publication date
JP2651143B2 (en) 1997-09-10

Similar Documents

Publication Publication Date Title
JP3748905B2 (en) Quantum effect device
US4186410A (en) Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors
US5677553A (en) Semiconductor device strucutre having a two-dimensional electron gas and contact thereto
EP0155215A2 (en) High electron mobility semiconductor device employing selectively doped heterojunction
KR20000006005A (en) ARTICLE COMPRISING AN OXIDE LAYER ON A GaAs-BASED SEMICONDUCTOR BODY, AND METHDO OF MAKING THE ARTICLE
US4249190A (en) Floating gate vertical FET
JPH0766366A (en) Semiconductor multilayered structure and semiconductor device using same
KR950001949B1 (en) Method of making double injection field effect transistor
US5391897A (en) Status induction semiconductor device
US5227644A (en) Heterojunction field effect transistor with improve carrier density and mobility
JPS63177573A (en) Superconducting transistor
Devlin et al. A molybdenium source, gate and drain metallization system for GaAs MESFET layers grown by molecular beam epitaxy
JPH0344919A (en) Semiconductor device and its manufacture
US4689646A (en) Depletion mode two-dimensional electron gas field effect transistor and the method for manufacturing the same
JPS61147577A (en) Complementary semiconductor device
Silver et al. Superconductor‐semiconductor device research
JPH0337735B2 (en)
EP0144217B1 (en) Superconducting device
JP2624666B2 (en) Superconducting element
JPH028458B2 (en)
JPH0445976B2 (en)
JPS63250879A (en) Superconducting element
JP3083683B2 (en) Semiconductor device
JP2680821B2 (en) Heterostructure field effect transistor
JPS63252484A (en) Hetero-junction field-effect transistor