JPS63177493A - Manufacture of semiconductor laser - Google Patents
Manufacture of semiconductor laserInfo
- Publication number
- JPS63177493A JPS63177493A JP857387A JP857387A JPS63177493A JP S63177493 A JPS63177493 A JP S63177493A JP 857387 A JP857387 A JP 857387A JP 857387 A JP857387 A JP 857387A JP S63177493 A JPS63177493 A JP S63177493A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- stencil
- conductivity type
- mesa
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012808 vapor phase Substances 0.000 claims abstract description 10
- 238000005253 cladding Methods 0.000 claims description 8
- 125000002524 organometallic group Chemical group 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 238000001947 vapour-phase growth Methods 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007791 liquid phase Substances 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 101150054880 NASP gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、大面積に均一な組成および層厚を有するエピ
タキシャル膜を成長可能な有機金属気相エピタキシャル
法による埋込み構造半導体レーザの製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a buried structure semiconductor laser using an organometallic vapor phase epitaxial method that is capable of growing an epitaxial film having a uniform composition and layer thickness over a large area. It is something.
レーザとしては、低しきい値で発振し、かつ安定なモー
ドで動作するものが望ましい。以上の条件をみたすもの
として、活性層を活性層よりも屈折率の小さい材料で囲
むように埋め込んだ埋込み構造半導体レーザがある。今
までに報告されている埋込み構造半導体レーザの代表的
なものを第７図、第８図に示す。It is desirable that the laser oscillates at a low threshold and operates in a stable mode. As a device that satisfies the above conditions, there is a buried structure semiconductor laser in which the active layer is surrounded by a material having a lower refractive index than the active layer. Typical buried structure semiconductor lasers that have been reported so far are shown in FIGS. 7 and 8.
第７図は、「平尾他、応用物理誌、 １９８０．５１巻
、 ４５３９頁」（Ｍ、旧ｒａｏ ｅｔ ａｌ、、Ｊ、
Ａｐｐｌ、 Ｐｈｙｓ、。Figure 7 is from “Hirao et al., Journal of Applied Physics, Vol. 51, 1980, p. 4539” (formerly RAO et al., J.
Appl, Phys.
１９８０、 ｖｏｌ 、５１． ｐ４５３９）で報告さ
れた埋込み構造半導体レーザを示す断面図である。第７
図において、ｌはｎ形ＩｎＰバッファ層、２はＧａ１ｎ
ＡｓＰ活性層、３はｐ形ＩｎＰクラッド層、４はｐ形Ｉ
ｎＰ電流ブロック層、５はｎ形１ｎＰ電流閉込め層であ
る。活性層２が屈折率の小さいＩｎＰ層１．３，４．５
によって囲まれた埋込み構造になっている。この構造に
おいて、埋込み層４および５は液相エピタキシャル法（
以下ｒＬＰＥ法」という）によって成長され、このＬＰ
Ｅ法では、メサ上部につけた誘電体膜に結晶が成長しな
いことを利用している。1980, vol, 51. 4539) is a cross-sectional view showing a buried structure semiconductor laser reported in 7th
In the figure, l is an n-type InP buffer layer, 2 is a Ga1n
AsP active layer, 3 p-type InP cladding layer, 4 p-type I
The nP current blocking layer 5 is an n-type 1nP current confinement layer. Active layer 2 is an InP layer with a small refractive index 1.3, 4.5
It has an embedded structure surrounded by. In this structure, buried layers 4 and 5 are formed by liquid phase epitaxial method (
This LP is grown by
The E method takes advantage of the fact that crystals do not grow on the dielectric film attached to the top of the mesa.
また、第８図は、「水戸他、米国電気電子技術者協会、
光波技術誌、 ＬＴ−１＠、 １９５頁、 １９８３Ｊ
（１，Ｍｉｔｏ ｅｔ ａｌ、１ＩＥＥＥ、Ｊ、 Ｌｉ
ｇｈｔ ｗａｖｅ Ｔｅｃｈ、、ＬＴ−１、ｐ、１９５
．１９８３ ）で報告された埋込み構造半導体レーザを
示す断面図である。この半導体レーザは、第７図に示し
た半導体レーザと同様に、活性層２がＩｎＰ層１． ３
． ４． ５に埋め込まれているが、最後にクラッド層
３を含めてすべてをｐ形ＩｎＰの層６により埋め込む構
造になっている。ここでは、電流ブロック層４．電流閉
込め層５の成長には過飽和度の小さい２相融液を用いた
ＬＰＥ法が用いられており、この場合、メサ上部と高さ
が一致するまでメサ上部には結晶が成長しないことを利
用している。In addition, Figure 8 shows “Mito et al., Institute of Electrical and Electronics Engineers,
Light Wave Technology Magazine, LT-1@, 195 pages, 1983J
(1, Mito et al., 1 IEEE, J. Li
ght wave Tech,, LT-1, p, 195
．． 1983) is a cross-sectional view showing a buried structure semiconductor laser reported in 1983). Similar to the semiconductor laser shown in FIG. 7, this semiconductor laser has an active layer 2 formed of an InP layer 1. 3
．． 4. 5, the structure is such that the entire layer including the cladding layer 3 is finally buried with a p-type InP layer 6. Here, the current blocking layer 4. The current confinement layer 5 is grown using the LPE method using a two-phase melt with a low degree of supersaturation. We are using.
ところが、有機金属気相エピタキシャル法（以下ｒＭＯ
ＶＰＥ法」という）によって、第９図に示すメサ上部に
５ｉＯｚ膜７をつけた逆メサ構造を埋め込む場合、メサ
上部の両端でメサ側面方向にそった角状の異常成長がお
こり、埋込み成長ができない。このことは、例えば「大
面および黒岩、電気化学製会誌、 １２０１〜１２１４
頁、１３２巻、５号。However, metal organic vapor phase epitaxial method (rMO
When an inverted mesa structure with a 5iOz film 7 attached to the top of the mesa as shown in Fig. 9 is buried by the VPE method (referred to as "VPE method"), abnormal angular growth along the sides of the mesa occurs at both ends of the top of the mesa, resulting in the embedding growth. Can not. This can be seen, for example, in ``Omen and Kuroiwa, Denki Kagaku Seikatsu Journal, 1201-1214.
Page, Volume 132, Issue 5.
１９８５Ｊ （Ｍ、０ｉｓｈｉ ａｎｄ Ｋ、Ｋｕｒ
ｏｉｗａ＋Ｊ、Ｅｌｅｃｔｒｏｃｈｅｍ。1985J (M, Oishi and K, Kur
oiwa+J, Electrochem.
Ｓｏｃ、、ｐｐ、 １２０１〜１２１４．ｖｏｌ、１３
２．Ｎｏ、５．１９８５）に記載されている。この異常
成長は５ｉＯｚ膜の他に窒化シリコン膜でも生じ、一般
にその上に結晶成長が生じない膜をメサ上部に付した場
合に生じる。Soc,, pp. 1201-1214. vol, 13
2. No. 5.1985). This abnormal growth occurs not only in the 5iOz film but also in the silicon nitride film, and generally occurs when a film on which crystal growth does not occur is deposited on top of the mesa.
また、第１０図に示すように、垂直にメサを切った場合
も、側壁部分の成長が速く、側壁部分がすべてｐ形Ｉｎ
Ｐ４で覆われてしまうので、ｐｎ接合をメサ側面に形成
することができなかった。Furthermore, as shown in Figure 10, when the mesa is cut vertically, the growth of the sidewalls is fast, and the sidewalls are all p-type In.
Since it was covered with P4, it was not possible to form a pn junction on the side surface of the mesa.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、気相成長特有のガスの輸送現象
によって起こるメサ近傍での異常成長の影響を除去でき
るＭＯＶＰＥ法による埋込み構造半導体レーザの製造方
法を提供することにある。The present invention has been made in view of these points, and its purpose is to provide a buried structure using the MOVPE method that can eliminate the influence of abnormal growth near the mesa caused by the gas transport phenomenon unique to vapor phase growth. An object of the present invention is to provide a method for manufacturing a semiconductor laser.
このような目的を達成するために本発明は、活性層、ク
ラッド層、ステンシル層から成る多層構造のメサ領域を
有する第１導電形半導体基板上に第２導電形半導体層と
第１導電形半導体層から成る積層を有機金属気相エピタ
キシャル法により成長し、メサ領域以外の第１導電形半
導体基板上に成長した積層の高さがステンシル層の下面
に等しくなるようにする工程と、ステンシル層を選択除
去することによってステンシル層上面に堆積された積層
を除去するようにしたものである。In order to achieve such an object, the present invention provides a semiconductor layer of a second conductivity type and a semiconductor of a first conductivity type on a semiconductor substrate of a first conductivity type, which has a mesa region with a multilayer structure consisting of an active layer, a cladding layer, and a stencil layer. growing a stack of layers by a metal organic vapor phase epitaxial method so that the height of the stack grown on the first conductivity type semiconductor substrate other than the mesa region is equal to the lower surface of the stencil layer; The stacked layers deposited on the upper surface of the stencil layer are removed by selective removal.
本発明においては、大面積に均一な組成および層厚を有
するエピタキシャル膜を成長可能なを機金属気相エピタ
キシャル法により、メサ近傍での異常成長を起こすこと
なく、埋込み構造半導体レーザを作製できる。In the present invention, a buried structure semiconductor laser can be manufactured without causing abnormal growth in the vicinity of the mesa by using a metal-mechanical vapor phase epitaxial method that is capable of growing an epitaxial film having a uniform composition and layer thickness over a large area.
第１図〜第６図は、本発明に係わる埋込み構造半導体レ
ーザの製造方法の一実施例を説明するための断面図であ
る。まず、第１図に示すように、（１００）面ｎ形Ｉｎ
Ｐ基板ｌａ上にＳｅドープｎ形１ｎＰ層１ｂ（層厚約２
μｍ）を積層した１ｎＰ基板１を形成し、次に、アンド
ープＧａＩｎＡｓＰの活性層２（層厚約０．１μｍ＞、
ｐ形ＩｎＰクラッド層３ （層厚約１．０μｍ）を形成
し、さらに、選択エツチングによりメサ上面に成長した
層を除去するためのＧａＩｎＡｓＰステンシル層８（層
厚約０．１μｍ）をＭＯＶＰＥ法によって成長する。1 to 6 are cross-sectional views for explaining an embodiment of a method for manufacturing a buried structure semiconductor laser according to the present invention. First, as shown in FIG. 1, (100) plane n-type In
A Se-doped n-type 1nP layer 1b (layer thickness approximately 2
A 1nP substrate 1 with a layer thickness of about 0.1 μm is formed, and then an active layer 2 of undoped GaInAsP (layer thickness of about 0.1 μm>,
A p-type InP cladding layer 3 (layer thickness of about 1.0 μm) is formed, and a GaInAsP stencil layer 8 (layer thickness of about 0.1 μm) is formed by MOVPE to remove the layer grown on the top surface of the mesa by selective etching. grow up.
次に、第２図に示すように成長面にプラズマＣＶＤ法に
よって酸化シリコン膜（図示せず）を付け、ホトリソグ
ラフィの技術によって（０１１）方向に酸化シリコン膜
でストライプ幅約２〜３μｍのストライプマスクを形成
し、１％の１３ｒメチル液によって活性層の下までエツ
チングし、メサ領域を形成する。そして、次に、酸化シ
リコン膜をプラズマエツチング法によって除去する。Next, as shown in FIG. 2, a silicon oxide film (not shown) is applied to the growth surface by plasma CVD, and the silicon oxide film is formed into stripes with a stripe width of about 2 to 3 μm in the (011) direction using photolithography. Form a mask and etch below the active layer with 1% 13r methyl solution to form mesa regions. Then, the silicon oxide film is removed by plasma etching.
次に、第３図に示すように、ＭＯＶＰＢ法により、上記
のメサ領域を有する基板上にｐ形ＩｎＰ電流ブロック層
４ （Ｊｉｉ厚約０．５μｍ）およびｎ形ＩｎＰ電流閉
込め層５（層厚約０．５μｍ）を形成する。成長条件と
しては、例えばソースガスとしてＰＨ３：ＴＭＩ＝１５
０ ： １ （流量比）を用い、ｐ形ＩｎＰを堆積す
る場合はドーピングガスとしてＤＥＺ （ジエチル亜鉛
）を、ｎ形ＩｎＰを堆積する場合にはドーピングガスと
してＨｚｓｅを用い、キャリアガスとして水素を用い、
反応炉内圧力を５０Ｔｏ ｒ ｒ、基板温度を約６８５
℃として堆積を行なう。このとき、メサ上面では、側面
に（１１１）面を出した成長がおこり、他の領域では、
はぼ均一な成長がおこる。そして、メサ領域以外で成長
したｎ形ＩｎＰ電流閉込め層５の高さをメサ領域最上面
のＧａ１ｎＡｓＰステンシル層８の下面にそろうように
する。Next, as shown in FIG. 3, a p-type InP current blocking layer 4 (Jii thickness of about 0.5 μm) and an n-type InP current confinement layer 5 (layer A thickness of approximately 0.5 μm) is formed. As a growth condition, for example, PH3:TMI=15 as a source gas.
DEZ (diethyl zinc) is used as a doping gas when depositing p-type InP, Hzse is used as a doping gas when depositing n-type InP, and hydrogen is used as a carrier gas. ,
The pressure inside the reactor was 50 Torr, and the substrate temperature was about 685
Deposition is carried out at ℃. At this time, growth occurs on the top surface of the mesa with (111) planes on the sides, and in other areas,
Uniform growth occurs. Then, the height of the n-type InP current confinement layer 5 grown outside the mesa region is made to be aligned with the lower surface of the Ga1nAsP stencil layer 8 on the uppermost surface of the mesa region.
次に、Ｈ２ＳＯ４： Ｈ２Ｏ２： Ｈ２０’＝３ ：
１ ： １（３０℃）の溶液を用いてメサ領域最上面の
ＧａＩｎＡｓＰステンシル層８を選択エツチングし、メ
サ領域上面に成長したｐ形１ｎＰ電流ブロック層４．
ｎ形１ｎＰ電流閉込め層５を除去する。これにより、
第４図に示すような結晶平面の平坦化を行なう。Next, H2SO4: H2O2: H20'=3:
The GaInAsP stencil layer 8 on the top surface of the mesa region is selectively etched using a 1:1 (30° C.) solution, and a p-type 1nP current blocking layer 4 is grown on the top surface of the mesa region.
The n-type 1nP current confinement layer 5 is removed. This results in
The crystal plane is flattened as shown in FIG.
次に、ＭＯＶＰＥ法によって、ｐ”形Ｇａ１ｎＡｓＰキ
ャップ層９をウェハ全体に成長し、基板側を研磨してウ
ェハの厚さを約８０μｍとした後、成長側にＡｕンＺ
ｎ ／ Ｎ ｉ電極１０、基板側にＡｕ ／ Ｇ ｅ
／ Ｎ ｉ電極１１を真空蒸着し、Ｈ２中４２０℃で熱
処理し電極を形成する。その後、紙面に平行な面をへき
関し、第５図に示すようなレーザ・チップを作製する。Next, a p'' type Ga1nAsP cap layer 9 is grown on the entire wafer by MOVPE, and the substrate side is polished to a thickness of about 80 μm, and then Au and Z are grown on the growth side.
n/Ni electrode 10, Au/Ge on the substrate side
/ Ni electrode 11 is vacuum deposited and heat treated in H2 at 420°C to form an electrode. Thereafter, the plane parallel to the plane of the paper is separated to produce a laser chip as shown in FIG.
上記に示したように、その上に化合物半導体のエピタキ
シャル成長が可能な膜をメサ領域の最上層に用いること
によりレーザを作製すれば、ＭＯＶＰＥ法によるメサ領
域での異常成長は生じず、メサ領域を埋め込むことがで
き、ＭＯＶＰＥ法だけで容易に埋込み構造半導体レーザ
を作製することができる。なお、最上層（ステンシル層
）８の選択エツチング時に下地のクラッド層３がエツチ
ングされないように最上層を選ぶ必要がある。As shown above, if a laser is manufactured by using a film on which a compound semiconductor can be epitaxially grown as the top layer of the mesa region, abnormal growth will not occur in the mesa region by the MOVPE method, and the mesa region will be It can be buried, and a buried structure semiconductor laser can be easily manufactured using only the MOVPE method. Incidentally, when selectively etching the uppermost layer (stencil layer) 8, it is necessary to select the uppermost layer so that the underlying cladding layer 3 is not etched.
また、上記実施例では、メサ領域最上層のＧａＩｎＡｓ
Ｐステンシル層８の下面とｎ形１ｎＰ電流閉込め層５の
上面がちょうど一致しなければ、選択エツチングによっ
て表面の平坦化はできない。In the above embodiment, the uppermost layer of the mesa region is made of GaInAs.
Unless the bottom surface of the P stencil layer 8 and the top surface of the n-type 1nP current confinement layer 5 exactly match, the surface cannot be planarized by selective etching.
しかし、ｎ形１ｎＰ電流閉込め層５の上面がメサ領域最
上層（ステンシル層）８の下面より低く、選択エツチン
グを行なった後、低いメサが残ったとしても、そのメサ
の高さが１μｍより小さければ、ＭＯＶＰＥ法でもウェ
ハ全体に均一に結晶を成長させることができるので、そ
の場合は、第６図に示すように、選択エツチング後にウ
ェハ全体にｐ形ＩｎＰ埋込み層６を成長し、表面の平坦
化を行なってから、前述したようにｐ°形ＧａＩｎＡｓ
Ｐキ（１７プ層９．Ａｕ／Ｚｎ／Ｎｉ電極１０、Ａｕ／
Ｑｅ／Ｎｉ電極１１を作製し、埋込み構造半導体レーザ
を作製する。However, even if the top surface of n-type 1nP current confinement layer 5 is lower than the bottom surface of mesa region top layer (stencil layer) 8 and a low mesa remains after selective etching, the height of the mesa is less than 1 μm. If the crystal is small, it is possible to grow the crystal uniformly over the entire wafer using the MOVPE method. In that case, as shown in FIG. 6, a p-type InP buried layer 6 is grown over the entire wafer after selective etching, and the surface After planarization, the p° type GaInAs was
P key (17 layer 9. Au/Zn/Ni electrode 10, Au/
A Qe/Ni electrode 11 is produced, and a buried structure semiconductor laser is produced.
また、埋込み層６となる部分にｎ形ＩｎＰを用いた場合
は、活性層２上面の埋込み層６部分にｐ形１ｎＰクラッ
ド層３に到達するまでＺｎの拡散を行ないｐ形化すれば
よい。Furthermore, when n-type InP is used for the portion that will become the buried layer 6, Zn may be diffused into the portion of the buried layer 6 on the upper surface of the active layer 2 until it reaches the p-type 1nP cladding layer 3 to make it p-type.
さらに、半導体基板１としてＳｅドープｎ形ＩｎＰＪｉ
ｌｂがないｎ形１ｎＰ基板１ａを用いてもよい。Furthermore, Se-doped n-type InPJi is used as the semiconductor substrate 1.
An n-type 1nP substrate 1a without lb may also be used.
さらに、上記実施例では、電流ブロック層としてＩｎＰ
のｐｎ逆バイアス層を用いたが、ｐＨｎＰ電流ブロック
層４． ｎ形１ｎＰ電流閉込め層５の代わりに半絶縁
性のＩｎＰ層を用いてもよい。Furthermore, in the above embodiment, InP is used as the current blocking layer.
A pn reverse bias layer was used, but a pHnP current blocking layer 4. A semi-insulating InP layer may be used instead of the n-type 1nP current confinement layer 5.
さらに、Ｇａ１ｎＡｓＰ／ＩｎＰ系について述べたが、
Ｇ ａ Ａ ｓ ／ Ａ！ＧａＡｓ系など他の結晶系を
用いてもよい。Furthermore, although we have described the Ga1nAsP/InP system,
G a As / A! Other crystal systems such as GaAs may also be used.
さらに、ここではｎ形基板を用いて説明したが、ｐ形基
板を用いても同様のことが可能である。Furthermore, although the explanation has been made using an n-type substrate, the same thing can be done using a p-type substrate.
以上説明したように本発明は、多層構造のメサ領域を有
する第１導電形半導体基板上に第２導電形半導体層と第
１導電形半導体層から成る積層を有機金属気相エピタキ
シャル法により成長し、メサ領域以外の第１導電形半導
体基板上に成長した積層の高さがメサ領域のステンシル
層の下面に等しくなるようにし、上記ステンシル層を選
択除去することによってステンシル層上面に堆積された
積層を除去して表面の平坦化を行なうことにより、有機
金属気相エピタキシャル法だけで埋込み構造半導体レー
ザを作製することができるので、液相エピタキシャル法
で不可能な一度に大面積の成長を行なうことができ、多
量の半導体レーザを作製することが可能になる効果があ
る。As explained above, the present invention grows a stack of a second conductivity type semiconductor layer and a first conductivity type semiconductor layer on a first conductivity type semiconductor substrate having a multilayered mesa region by an organometallic vapor phase epitaxial method. , the height of the stack grown on the first conductivity type semiconductor substrate other than the mesa region is made equal to the lower surface of the stencil layer in the mesa region, and the stencil layer is selectively removed, thereby forming a stack deposited on the upper surface of the stencil layer. By removing and flattening the surface, it is possible to fabricate a buried structure semiconductor laser using only the organometallic vapor phase epitaxial method, which allows growth of a large area at once, which is impossible with the liquid phase epitaxial method. This has the effect of making it possible to manufacture a large number of semiconductor lasers.
第１図〜第５図は本発明に係わる埋込み構造半導体レー
ザの製造方法の一実施例を説明するための断面図、第６
図はその第２の実施例を説明するための断面図、第７図
、第８図は液相エピタキシャル法で作製された埋込み構
造半導体レーザを示す断面図、第９図、第１０図は有機
金属気相エピタキシャル法による従来の製造方法を説明
するための断面図である。
１．１ａ−ｎ形ＩｎＰ基板、ｌｂ’−・・ｎ形１ｎＰバ
ッファ層、２・・・ＱａｌｎＡｓＰ活性層、３・・・ｐ
形１ｎＰクラッド層、４・・・ｐ形ＩｎＰ電流ブロック
層、５・・・ｎ形ＴｎＰ電流閉込め層、６・・・ｐ形Ｉ
ｎＰ埋込み層、７・・・酸化シリコン膜、８・・・Ｇａ
ＩｎＡｓ Ｐステンシル層、９ ・ｐ ”形Ｇａ Ｉ
ｎＡｓＰキー？７ブ層９．１０ ・・・Ａ ｕ／ Ｚ
ｎ／Ｎ ｉ電極、１１”Ａｕ／Ｇｅ／Ｎｉ電極。1 to 5 are cross-sectional views for explaining one embodiment of the method for manufacturing a buried structure semiconductor laser according to the present invention, and FIG.
The figure is a cross-sectional view for explaining the second embodiment, FIGS. 7 and 8 are cross-sectional views showing a buried structure semiconductor laser fabricated by liquid phase epitaxial method, and FIGS. 9 and 10 are organic FIG. 2 is a cross-sectional view for explaining a conventional manufacturing method using a metal vapor phase epitaxial method. 1.1a-n-type InP substrate, lb'--n-type 1nP buffer layer, 2...QalnAsP active layer, 3...p
1nP type cladding layer, 4...p-type InP current blocking layer, 5...n-type TnP current confinement layer, 6...p-type I
nP buried layer, 7... silicon oxide film, 8... Ga
InAs P stencil layer, 9.p” type Ga I
nAsP key? 7b layer 9.10...A u/Z
n/N i electrode, 11” Au/Ge/Ni electrode.
Claims (1)
メサ領域を有する第１導電形半導体基板上に第２導電形
半導体層と第１導電形半導体層から成る積層を有機金属
気相エピタキシャル法により成長させて前記メサ領域以
外の前記第１導電形半導体基板上に成長した前記積層の
高さが前記ステンシル層の下面に等しくなるようにする
工程と、前記ステンシル層を選択除去することによって
前記ステンシル層上面に堆積された前記積層を除去して
表面の平坦化を行なう工程とを含むことを特徴とする埋
込み構造半導体レーザの製造方法。A laminated layer consisting of a second conductivity type semiconductor layer and a first conductivity type semiconductor layer is grown by an organometallic vapor phase epitaxial method on a first conductivity type semiconductor substrate having a multilayer structure mesa region consisting of an active layer, a cladding layer, and a stencil layer. the stencil layer by selectively removing the stencil layer, and selectively removing the stencil layer so that the height of the stacked layer grown on the first conductivity type semiconductor substrate in areas other than the mesa region is equal to the lower surface of the stencil layer; 1. A method of manufacturing a buried structure semiconductor laser, comprising the step of removing the laminated layer deposited on the upper surface to planarize the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP857387A JPH0710019B2 (en) | 1987-01-17 | 1987-01-17 | Embedded structure semiconductor laser manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP857387A JPH0710019B2 (en) | 1987-01-17 | 1987-01-17 | Embedded structure semiconductor laser manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63177493A true JPS63177493A (en) | 1988-07-21 |
| JPH0710019B2 JPH0710019B2 (en) | 1995-02-01 |
Family
ID=11696787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP857387A Expired - Fee Related JPH0710019B2 (en) | 1987-01-17 | 1987-01-17 | Embedded structure semiconductor laser manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0710019B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2672740A1 (en) * | 1991-02-08 | 1992-08-14 | Alcatel Nv | PROCESS FOR PRODUCING A PLANAR SEMICONDUCTOR LASER WITH BURIED RIBBON. |
| FR2674684A1 (en) * | 1991-03-28 | 1992-10-02 | Alcatel Nv | PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT SUCH AS A BURIED RIBBON LASER |
| US5478775A (en) * | 1993-12-10 | 1995-12-26 | Nec Corporation | Ridge stripe type laser diode and method for fabricating the same |
-
1987
- 1987-01-17 JP JP857387A patent/JPH0710019B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2672740A1 (en) * | 1991-02-08 | 1992-08-14 | Alcatel Nv | PROCESS FOR PRODUCING A PLANAR SEMICONDUCTOR LASER WITH BURIED RIBBON. |
| FR2674684A1 (en) * | 1991-03-28 | 1992-10-02 | Alcatel Nv | PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT SUCH AS A BURIED RIBBON LASER |
| US5278094A (en) * | 1991-03-28 | 1994-01-11 | Alcatel N.V. | Method of manufacturing a planar buried heterojunction laser |
| US5478775A (en) * | 1993-12-10 | 1995-12-26 | Nec Corporation | Ridge stripe type laser diode and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0710019B2 (en) | 1995-02-01 |
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