JPH01189185A - Manufacture of semiconductor laser having embedded structure - Google Patents

Manufacture of semiconductor laser having embedded structure

Info

Publication number
JPH01189185A
JPH01189185A JP1323188A JP1323188A JPH01189185A JP H01189185 A JPH01189185 A JP H01189185A JP 1323188 A JP1323188 A JP 1323188A JP 1323188 A JP1323188 A JP 1323188A JP H01189185 A JPH01189185 A JP H01189185A
Authority
JP
Japan
Prior art keywords
layer
mesa
substrate
conductivity type
mesa structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1323188A
Other languages
Japanese (ja)
Inventor
Yasuhiro Kondo
康洋 近藤
Yoshio Itaya
板屋 義夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1323188A priority Critical patent/JPH01189185A/en
Publication of JPH01189185A publication Critical patent/JPH01189185A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate abnormal growing in the vicinity of a mesa, to omit restriction on embedded growing due to the height of the mesa and to enhance reliability, by using dry etching when the mesa structure is formed. CONSTITUTION:An Se doped type InP buffer layer 1b, an undoped GaInAsP active layer 2 and a P-type GaInAsP cap layer 7 are grown on a (100)-face N-type InP substrate 1a. Then, a titanium oxide film 8 is attached. The stripe mask of the titanium oxide film is formed in the orientation of (011). A mesa structure is formed by using an argon-chloride based RIE device. Then, a P-type InP current blocking layer 4 and an N-type InP current blocking layer 5 are formed so as to embed a region other than the mesa structure selectively. The titanium 8 is removed. An electrode comprising Au/Zn/Ni is evaporated on the growing side and an electrode comprising Au/Ge/Ni is evaporated on the substrate side in a vacuum state. Since the dry etching is used in this way, a (111) face does not appear on the surface of the mesa side, and the restriction caused by the height of the mesa is not imposed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、大面積に均一な組成および層厚を有するエピ
タキシャル膜を成長可能な有機金属エピタキシャル法に
よる埋込み構造半導体レーザの製造方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a buried structure semiconductor laser using an organometallic epitaxial method capable of growing an epitaxial film having a uniform composition and layer thickness over a large area. be.

〔従来の技術〕[Conventional technology]

レーザとしては、低しきい値で発振しかつ安定なモード
で動作するものが望ましい。このような条件を満たすも
のとして、活性層を活性層よりも屈折率の小さい材料で
囲むように埋め込んだ埋込み構造半導体レーザがある。
It is desirable that the laser oscillates at a low threshold and operates in a stable mode. As a device that satisfies these conditions, there is a buried structure semiconductor laser in which the active layer is surrounded by a material having a lower refractive index than the active layer.

今までに報告されている埋込み構造半導体レーザの代表
的な構造を第8図に示す。
FIG. 8 shows a typical structure of a buried structure semiconductor laser that has been reported so far.

第8図は、エム・ヒラオ(M、Hirao)等によって
報告されたもの(J、Appρ、phys、 、 19
80. vol、 51. P453’9)である。図
中1bはn形1nPバッファ層、2はGaInAsP活
性層、3はp形InPクラッド層、4はp形InP電流
ブロック層、5はn形1nP電流閉じ込め層、7はp形
Ga1nAsPキャップ層である。活性層2が屈折率の
小さいInP層lb、3.4.5によって囲まれた埋込
み構造になっている。この構造において、ブロック層4
及び電流閉じ込め層5は液相エピタキシャル法(LPE
法)によって成長され、LPE法ではメサ上部につけた
誘電体膜に結晶が成長しないことを利用している。
Figure 8 is the one reported by M, Hirao et al. (J, Apprho, phys, 19
80. vol, 51. P453'9). In the figure, 1b is an n-type 1nP buffer layer, 2 is a GaInAsP active layer, 3 is a p-type InP cladding layer, 4 is a p-type InP current blocking layer, 5 is an n-type 1nP current confinement layer, and 7 is a p-type Ga1nAsP cap layer. be. The active layer 2 has a buried structure surrounded by an InP layer lb, 3.4.5 having a low refractive index. In this structure, block layer 4
The current confinement layer 5 is formed by liquid phase epitaxial method (LPE).
The LPE method takes advantage of the fact that crystals do not grow on the dielectric film attached to the top of the mesa.

〔課題を解決するための方法〕[Method to solve the problem]

ところが、有機金属気相エピタキシャル法(MOVPE
法)によって、第9図に示すメサ上面にSing膜8を
つけた高さ、μm以上の逆メサ構造を埋め込む場合、メ
サ側面で角状の異常成長が起き、埋め込み成長ができな
い。これはメサ側面にエピタキシャル成長の起きにくい
(111) 面が出ているためであると考えられる。メ
サ側面での異常成長が起きないように埋込み成長を行う
ためには、メサ高を1μm以下にした逆メサ構造でメサ
上面のマスクによって選択的にメサ側面を埋め込み、更
にマスクを除去した後基板全面に成長を行う2回の工程
が必要となる。このことは、例えば、「近藤他昭和62
年度春季応物予稿30P−ZH−8Jに記載されている
However, metal organic vapor phase epitaxial method (MOVPE)
When embedding an inverted mesa structure having a height of more than .mu.m with the Sing film 8 on the top surface of the mesa shown in FIG. 9 using the method shown in FIG. This is thought to be due to the presence of (111) planes on the sides of the mesa where epitaxial growth is difficult to occur. In order to perform buried growth to prevent abnormal growth on the mesa sides, the mesa sides are selectively buried using a mask on the top of the mesa in an inverted mesa structure with a mesa height of 1 μm or less, and after the mask is removed, the substrate Two steps are required to grow the entire surface. This can be seen, for example, in ``Kondo et al.
It is described in the 2018 Spring Science Proceedings 30P-ZH-8J.

このことから、MOVPE法で埋込み構造レーザを従来
の方法で製作する場合、メサ高を1μm以下に制御する
ことが必要であり、それをウェットエツチングで均一に
行うことはかなりの困難を有する。また、このようにし
て埋込み構造レーザを製作した場合、エピタキシャル成
長の起こりにくい(111)面がメサ側面に表われてお
り、第10図に示すように埋込み層との界面で成長が進
まず結晶性が悪くレーザの信顧性等に問題が出る場合が
ある。
For this reason, when manufacturing a buried structure laser using the conventional MOVPE method, it is necessary to control the mesa height to 1 μm or less, and it is quite difficult to uniformly perform this by wet etching. In addition, when a buried structure laser is manufactured in this way, the (111) plane, which is difficult for epitaxial growth to occur, appears on the side surface of the mesa, and as shown in Figure 10, growth does not proceed at the interface with the buried layer, resulting in a crystalline structure. This may cause problems with the reliability of the laser.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の目的は、気相成長特有のガスの輸送現像によっ
て起こるメサ近傍での異常成長を除去し、メサ高による
埋込み成長の制限をなくし、さらに信頬性の高い埋込み
構造半導体レーザの製造方法を提供することにある。
The purpose of the present invention is to eliminate abnormal growth near the mesa caused by gas transport development peculiar to vapor phase growth, eliminate the limitation on buried growth due to mesa height, and provide a method for manufacturing a buried structure semiconductor laser with high reliability. Our goal is to provide the following.

本発明は、第1導電型バッファ層、活性層、第2導電型
クラッド層又は、さらに第2導電型キャップ層を加えた
多層構造を有する第1導電型半導体基板を選択的にエツ
チングしてメサ構造を形成するとき、従来の技術で使用
されていたウェットエツチングを使わずドライエツチン
グを使用することを主要の特徴とする。ドライエツチン
グを使用することにより、メサ側面に(111)面ば表
われない。垂直に近いメサ構造を容易に均一に形成する
ことが可能である。
The present invention involves selectively etching a first conductivity type semiconductor substrate having a multilayer structure including a first conductivity type buffer layer, an active layer, a second conductivity type cladding layer, or a second conductivity type cap layer. The main feature is that when forming the structure, dry etching is used instead of wet etching used in conventional techniques. By using dry etching, the (111) surface does not appear on the mesa side. It is possible to easily and uniformly form a nearly vertical mesa structure.

そのことにより、メサ高を2μm以上にした場合でも、
メサ近傍での異常成長をおさえてメサを平坦に埋込むこ
とが可能であり、またメサ側面での結晶性が良くなるこ
とより界面における欠陥が少なくなり信頼性も向上する
As a result, even when the mesa height is 2 μm or more,
It is possible to suppress abnormal growth in the vicinity of the mesa and embed the mesa flatly, and since the crystallinity on the side surfaces of the mesa is improved, defects at the interface are reduced and reliability is improved.

〔実施例〕〔Example〕

第1図から第3図に本発明による半導体レーザの製造方
法を順を追って示す。まず第1図に示すように、(10
0)面n形1nP基板la上にSeドドーn形1nPバ
ッファ層1b(d!24m)、アンドープGaInAs
P活性層2(d=Q。
1 to 3 show a method for manufacturing a semiconductor laser according to the present invention in order. First, as shown in Figure 1, (10
0) Se-doped n-type 1nP buffer layer 1b (d! 24m) on surface n-type 1nP substrate la, undoped GaInAs
P active layer 2 (d=Q.

1μm)、p形InPクラッド層3 (d=1. 0μ
m)、p形Ga1nAsPキャップ層? (d=0.5
μm)をMOVPE法によって成長する。
1 μm), p-type InP cladding layer 3 (d=1.0μ
m), p-type Ga1nAsP cap layer? (d=0.5
μm) is grown by the MOVPE method.

次に第2図において成長面にスパッタリング法によって
酸化チタン膜8を付け、ホトグラフィ技術によって(0
11)方向に酸化チタン膜ストライプマスクをストライ
ブ幅約1.5μmで形成する。
Next, in FIG. 2, a titanium oxide film 8 is attached to the growth surface by sputtering method, and (0
11) Form a titanium oxide film stripe mask with a stripe width of approximately 1.5 μm in the direction.

そして、塩素アルゴン系のRIE装置を使用してメサ高
2.0μmのメサ構造を形成する。このときメサ側面は
基板表面に対して80度程度であり、(111)面は表
われない。またほぼ垂直に近いためクラッド層3が1μ
m程度である場合でも活性層幅は、2μm以下であり、
横モードの制御は可能である。さらにドライエツチング
の特徴より、メサ高は面内で均一に形成することができ
る。
Then, a mesa structure with a mesa height of 2.0 μm is formed using a chlorine-argon RIE device. At this time, the mesa side surface is at about 80 degrees with respect to the substrate surface, and the (111) plane is not exposed. Also, since it is almost vertical, the cladding layer 3 is 1μ
Even when the active layer width is about 2 μm, the active layer width is 2 μm or less,
Control of transverse mode is possible. Furthermore, due to the characteristics of dry etching, the mesa height can be formed uniformly within the surface.

次に第3図に示すようにメサ上面のマスクを用い選択的
にメサ構造以外の領域を埋め込むように、MOVPE法
によって、p形InP電流ブロック層4 (d=l μ
m)、n形!nP電流閉じ込め層5 (dユ1μm)を
形成する。この場合のMOVPE法の成長条件としては
、例えばソースガスとしてPH,:TMI−150:1
  (モル比)を用い、P形1nPを堆積する場合はド
ーピングガスとしてDEZを、n形1nPを堆積する場
合にはドーピングガスとしてH,Seを用い、キャリア
ガスとして水素を用い、反応炉内圧力を50T0rr、
基板温度を約685℃として堆積を行う。
Next, as shown in FIG. 3, a p-type InP current blocking layer 4 (d=l μ
m), n-type! An nP current confinement layer 5 (d: 1 μm) is formed. In this case, the MOVPE growth conditions include, for example, PH, :TMI-150:1 as the source gas.
DEZ is used as a doping gas when depositing P-type 1nP, H and Se are used as doping gases when depositing n-type 1nP, and hydrogen is used as a carrier gas. 50T0rr,
Deposition is performed at a substrate temperature of approximately 685°C.

この成長において、メサ高は1μm以上になっているが
、メサ側面には角状の異常成長はおこらない。
In this growth, the mesa height is 1 μm or more, but no angular abnormal growth occurs on the sides of the mesa.

次に、HFによってメサ上面の酸化チタン8を除去する
。そして、基板側を研磨してウェハの厚さを約80μm
とした後、成長側にA u / Z n /Ni電極、
基板側にAu / G e / N i電極を真空蒸着
し、H2中420℃で熱処理し電極を形成する。その後
、紙面に平行な面をへき関し、レーザ・チップを作製す
る。
Next, the titanium oxide 8 on the upper surface of the mesa is removed using HF. Then, polish the substrate side to reduce the thickness of the wafer to approximately 80 μm.
After that, A u /Z n /Ni electrode was placed on the growth side,
Au/Ge/Ni electrodes are vacuum-deposited on the substrate side and heat treated in H2 at 420°C to form electrodes. Thereafter, the plane parallel to the plane of the paper is separated to produce a laser chip.

上記に示したように、メサ構造形成にドライエツチング
を用いることによりレーザデバイスを作製すれば、メサ
側面に(111)面が表われないため、メサ高の制限を
受けることなく、MOVPE法で、メサ近傍に異常成長
を生じさせることなく、メサを平坦に埋め込むことがで
き、MOVPE法だけで容易に埋込み構造半導体レーザ
を作製することができる。さらに、メサ側面を成長前に
ウェットエツチングによりドライエツチングのダメージ
領域を除去することで、界面状態をよくし、信頼性を向
上させることができる。
As shown above, if a laser device is manufactured by using dry etching to form a mesa structure, the (111) plane will not appear on the mesa side surface, so the MOVPE method can be used without being limited by the mesa height. The mesa can be buried flat without causing abnormal growth in the vicinity of the mesa, and a buried structure semiconductor laser can be easily manufactured using only the MOVPE method. Furthermore, by wet etching the side surfaces of the mesa before growth to remove areas damaged by dry etching, the interface condition can be improved and reliability can be improved.

また、上記実施例では、1回のMOVPE法による埋込
み成長で埋込み構造レーザデバイスを作製したが、従来
のようにメサ高の低いメサ構造を用い、選択的にその領
域以外に成長を行い、その後マスクを除去し基板全面に
成長を行う、2回のMOVPE法による埋込み成長で埋
込み構造レーザを作製する工程でもよい。その工程を第
4図から第7図に示す。また、この場合埋込み層6とな
る部分にn形InPを用いた場合は、活性層上面の埋込
み層6部分にp形TnPクラッド層3に到達するまでZ
nの拡散を行いp形化すればよい。
Furthermore, in the above example, a buried structure laser device was fabricated by one-time buried growth using the MOVPE method, but as in the conventional method, a mesa structure with a low mesa height was used, and growth was selectively performed in areas other than that area. A buried structure laser may be manufactured by two-time MOVPE buried growth in which the mask is removed and growth is performed on the entire surface of the substrate. The process is shown in FIGS. 4 to 7. In addition, in this case, if n-type InP is used for the part that becomes the buried layer 6, Z
What is necessary is to perform n diffusion to make the p-type.

さらに、半導体基板1としてSeドドーn形InP層1
bがないn形1nP基板1aを用いてもよい。
Furthermore, a Se-doped n-type InP layer 1 is used as the semiconductor substrate 1.
An n-type 1nP substrate 1a without b may also be used.

さらに、上記実施例では、電流ブロック部として、In
Pのpn逆バイアス層を用いたが、p形InP電流ブロ
ック層4、n形1nP電流閉じ込めN5の代わりに、半
絶縁性のInP層を用いてもよい。
Furthermore, in the above embodiment, as the current block section, In
Although a pn reverse bias layer of P is used, a semi-insulating InP layer may be used instead of the p-type InP current blocking layer 4 and the n-type 1nP current confinement layer N5.

さらに、GaInAsP/InP系について述べたが、
G a A s / A RG a A s系などの他
の結晶系を用いてもよい。
Furthermore, although we have described the GaInAsP/InP system,
Other crystal systems such as the GaAs/ARGaAs system may also be used.

さらに、ここでは、n形基板を用いて説明したが、p形
基板を用いても、同様のことが可能である。
Furthermore, although the explanation has been made using an n-type substrate, the same thing can be done using a p-type substrate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、メサ形成に側面ニ(11
1)面の出ないドライエツチングを使用することにより
、メサ高に関係なく、メサ近傍で異常成長が起こらない
埋込み成長が可能となり、またメサ側面の結晶性を向上
させ、レーザデノ\イスの特性を上げる。さらに、均一
にエツチングが行えるドライエッチを用いることによっ
て、MOVPE法の利点である一度に大面積での成長が
行えることを生かし、多量の半導体レーザデバイスを作
製することが可能になる効果があり、また、均一なメサ
が形成できるという点からも狭線幅が得られる等のレー
ザ特性を上げることができる。
As explained above, the present invention has a method for forming mesa on the side faces (11
1) By using dry etching that does not expose the surface, buried growth is possible without abnormal growth near the mesa, regardless of the mesa height, and the crystallinity of the mesa side surface is improved, improving the characteristics of laser denomination. increase. Furthermore, by using dry etching, which enables uniform etching, it is possible to make use of the advantage of the MOVPE method, which allows growth over a large area at one time, to make it possible to fabricate a large number of semiconductor laser devices. Further, since a uniform mesa can be formed, laser characteristics such as a narrow line width can be obtained and the laser characteristics can be improved.

そして本発明において、特許請求範囲第1項の発明は従
来のMOVPE法での埋込み構造レーザと違い埋込み成
長は一回ですみ、製造工程を簡単にすることができる。
In the present invention, unlike the buried structure laser using the conventional MOVPE method, the invention as claimed in claim 1 requires only one buried growth, which simplifies the manufacturing process.

同じく第2項の発明は、2回の埋込み成長が必要である
が、前記第1項の発明以上にメサ側面での結晶性を上げ
、さらに信頼性等の特性が向上する。同じく第3項の発
明は、前記第1項、第2項の発明と比較し、高抵抗In
P層によって埋込むことから、活性層への電流狭窄を止
めることが可能であり、また第1項、第2項の発明で電
流ブロック部として使用していたp−n接合を無くすこ
とにより、レーザ素子の寄生容量を小さくすることがで
き、高周波特性を上げることが可能である。
Similarly, the invention described in item 2 requires buried growth twice, but it improves crystallinity on the mesa side surface more than the invention described in item 1, and further improves characteristics such as reliability. Similarly, the invention in item 3, compared to the inventions in items 1 and 2, is a high resistance Invention.
Since it is buried with a P layer, it is possible to stop current confinement to the active layer, and by eliminating the pn junction used as a current blocking part in the inventions of Items 1 and 2, It is possible to reduce the parasitic capacitance of the laser element and improve high frequency characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明に係わる埋込み構造半導体レ
ーザデバイスの製造方法の一実施例を説明するための工
程断面図、第4図乃至第7図はその第2の実施例を説明
するための断面図、第8図はLPE法で作製された従来
の埋込み構造半導体レーザを示す断面図、第9図、第1
0図は、MOVPE法による従来゛の製造方法を説明す
るための断面図である。 1、la”−n形1nP基板、■b・・・n形rnPバ
ッファ層、2・・・GaInAsP活性層、3・・・p
形TnPクラッド層、4・・・p形1nP電流ブロック
層、5・・・n形InP電流閉込め層、6・・・p形■
nP埋込み層、7・・・p形Ga1nAsPキャップ層
、8・・・酸化チタン膜 特許出願人   日本電信電話株式会社代理人 弁理士
 玉 蟲 久五部 (外2名) 第 1 図 第 2 図 第  3  口 本発明の第2の実施伊1の断面図 第4図 本発明の12の実施例のWfri!1図第5図 本発明の第2の実74伊KI)断面図 篤6図 本発明の第2の実廃伊]の断面図 第7図 旦 半導体レーザの断1lliQ図 第8図 MOVPE法による従来の製造方法の 断面図 第  9  図 MOVPE汰による従来の製造方法の 断面図 第10図
1 to 3 are process cross-sectional views for explaining one embodiment of the method for manufacturing a buried structure semiconductor laser device according to the present invention, and FIGS. 4 to 7 are for explaining a second embodiment thereof. Figure 8 is a cross-sectional view showing a conventional buried structure semiconductor laser fabricated by the LPE method, Figure 9, Figure 1.
FIG. 0 is a cross-sectional view for explaining a conventional manufacturing method using the MOVPE method. 1, la''-n type 1nP substrate, b...n type rnP buffer layer, 2...GaInAsP active layer, 3...p
TnP type cladding layer, 4...p type 1nP current blocking layer, 5...n type InP current confinement layer, 6...p type ■
nP buried layer, 7...p-type Ga1nAsP cap layer, 8...titanium oxide film Patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Kugobe Tamamushi (2 others) Figure 1 Figure 2 Figure 2 3 Cross-sectional view of the second embodiment of the present invention 1 Figure 4 Wfri of the 12th embodiment of the present invention! Fig. 1 Fig. 5 A cross-sectional view of the second fruit of the present invention 6 Fig. 7 A cross-sectional view of the second fruit of the present invention Fig. 7 A cross-section of a semiconductor laser Fig. 8 A cross-sectional view of the second fruit of the present invention Cross-sectional view of the conventional manufacturing method Fig. 9 Cross-sectional view of the conventional manufacturing method according to MOVPE

Claims (3)

【特許請求の範囲】[Claims] (1)第1導電型半導体基板上又は該半導体基板上に第
1導電型バッファ層が形成されてなる基板上に活性層、
第2導電型クラッド層、第2導電型キャップ層を堆積す
る工程と、該キャップ層、該クラッド層、該活性層、該
バッファ層又は該半導体基板をドライエッチングを用い
て選択的にエッチングしメサ側面が基板表面と90度か
ら70度と垂直に近い角度をなし(111)面とは異な
る面方位を有するメサ構造を形成する工程、有機金属エ
ピタキシャル法によつてメサ構造上面のマスクを用いて
選択的にメサ構造以外の領域に第2導電型半導体層、第
1導電型半導体層を成長させる工程を含むことを特徴と
する埋込み構造半導体レーザの製造方法。
(1) an active layer on a first conductivity type semiconductor substrate or a substrate having a first conductivity type buffer layer formed on the semiconductor substrate;
A step of depositing a second conductivity type cladding layer and a second conductivity type cap layer, and selectively etching the cap layer, the cladding layer, the active layer, the buffer layer, or the semiconductor substrate using dry etching to form a mesa. A step of forming a mesa structure whose side surfaces are at an angle close to perpendicular to the substrate surface at 90 degrees to 70 degrees and has a plane orientation different from the (111) plane, using a mask on the top surface of the mesa structure by an organometallic epitaxial method. A method for manufacturing a buried structure semiconductor laser, comprising the step of selectively growing a second conductivity type semiconductor layer and a first conductivity type semiconductor layer in a region other than the mesa structure.
(2)第1導電型半導体基板上又は該半導体基板上に第
1導電型バッファ層が形成されてなる基板上に、活性層
、第2導電型クラッド層を堆積する工程と、該クラッド
層、該活性層、該バッファ層又は該半導体基板をドライ
エッチングを用いて選択的にエッチングしメサ側面が基
板表面と90度から70度と垂直に近い角度をなし(1
11)面とは異なる面方位を有するメサ構造を形成する
工程と、有機金属エピタキシャル法によつてメサ構造上
面のマスクを用いて選択的にメサ構造以外の領域に第2
導電型半導体層、第1導電型半導体層を成長させる工程
と、メサ構造上面のマスクを除去し該基板全面に第2導
電型半導体層、第2導電型キャップ層を成長させる工程
を含むことを特徴とする埋込み構造半導体レーザの製造
方法。
(2) a step of depositing an active layer and a second conductivity type cladding layer on a first conductivity type semiconductor substrate or a substrate having a first conductivity type buffer layer formed on the semiconductor substrate; and the cladding layer; The active layer, the buffer layer, or the semiconductor substrate is selectively etched using dry etching so that the mesa side surface forms a nearly perpendicular angle of 90 degrees to 70 degrees with the substrate surface (1
11) A step of forming a mesa structure having a plane orientation different from that of the plane, and selectively forming a second layer in a region other than the mesa structure using a mask on the top surface of the mesa structure by an organometallic epitaxial method.
A step of growing a conductive type semiconductor layer, a first conductive type semiconductor layer, and a step of removing a mask on the top surface of the mesa structure and growing a second conductive type semiconductor layer, a second conductive type cap layer on the entire surface of the substrate. A method for manufacturing a featured buried structure semiconductor laser.
(3)第1導電型半導体基板上又は該半導体基板上に第
1導電型バッファ層が形成されてなる基板上に活性層、
第2導電型クラッド層、第2導電型キャップ層を堆積す
る工程と、該キャップ層、該クラッド層、該活性層、該
バッファ層又は該半導体基板をドライエッチングを用い
て選択的にエッチングし、メサ側面が基板表面と90度
から70度と垂直に近い角度をなし(111)面とは異
なる面方位を有するメサ構造を形成する工程、有機金属
エピタキシャル法によつてメサ構造上面のマスクを用い
て選択的にメサ構造以外の領域に半絶縁性半導体層を成
長させる工程を含むことを特徴とする埋込み構造半導体
レーザの製造方法。
(3) an active layer on a first conductivity type semiconductor substrate or a substrate having a first conductivity type buffer layer formed on the semiconductor substrate;
depositing a second conductivity type cladding layer and a second conductivity type cap layer; selectively etching the cap layer, the cladding layer, the active layer, the buffer layer or the semiconductor substrate using dry etching; A process of forming a mesa structure in which the mesa side surface is at a near perpendicular angle of 90 degrees to 70 degrees with the substrate surface and has a plane orientation different from the (111) plane, using a mask on the top surface of the mesa structure by the organometallic epitaxial method. A method for manufacturing a buried structure semiconductor laser, comprising the step of selectively growing a semi-insulating semiconductor layer in a region other than a mesa structure.
JP1323188A 1988-01-23 1988-01-23 Manufacture of semiconductor laser having embedded structure Pending JPH01189185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1323188A JPH01189185A (en) 1988-01-23 1988-01-23 Manufacture of semiconductor laser having embedded structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1323188A JPH01189185A (en) 1988-01-23 1988-01-23 Manufacture of semiconductor laser having embedded structure

Publications (1)

Publication Number Publication Date
JPH01189185A true JPH01189185A (en) 1989-07-28

Family

ID=11827411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1323188A Pending JPH01189185A (en) 1988-01-23 1988-01-23 Manufacture of semiconductor laser having embedded structure

Country Status (1)

Country Link
JP (1) JPH01189185A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260586A (en) * 1989-03-31 1990-10-23 Mitsubishi Kasei Corp Optical semiconductor device and manufacture thereof
US5721751A (en) * 1993-10-28 1998-02-24 Nippon Telegraph & Telephone Corporation Semiconductor laser

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178525A (en) * 1982-04-14 1983-10-19 Fujitsu Ltd Manufacture of semiconductor device
JPS61180493A (en) * 1985-02-05 1986-08-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor laser device
JPS61216495A (en) * 1985-03-22 1986-09-26 Fujitsu Ltd Semiconductor light emitting device and manufacture thereof
JPS61228692A (en) * 1985-04-02 1986-10-11 Nec Corp Semiconductor laser
JPS6284581A (en) * 1985-10-08 1987-04-18 Fujitsu Ltd Semiconductor light-emitting device
JPS62179192A (en) * 1986-01-31 1987-08-06 Nec Corp Semiconductor light emitting device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178525A (en) * 1982-04-14 1983-10-19 Fujitsu Ltd Manufacture of semiconductor device
JPS61180493A (en) * 1985-02-05 1986-08-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor laser device
JPS61216495A (en) * 1985-03-22 1986-09-26 Fujitsu Ltd Semiconductor light emitting device and manufacture thereof
JPS61228692A (en) * 1985-04-02 1986-10-11 Nec Corp Semiconductor laser
JPS6284581A (en) * 1985-10-08 1987-04-18 Fujitsu Ltd Semiconductor light-emitting device
JPS62179192A (en) * 1986-01-31 1987-08-06 Nec Corp Semiconductor light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260586A (en) * 1989-03-31 1990-10-23 Mitsubishi Kasei Corp Optical semiconductor device and manufacture thereof
US5721751A (en) * 1993-10-28 1998-02-24 Nippon Telegraph & Telephone Corporation Semiconductor laser

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