JPS63177239A - Virtual computer system - Google Patents

Abstract

PURPOSE:To reduce the overhead and to improve the processing capacity in a virtual computer system by qualifying an index logical address part with the identification information of a guest virtual computer system despite a high coincidence frequency secured between the address of he guest virtual computer and the index address of a conversion buffer. CONSTITUTION:A guest virtual computer number VNMO is set at a register 11 and the contents of an address conversion buffer TLB selection part 15, a register 11 and a mode register 10 are supplied to a column address qualifying circuit 2. When the register 10 is set at '1', i.e., the guest VM is carried out, the input of the circuit 2 is turned into the output 18 of adders 12 and 13 respec tively and supplied to a column address decoder 6 for selection of an entry of a TLB 4. In such a way, the TLB address is decided by the circuit 2 and therefore it is possible to reduce the overhead and to improve the processing capacity of a virtual computer system without replacing the contents of the TLB despite the coincidence secured between the logical addresses of a host VM and a guest VM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual machine: 44f& system having an address translation buffer (TLB).

[Conventional technology]

It is well known that TLB is used to perform address translation at high speed, and this TLB is also used in virtual machine systems.
is used. Japanese Patent Publication No. 57-25547 indicates that entries for a host computer and multiple guest VMs can be held in the TLB at the same time by providing identification information for the guest virtual machine (GES) VM in the valley entry of the TLB. . Special Publication No. 57-25547 (Guess) VM
As a separate report for m, V M -i D f, TLBKV
A field for setting M-iD' is provided, and a register 'km for setting VM-iD' is provided.

When indexing the TLB, set VM-iDy in the register in advance, compare the VM-iD read from Tl, B and the VM-iDi set in the register, and only if they match, store the main memory. A translation is made to an address.

According to this technology, when control is transferred between a certain guest VM and the host, the contents of the TLB are not cleared (they can be used as is).

[Problem that the invention seeks to solve]

When used in a set φ associative TLBl indexed using a part of the logical address, one guess)
After a VM registers a TLBK address translation pair, if a different guest VM or host computer performs an 'I'LBg index using the registered logical address of the translation pair, the translation pair will be replaced and newly registered.

(Multiple Guess) Index TLB at the same logical address between VM and host computer, that is, multiple Guess)
If the VM and the host computer have the same operating system, etc., and the TLB reference busy Y is frequently used, and the Tl and Bm lookup addresses are often the same, the TLB replacement frequency for the index address will increase, and the instruction processing performance will decrease. This creates unnecessary overhead.

The purpose of the present invention is to replace frequently MY in the above TLBK.
The objective is to improve processing performance in a virtual computer system.

[Means for solving problems]

The present invention provides a logical address portion t for indexing the TLH.
Qualify with the guest VM identification information and index the TLB with this qualified address.

[Operation] By determining the index address of the TLB based on the logical address of the guest VM being executed by the central processing IN fIt and the identification information of the guest VM, a certain 7-st VM enters the TLB at a certain logical address. After registering an address translation pair, when control is transferred to a different VM and a TLB index is performed using the same logical address as the above logical address, the TLB index address is modified, and different TLB entries even at the same logical address , the registered address translation pair is not replaced.

Therefore, even if control is returned to the VM,
TLB index result is i NTLB (exists in TLB)
Therefore, there is no need to perform address conversion again, and no unnecessary overhead is caused in terms of instruction processing performance. especially multiple guesses)
There is a gap in TLB# between VM and host computer.
That is, this is effective when the TLB index addresses are often the same, and the instruction processing performance can be improved.

〔Example〕

The present invention will be explained below using an example.

FIG. 1 shows a portion of the central processing unit of a virtual computer system that is relevant to the present invention.

In this embodiment, the VM1i1 information is
This will be explained using N O (VM number). VNNO
can be created, for example, from the state descriptor (SD) address, which is the second operand of the virtual machine execution start instruction (8iE instruction), and is determined by the instruction execution unit IK in FIG. The VM classification information is not limited to VMNO, and for example, VMiD may be used.

In FIG. 1, reference numeral 7 is a real mode register indicating whether TLB indexing is performed using virtual addresses or real addresses, and @1'' is set when performing the TLB indexing using virtual addresses or real addresses. 8 is the segment cheap origin register (STO register), 9 is the address register. 10 is the guest VM mode register (G register), which is @1" in guest VM mode.
K is set. 11 is a VMNO register. The address register 9 consists of, for example, 51 bits, and the upper 1st to 19th bits are page addresses, which are bits subjected to address conversion, and the 20th to 41st bits are bits common to absolute addresses.

Instruction execution 1fls1 sets @1'' in the G register 10 as an 8iE instruction process, and changes the STO in the SD to ST.
Set to O register 8, and then VMNO-gVMNO
Set register 1.

TI, 84 uses a set anonymity type, that is, one or more entries selected by a column address are called a row, and this row is the target of indexing or restoration. In this example, the number of columns is 512. The TLB configuration has one row, that is, a total of 512 entries, but a-
Make the number plural, etc.

Other configurations can also be easily inferred.

Each entry in TLB5 has a valid field (V), 'l
X) 74-pv)”CG), VM
N O7 Eat A/et (VMNO), real address field (R), segment origin field (ST
O), a virtual address field (VA), and an absolute address field (PA). The number of bits in each field is shown in 'kl). The V field is a 1-bit field that indicates whether this entry is valid or invalid; it is 11" when this entry is valid, and @ when it is invalid.
IO". The G field is a bit field indicating whether this entry is address translation information for the host or guest VM.

When it is a host, it is “0” and when it is a guest VM, it is @1.VM
The NO field has meaning when the G field is @1''', and the VMNO that identifies the VM is set. In this example, it is expressed by VmNOy, -z bit. The B field indicates that this entry is actually Indicates whether it is an address or a virtual address.The G field is a 1-pit field indicating that this entry is address translation information using a common segment.In host save, host address translation.

In guest VM mode, in each guest address translation, when the common segment bit of the referenced segment table entry is 11'', this field becomes @1''. The 19TO field represents the segment table origin at the time of address translation of this entry. The VA field is a 10-bit field 9 that stores bits of the page frame address for TLB access other than the address used for the TLB index, that is, bits 1-10'Y. The FA field stores 19 bits of an absolute address page frame address.

The TLB hit determination unit 5 determines whether the host mode is set and the G field of the TLB entry is added, or the guest VM mote.

The TLB two-ton trifle field 9 is @1'', and the value of the VMNO register 11 is the V of the TLB entry.
Matches MNO field.

■ The C field of the TLB is @1'' or 'I'LB, and the 8TO value of the bird matches the STO register 8.

■ TLB entry V field value @1″ ■ TLB
VA field ° of entry and address bits 1-10 of address register 9 match.

■ The 几 field of the TLB entry and the 几 register 7 match.

If all of the above ■ to ■ are true, TLB hit 16 is @1", and if not, TLB miss 17 is @1"
becomes.

3 is a TLB write control unit. T by address translation
Controls LB addition registration and TLB dual entry activation.

In FIG. 1, 2 indicates a TLB column address modification circuit, and 12-15 indicate adders. address register 9
Among the contents of TLB, 11-19 used for entry selection of TLB a are inputted to the TLB column address modification circuit 2 by the TLB selection section 15.

When the VMNO register 1 is set to VMNO by the instruction execution unit 1 and a TLB index request is issued.

In addition to the TLB selection section 15, the contents of the VMNO register 11 and the G register 10 are also input to the TLB column address modification circuit 2.

The contents of the G register 10 and the V'MNO register 11 input to the TLB column address modification circuit 2 are input to the adder 12, and the addition result is input to the adder 13. When the TLB selector 15 in the contents of the logical address register 9 is set to ``1'' in the output of the G register 10, that is, when the contents of the G register 10 are ``1,'' VM
Addition is performed only if is being executed. Adder 1
The addition result 18 of 3 is input to the column address decoder 6 of the TLB 4, and one entry of the TLB 4 is selected based on this decoding result. Furthermore, if a carry occurs in the most significant bit as a result of the addition by the ff1jE unit 13, it is ignored and the addition result 18 is obtained.

Figure 2 shows TJ, T in B column address modification circuit 2.
It shows the relationship between the output of LB selection s15 and the addition result 18 input to the column address decoder 6 of TLB4. In FIG. 2,
represents the addition result 18'i.

Referring to Figure 2, in host mode (G −”o')
In this case, bits 11-19 of the address become the TLBO column address as they are. In guest mode ((j-@1”), bit 0 of VMNO
．． Depending on the value of 1, X K 256.320.384 or 448 will be added. As is clear from this, between different guest VMs and hosts, the numbers are modified by VMNO, so even if 2 has the same content, the value of 1 will be different, and the TLB index address will change.

That is, for one guest VM, Tl, B
4 index is the contents of logical address register 9 and VMNO
(It is determined by the contents of register 11, so it is different)
A TLB that is selected between VMs and between host computers even if the contents of the TLB selection sections 1 and 15 of the logical address register 9 are the same.

The entries will be different.

According to this embodiment, the TL and B column addresses are TLB
Since it is determined by the logical address to be referenced and VMNO, which is the guest VM identification information, the host and guest VM
Even if the TLB index part in the logical address is the same, the TLB column address changes between the two, and the registered address translation pair is not replaced (this results in a reduction in processing performance overhead due to replacement).

〔Effect of the invention〕

In the present invention, since the TLB index address is determined by the logical address to be referenced and the identification information of the guest VM, the contents of the TLB can be replaced even if the contents of the TLB index logical address part are the same between the host and guest VM. There isn't. %, when the host and multiple guest VMs have the same operating system, there is a bias in the logical addresses that refer to the TLBt, and there is a high frequency in which some of the logical addresses that refer to the TLB are the same (in that case, the TLB content will be replaced less frequently.

As described above, processing performance overhead due to replacement of TLB contents is reduced, and processing performance can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the TLB selection section 15 in the TLB column address modification circuit and the addition result 18 input to the column address decoder 6 of the TLB 4. It is. 1...-instruction execution unit, 2 ・T I, B column address modification circuit, 5 +++ 'l[' L B I included?
ff1J (IIIW, 4・TLB. 5・-TLB hit determination circuit, 6・TL 8 column address decoder, 7... Real mode register, 8・STO register, 9-... Logical address Register, 10・”kes) V M %-)'
L/')
2 and 13...Adder.

Claims (1)

[Claims] 1. In a virtual computer system having an address translation buffer that holds address translation pairs and is indexed by a part of a logical address, the address translation is performed by modifying a part of the logical address with identification information of a guest virtual machine. A virtual computer system characterized by indexing buffers.