JPS61173359A - Address conversion buffer control system in multiple virtual memory system - Google Patents

Abstract

PURPOSE:To regard multiway bits as obstruction to make efficient use of ILB by removing the possibility of multiway bits at the time of reading when the common segment bit CS of new data registered in an address conversion buffer TLB is '1'. CONSTITUTION:Logical addresses of '1' of a CS bit register 6 of the new conversion data is registered in buffers 1, 2 of a multiple virtual memory system. During registering, the logical address of a logical address register 3, a space identification number register 5, the logical register LA of the buffers 1 and 2, and space identification number STO are compard in comparators 7-10. If there are ways 0, 1 that concide upon such comparison, they are registered in the respective ways 0, 1 by using CS of new conversion data. In case of concurrent coincidence, one of them is registered in one and the other is invalidated. In case there is no coincidence in any ways, the way to be registered is determined by Least Recently Used method by a register way determining circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a TLB ! in a multiple virtual memory system having a common segment bit (CS) and an address translation buffer (TLB) consisting of multiple ways. Segmentation is a conventionally well-known control method related to the t control method, particularly when registering a logical address to the address translation buffer (TLB).

In a multi-virtual storage system based on the virtual storage system and the paging method, a virtual storage space is generated for each program (job) to be executed, and each generated virtual storage space has a space identification number (STO) unique to each virtual storage space. There are segment tables specified by , and page tables referenced by the segment tables, and these are used to protect mutual areas and manage shared areas.

One virtual storage space is composed of, for example, 256 consecutive segments, each segment is composed of 16 consecutive pages, and each page is composed of a continuous 4 KB area.

Each virtual storage space is identified by a space identification number (STO),
The logical address in the identified virtual storage space is represented by a segment number, page number, and displacement within the page.

When converting the logical address of a program running in the virtual memory space into a real address, dynamic address conversion (hereinafter referred to as
A mechanism called DAT is used.

When the logical address is translated into a real address using the DAT mechanism, the translated address pair is registered in an address translation buffer (hereinafter referred to as TLB).

The TLB is a high-speed buffer memory that holds a certain amount of recently used logical address translation data and enables direct translation. In other words, the DAT method using the segment table and page table requires two memory accesses, which takes a long time for conversion, so by using the direct conversion using the TLB, high-speed logical address-to-real address conversion is possible. It will be possible.

The above conventional registration update for the TLB is performed using the well-known RU
Based on the (Least Recently Used) method, conversion data that has not been used recently is removed, and new conversion data is then written.

By the way, in the above-mentioned multiple virtual storage spaces, for example, the system area and common area in which the control program for the input/output device and the common table are resident have the same real address in each virtual storage space. Therefore, segments corresponding to these system areas and common areas can share the same page table, and the segments can also share conversion data in the TLB. A segment common to these multiple virtual storage spaces is called a common segment.

In order to identify the common segment, enter the common segment bi in the winter space segment table.

(hereinafter referred to as a CS bit) is provided, and for each common segment, the CS bit is set to "1°."

Regarding the translation of logical addresses in each common segment area to real addresses, the space identification number (STO) is ignored, and the logical addresses in each virtual storage space are treated as if they were logical addresses in a single space. being handled,
Same segment table.

and is converted to a real address using a page table.

In this case, the TLB is also provided with a CS bit, which indicates whether or not the data is shared as conversion data for the common segment area.

The above virtual storage space is used for initial program loading (
Immediately after the IPL, the single (S
TO110), and the CS bits of all segment entries are cleared to "0", but as the number of programs to be processed in parallel increases, they are multiplexed as shown in Figure 2 (b). Teyuki (STOS.

~In), along with that, in each segment table, the CS bit of the common segment is °1
It can be switched to ゛.

At this point, when an attempt is made to convert the logical address included in the common segment area of the expanded virtual storage space, a so-called multi-way hit occurs in which the converted data of multiple ways of the TLB is hit.
There is a problem that a hit) may occur.

The process by which the above multi-way hit occurs is shown in Figure 3.
However, in this figure, it is assumed that the logical address A in each common segment area of each virtual storage space (space identification number (STO) 110 to 1tn) is accessed.

First, ■ is a state in which logical address A in the common segment area in a single space "IO" is accessed immediately after initial program loading (IPL) in FIG. 2(a), and at this time, TLBO way 80 , conversion data of CS bit = 'o', 5ro = *o, logical address = A is registered in way 11, for example, cs
It is assumed that bit L°o゛, sro=go, and logical address=B are registered.

2 shows a case where access to logical address A within the common segment area of the space of STO #1 is requested in the state of the multiple virtual storage space of FIG. 2(b). At this time, the CS bit is as described above.

It is set to 1'.

Therefore, TLB way go has CS bit=°0”
, there is a mismatch at 5TO=lIO, and way 11 is 5T
OdO, there is a mismatch at logical address = B, so the so-called ↑L
It becomes B-MISS.

■ is the result of TLB-MISS in ■, 5TO=I11
The conversion data in the common segment area obtained using the segment table and page table of the space is registered in the TLB. In this case, in the conventional system, CS bit=“l', 5TO=11.Logical address=A is registered in way 11 of TLB by LRU logic as described above.

In (2), an access request for logical address A in the common segment area is issued from the space of 5TO=lIO, the conversion data of way #0 matches, and way #1 is changed to C.
Since the S bit is “1”, the space identification number (ST
O)=ltl is ignored, and here too, an address match is obtained, resulting in the above multi-way hit.

In such a dynamic address translation mechanism that uses common segments, there is a problem in which so-called multi-way hits occur due to redundant translation data being registered in the TLB between common segments. was required.

Furthermore, in the state of (2) above, that is, when the CS bit in the segment table is set to 1, the multi-way hit can be suppressed when reading the TLB in (2) by invalidating the TLB. However, there is a problem in that the processing becomes complicated, and a method is required that can suppress the multi-way hit without requiring invalidation of the TLB.

[Conventional technology]

FIG. 4 is a block diagram showing an improved prior art TLB, the details of which are disclosed in Japanese Patent Application No. 59-223240. Therefore, the details will be omitted, but the contents can be summarized as follows using this figure (however, the way numbers have been changed for convenience of explanation).

First, in this figure, 1 is the TLB way l092 is the TL
B-ways #1 and 3 are logical address registers (LAR).

4 is real page address register (RAR), 5 is space identification number (STO) register (STO), 6 is C
S bit register (CS), 7 to 10 are comparators (C)
, R is a reading section, and R is a writing section.

In the improved conventional method, when registering new conversion data obtained by converting logical addresses in the common segment area in the TLB, the space identification number (STO) register (STO) 5 is ignored and the same - Logical address is T
It is checked whether the new conversion data exists in the LB way 101.1112, and if it exists, the new conversion data is registered in that way, and the multi-way hit is generated based on the duplicate conversion data. The configuration is such that in a multiple virtual storage system equipped with a TLB having a CS bit, the TLB is provided with a CS bit register (
CS) The contents of logical address register 3 where 6 is 1' are transferred to TLB way 1101. To register for ltl 2,
The comparator (C) 7.9 checks whether the same logical address as the logical address is registered in the TLB way 101.112, and if so, the way is registered. The above CS bit register (CS) 6
registers the logical address of 1゛, and if it is not registered, controls the CS bit register (CS) 6 to register the logical address of 1゛ in the way specified based on the LRU logic. It is characterized by

The registration operation for the above TLB way 101.1112 is as follows, and if CS bit = "1", TLB way 1
01゜Search for #12 and register the same logical address (
In other words, if it has been hit (HIT), it will be registered in that way,
If the logical address is not registered (i.e., NON
IIIT), or if CS bit = 'o"t",
It can be seen that the registration way is determined according to LRU logic.

As is clear from FIG. 4, the improved TLB is characterized in that the read section indicated by R and the write section indicated by K are provided separately.

[Problem that the invention seeks to solve]

Therefore, as disclosed in Japanese Patent Application No. 59-223240,
In the improved conventional method, the read unit (R) and write unit for TLB ways #01 and #12 are configured independently, which complicates control and, especially in registration processing, Since the number of logical stages is large, there is a problem in that processing takes time.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional technology, it is an object of the present invention to provide a registration control system that has a simple configuration and does not cause the multi-way hit.

[Means for solving problems]

This purpose has a common segment bit (CS),
In a multiple virtual storage system equipped with an address translation buffer (TLB) consisting of multiple ways, when registering a logical address with the common segment bit (CS) "1" in the address translation buffer (TLB), the registration The logical address and space identification number (ST
O) is compared with the logical address in the address translation buffer (TLB) and the space identification number (STO), and if there is a matching way, the common segment bit (C
S), and if multiple ways match at the same time, register in any one way and invalidate the contents of the other ways, and if none of the ways match. Ha, L[? This is accomplished by the TLB $11'a method in the multiple virtual storage system of the present invention, which controls the registration way determination using U logic or other methods.

[Effect]

That is, according to the present invention, the CS bit of new conversion data to be registered in a TLB having a plurality of ways is
In the case of 1, the space identification number (STO) of the TLB is removed from the comparison, and if there is a matching way, it is registered in that way to eliminate the possibility of a multi-way hit when reading. Therefore, all multi-way hits can be regarded as hardware failures, and in addition to achieving high-speed reading of the TLB, in a TLB that does not have any measures against multi-way hits regarding the CS bit, When setting the CS bit in the segment table entry to 1, it is necessary to invalidate TLB, but this invention eliminates the need for TLB.
This has the effect of making effective use of LB.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 4 indicate the same objects, and TL
When reading B, select the CS bit on the TLB side and read the TL
When registering new conversion data to B, a multiplexer (MP
X) 30.31 and the registered way determination circuit 40 are functional blocks necessary to implement the present invention.

As is clear from this figure, the present invention is characterized in that it is configured so that both read processing and registration processing can be realized by the same circuit.

Even if the present invention is implemented, the TLB reference operation is the same as in the conventional system.

First, when the logical address of the program is set in the logical address register (LAR) 3, a part of the page number in the logical address register (LAR) 3 is given to TLB way #01.1112, and the page number is Conversion data of an entry corresponding to a part is read.

In the TLB way 101, the registered logical address (LA) in the conversion data read out by the comparator (C) 7,
Compare with the corresponding part in the logical address register 3,
If they match, °1' is output to the AND circuit 14.

Comparator (C) 8 compares the space identification number (STO) in the conversion data read from TLB way #01 with the current space identification number (STO) set in space identification number register (STOR) 5. are compared, and if they match, it outputs °1' to the AND circuit 14 via the OR circuit 12.

The other input of the OR circuit 12 is a multiplexer (Mr'
X) 30 outputs are given, and when reading, TLB
It functions so that the CS bit (CS) in the conversion data read from way #01 is given.

Therefore, when the CS bit = "1", the OR circuit 12
outputs °1'' to the AND circuit 14 regardless of the output value of the comparator (C) 8. That is, the CS bit=.

1'', the comparison result of the space identification number (STO) is ignored.

When the CS pin='O', the output value of the comparator (C) 8 is given to the AND circuit 14.

In this way, when CS bit = "O', when each output of comparator (C) 7.8 is "1", when CS bit = 8T, what is the output value of comparator (C) 8? Restricted
However, if the output of the comparator (C) 7 is 1, the output of the AND circuit 14 is 1, indicating that TLB way #01 has been hit.

Similarly, when the CS bit in the conversion data read from TLB way #12 is “0”, the comparator (C)
When each output of 0 is 1, or if the CS bit = 1', when the output of comparator (C) 9 is 1, it indicates that the TLB way 112 has hit (HIT). .

Next, the operation when registering new conversion data in the TLB will be described.

In the present invention, if the same logical address as the conversion data to be registered already exists in the TLB, it is preferentially registered in that way, and in other cases, the L
It is registered in a way specified based on RU logic and functions in the same manner as disclosed in Japanese Patent Application No. 59-223240. That is, the new conversion data to be registered in the TLB way to t, st 2 is stored in the logical address register (LAR) 3. Real page address register (RAR)
4. Space identification number (STO) register (STOR)
5. CS bit register (CS) 6 is set respectively.

TLB ways [01 and 112 are each given a part of the page number of the logical address register (LAR) 3, as in the case of the reference operation, and output the conversion data of the corresponding entry. Then, the comparator (C) 7.9 compares the registered logical address in the conversion data read from the TLB ways 1101 and 112 with the corresponding part in the logical address register (LAR) 3, and if they match. At each time, "1" is output to one input of the AND circuit 14.

During the registration operation, multiplexer (MPX) 30.3
1 functions to select and output CS bit register (CS) 6, so when the CS bit of new conversion data is ``1'', one input of AND circuit 14 and 15 is always activated. Therefore, regardless of the output value of comparator (C) 8.10, the coincidence output at comparator (C) 7.9 °
If ``1'' is output, it will be displayed that there has been a hit (HIT), and if the CS bit of the new conversion data is 0'',
Comparator (C) 7.9 and Comparator (C) 8.10
It functions to display the hit (HIT) only when there is a match. Therefore, by inputting the HIT-(HIT) output to the registered way determination circuit 40, the registered way can be known.

By configuring the logic in the registered way determining circuit 40 as shown in the table below, for example, the multi-way hit can be suppressed.

As described above, in the present invention, when matching outputs are simultaneously obtained in a plurality of ways of the TLB, the registered way determining circuit 40 functions to determine one registered way and invalidate the other ways. The feature is that the TLB can be used effectively.

In the above description, the valid bit (V) originally provided in each TLB is not particularly mentioned, but the validity of data read from the TLB can be identified by
It goes without saying that this is done using the valid bit (V).

〔Effect of the invention〕

As explained above in detail, the TLB control method in the multiple virtual storage system of the present invention is based on the CS of new conversion data to be registered in a TLB having multiple ways.
If the bit is °1, the space identification number of the TLB (
If there is a matching way, it is registered in that way to eliminate the possibility of a multi-way hit when reading. All of these can be regarded as hardware failures, and in addition to high-speed TLB reading, C
In a TLB that does not have any measures against multi-way hits regarding the S bit, it is necessary to invalidate the TLB when setting the CS bit in the segment table entry to 1, but with the present invention, this is no longer necessary. This has the effect of making effective use of the TLB.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. Figure 2 shows multiple virtual memory spaces and common segment bits (
CS bit) is an explanatory diagram. FIG. 3 is an explanatory diagram of the process of multiway hit generation in TLB. FIG. 4 is a block diagram showing the TLB configuration in the prior art. It is. In the drawing, 1.2 is the address translation buffer (TLB way lto,
l1l). 3 is a logical address register (LAR). 4 is a real page address register (RAR). 5 is the space identification number (STO) register (STQ, 5T
OR). 6 is the CS bit register (CS). 7 to 10 are comparators (C). R is a reading section, - is a writing section. 30.31 is a multiplexer (MPX). 40 is a registered way determination circuit. are shown respectively. No. J country

Claims (1)

[Claims] In a multiplex virtual memory system equipped with an address translation buffer (TLB) having a common segment bit (CS) and consisting of multiple ways, the address translation buffer (
To register a logical address whose common segment bit (CS) of new conversion data is "1" in TLB), the logical address to be registered and the space identification number (S
TO) is compared with the logical address in the address translation buffer (TLB) and the space identification number (STO), and if there is a matching way, the common segment bit (CS) of the new translation data is used to identify the way. If multiple ways match at the same time, register in one of the ways and invalidate the contents of the other ways. If none of the ways match, use LRU logic or An address translation buffer control method in a multiple virtual memory system, characterized in that a registration way is determined using another method.