JPS63177220A - Auxiliary memory control device - Google Patents

Auxiliary memory control device

Info

Publication number
JPS63177220A
JPS63177220A JP62009624A JP962487A JPS63177220A JP S63177220 A JPS63177220 A JP S63177220A JP 62009624 A JP62009624 A JP 62009624A JP 962487 A JP962487 A JP 962487A JP S63177220 A JPS63177220 A JP S63177220A
Authority
JP
Japan
Prior art keywords
address
register
error
instruction
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62009624A
Other languages
Japanese (ja)
Other versions
JPH0577091B2 (en
Inventor
Katsutoshi Takachiho
Fumiaki Tahira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62009624A priority Critical patent/JPH0577091B2/ja
Publication of JPS63177220A publication Critical patent/JPS63177220A/en
Publication of JPH0577091B2 publication Critical patent/JPH0577091B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the increase of the re-access time by obtaining the data address and the number of remaining records of an error state via an address control table and recording them in a state register for restart of an access in case an error is detected with the access data.
CONSTITUTION: If an error is detected with the access data, this error is displayed on a state register 109 and an interruption signal is sent to a CPU CC2. The CC2 detects the interruption signal and recognizes the error owing to a face that the register 109 and a state register 105 have no error display nor end display respectively. Then the CC2 sends a read record address instruction. A memory 3 reads said address instruction to interpret it and obtains the present address and the number of remaining sectors by means of an address control program 113 and an address control table 111 to transfer them to the register 109 and then to a peripheral bus 7. Then the memory 3 sends the information to the CC2. The CC2 records these received address and the number of sectors into an address register 101 of an auxiliary memory control device 1' and sets a read data instruction at an instruction register 100.
COPYRIGHT: (C)1988,JPO&Japio
JP62009624A 1987-01-19 1987-01-19 Expired - Lifetime JPH0577091B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62009624A JPH0577091B2 (en) 1987-01-19 1987-01-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62009624A JPH0577091B2 (en) 1987-01-19 1987-01-19

Publications (2)

Publication Number Publication Date
JPS63177220A true JPS63177220A (en) 1988-07-21
JPH0577091B2 JPH0577091B2 (en) 1993-10-26

Family

ID=11725416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62009624A Expired - Lifetime JPH0577091B2 (en) 1987-01-19 1987-01-19

Country Status (1)

Country Link
JP (1) JPH0577091B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718555A (en) * 1980-07-04 1982-01-30 Aisin Seiki Co Ltd Pedal parking brake

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718555A (en) * 1980-07-04 1982-01-30 Aisin Seiki Co Ltd Pedal parking brake

Also Published As

Publication number Publication date
JPH0577091B2 (en) 1993-10-26

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