JPS63177220A - Auxiliary memory control device - Google Patents

Abstract

PURPOSE:To eliminate the increase of the re-access time by obtaining the data address and the number of remaining records of an error state via an address control table and recording them in a state register for restart of an access in case an error is detected with the access data. CONSTITUTION:If an error is detected with the access data, this error is displayed on a state register 109 and an interruption signal is sent to a CPU CC2. The CC2 detects the interruption signal and recognizes the error owing to a face that the register 109 and a state register 105 have no error display nor end display respectively. Then the CC2 sends a read record address instruction. A memory 3 reads said address instruction to interpret it and obtains the present address and the number of remaining sectors by means of an address control program 113 and an address control table 111 to transfer them to the register 109 and then to a peripheral bus 7. Then the memory 3 sends the information to the CC2. The CC2 records these received address and the number of sectors into an address register 101 of an auxiliary memory control device 1' and sets a read data instruction at an instruction register 100.

Description

[Detailed Description of the Invention] [Summary] The auxiliary memory control device sequentially records the data addresses of the auxiliary memory that are being accessed, and when a data error occurs, the restart data address etc. are sent to the central control device for re-access. The purpose is to inform the public.

[Industrial application field]

The present invention relates to an improvement in an auxiliary memory control device in a data processing device.

When an auxiliary memory control device that controls auxiliary memory such as a magnetic disk device or a floppy disk device encounters a data error while accessing the auxiliary memory, the central control device, for example, stores the data address at the time of the error occurrence (hereinafter referred to as address). ), and commands re-access from that address.

Therefore, it is desired to provide an auxiliary memory control device that can easily know the address for re-accessing.

[Conventional technology]

FIG. 5 is a block diagram of a conventional auxiliary memory control device.

In the figure, when data is transferred between an auxiliary memory floppy disk device (hereinafter referred to as FD) 8 or magnetic disk device 9 and a memory device (hereinafter referred to as MM) 3,
The central control unit (hereinafter referred to as CC) 2 is connected to the peripheral bus control unit (hereinafter referred to as PBC) 6. Auxiliary memory control device (hereinafter referred to as F
After issuing a command to the MM3 and the direct memory access control device (hereinafter referred to as DMAC) 4, the control is performed between the auxiliary memory and the auxiliary memory 13 via the common bus 5 and the peripheral bus 7 under the control of the DMAC 4. Data transfer is performed directly without going through CC2. The operation of reading data from FD8 will be explained. CC2 starts PBC6, connects to FMCI, and writes the address register of FMol (
(hereinafter referred to as CAR) 101 is the read address of FD8 (
Side number, track number.

Number of records (number of sectors) to be read into the record size register (hereinafter referred to as RSR) 102
is recorded in the command register (hereinafter referred to as CMR) 10.
Set the read data command to 0.

Also, at this time, CC2 is the word counter 41 of DMAC4.
Also records the number of sectors to be read, and DMs subsequent read operations.
Outsource to AC4.

FMCI microprocessor (hereinafter referred to as MPU) 1
03 reads the read data command of CMRloo by scanning and interprets it, displays an in-use indication in the status register 105, and uses a read program (not shown) stored in the memory 104 to control the floppy disk controller (HO6, hereinafter referred to as FDC). Start up, control FD8, and use CA
Reading starts from the address recorded in RIOI, and the sequentially read data is sent to the buffer memory (
(hereinafter referred to as BM) 108.

The data accumulated in the 8M 108 is written to the memory 3 under the control of the DMAC 4, but the transfer ends when the content of the word counter 41, which is decremented every time data in sectors are written, becomes zero.

The FMCI checks the cyclic code attached to the data by the FDC 106, and the result of the determination of pass/fail is displayed in the status register 109.

When data reading from the FD8 is completed, a completion indication is made in the status register 105, and an interrupt signal is issued to the CG2. The CC2 detects the no-error indication in the status register 109 and the completion indication in the status register 105 to identify the completion of data transfer.

[Problem that the invention seeks to solve]

In the data reading of the conventional example described above, if an error occurs, an error is displayed in the status register 109, and the C
An interrupt signal is issued to C2.

The CC2 connects to the FMCI by the interrupt signal, identifies that the data read was defective because there is no error indication in the status register 109 and no completion indication in the status register 105, and instructs re-reading.

CC2 is the content of word counter 41 of DMAC4 and C
Read the address of ARlol and calculate the restart address and the number of remaining sectors.
After recording to MCI, read data command to CMRl
Set to oo to read data again. Therefore, a dedicated restart processing program is required, and this processing increases the reading time.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

lo indicates FMC. 103 is an MPU that controls the entire PMCI, 110 is a memory that stores programs used by the MPU 103, and 150 is an auxiliary memory that controls the
Auxiliary memory control unit that checks accessed data;
Reference numeral 109 denotes a status register for recording the quality determination result of the accessed data.

As related to the present invention, 111 is an address management table for recording the address of the auxiliary memory currently being accessed and the number of records accessed so far, and 112 is for recording the above address and the number of records in the address management table 111. The current address and the number of remaining records are stored in status register 10.
This is address management means for recording in 9.

[Effect]

FMCI's MPU 103 according to instructions from the central controller.
starts the auxiliary memory control unit 150 to access the auxiliary memory, but at this time, the address management means 112 stores the address of the auxiliary memory currently being accessed and the number of records accessed so far in the address management table 11 of the memory 110.
1 in sequence.

The auxiliary memory control unit 150 checks the cyclic code added to the data at the time of access, but if an error is detected, the address management unit 112 uses the address management table 111 to check the address at the time of the error occurrence. The remaining number of records is obtained and recorded in the status register 109.

The central control unit, to which the interrupt signal is sent due to the error detection, reads the contents of the status register 109 and issues a re-access command.

In this way, the central control unit can directly know the restart address without the need for arithmetic means to find the restart address, so a dedicated restart processing program is not required.
Continuation time in the event of an error is shortened.

〔Example〕

The present invention will be specifically explained below with reference to illustrated examples.

FIG. 2 is a block diagram of an auxiliary memory control device according to an embodiment of the present invention, FIG. 3 is an explanatory diagram of a reading procedure of the present invention, and FIG. 4 is a diagram of an explanatory diagram of a restart address sending procedure of the present invention. The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the address management program 113
Corresponding to the address management means 112 in the figure, FflC106
, the magnetic disk control section 107 corresponds to the auxiliary memory control section 150 in FIG.

As an example, a case will be described in which data is read from the FD8. C
C2 is PBC6, MM3. Start DMAC4 and start FMC
The data read from FD8 by I' is transferred to DMAC4.
under the control of CG2 via peripheral bus 7 and common bus 5.
so that it is written directly to MM3 without going through it.

FMCI' is the same as the conventional example < FD8 read start address (side number, track number, sector number)
ARIOI and the number of sectors to be read are recorded in R5R102 (step S1 in FIG. 3), and a read data command is set in CMRloo (step S2).

The MPU 103 reads and interprets the read data command (step S3), displays an in-use indication in the status register 105 (step S4), and then starts the FDC 106 and executes the FDC command.
D8 is operated (step S5), a read address is set (step S6), and the address management program 113
The read address is recorded in the address field 111^ of the address management table 110, and the number of read sectors is recorded in the record number field 111B (step 57) (initially zero).

Data is read from the FD8 using the above read address (step S8), checked by a cyclic code in the FDC106 (step S9), and if there is no error, it is written to the 8M108, and the data is transferred to the AC4
is transferred to MM3 under the control of (step 510).

Next, it is determined whether all reading has been completed by referring to the number of sectors in R5R102 (step 511). If not, the next address is set and the process returns to step S6 to repeat reading.

When the reading is completed, the state register 109 displays no error (step 512), the status register 105 displays the read completion (step 513), and an interrupt signal is sent to the CC2 (step knob 514). The CC2 detects the no-error indication in the status register 109 and the completion indication in the status register 105 to identify the completion of data transfer.

If there is an error in step S9, status register 1
09 is displayed as an error (step 515), and CC2
An interrupt signal is sent to (step 514).

The CC 2 detecting the interrupt signal recognizes an error from the error indication in the status register 109 and the absence of a completion indication in the status register 105, and sends out a read record address command.

As shown in FIG. 4, the MPU 3 reads and interprets the read record address command of CMRloo (step 550), uses the address management program 113 to transfer it to the status register 109 (step 551), and sends it to the peripheral bus 7. , CC2 of the information (step 552).

CC2 sends the address and the number of remaining sectors to FMCI'
CARIOI and R5R102, and set the read data command to CMRloo to restart reading.

〔Effect of the invention〕

As explained in detail above, in the present invention, the auxiliary memory control device constantly records the address of the auxiliary memory being accessed, and when a data error occurs, the central control device directly records the address. Because you can know
This eliminates the need for means for calculating addresses for re-access, and has the effect of eliminating increase in re-access time due to such means.

[Brief Description of the Drawings] Fig. 1 is a principle block diagram of the present invention; Fig. 2 is a block diagram of an auxiliary memory control device according to an embodiment of the present invention; Fig. 3 is an explanatory diagram of the read procedure of the present invention; This figure is an explanatory diagram of the restart address sending procedure of the present invention, and FIG. 5 is a block diagram of a conventional auxiliary memory control device. In the figure, 1' is an auxiliary memory control device, 103 is a microprocessor, 109 is a status register, 110 is a memory, 111 is an address management table, 112 is an address management means, and 150 is an auxiliary memory control unit.

Claims (1)

[Claims] A microprocessor (103) that controls the entire device;
A memory (110) that stores programs used by the microprocessor (103), an auxiliary memory control unit (150) that controls the auxiliary memory and checks accessed data, and records the results of judgments on the accessed data. an address management table (111) for recording the data address of the auxiliary memory being accessed and the number of accessed records; Address management means (112) is provided to record in a management table (111) and record the data address at the time of error occurrence and the number of remaining records in the status register (109), and when an error is detected in the accessed data, Using the address management table (111), obtain the data address at the time of error and the number of remaining records, and store the data in the status register (109).
1. An auxiliary memory control device characterized in that it is possible to record data in the memory and resume access.