JPH04211822A - Memory controller - Google Patents

Abstract

PURPOSE:To improve processing speed accompanying a data write request from a host processor by providing the title memory controller which is interposed between the host processor and an external auxiliary storage device, and simultaneously, is connected to a cache memory to store a part of data in the external auxiliary storage device. CONSTITUTION:When both an interface unit 30 at a host processor side and a buffer memory 50 at an external auxiliary storage device side are active, a data read signal IORD1 is supplied to the unit 30, and simultaneously, a data write signal IOWR1 and a memory write signal MWR are generated to the buffer memory 50 and the cache memory 5 respectively.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller, and more particularly to a memory controller for a hard disk drive, floppy disk drive, optical disk drive, cartridge magnetic tape, etc. as an external auxiliary storage device of an information processing system.

0002

2. Description of the Related Art External auxiliary storage devices as described above are often used in information processing systems. A memory controller is interposed between the device and the host processor and controls data transfer between the two. In general, a memory controller includes an interface unit that controls the interface with the host processor, a buffer memory that temporarily stores data to be written to an external auxiliary storage device and data read from the device, and an interface unit that controls the interface with the host processor. It has a control unit that controls data transfer. In response to requests from the host processor, the memory controller writes data from the host processor to an external auxiliary storage device, reads data stored in the device, and supplies the data to the host processor.

[0003] A host processor may reuse data written to an external auxiliary storage device. Since the data has been written to the external auxiliary storage device, it is necessary to access the external auxiliary storage device in order to pass the data to the host processor. However, since the access speed of the external auxiliary storage device is relatively slow, it takes time to supply data to the host processor.

[0004] Therefore, cache memory techniques have been applied to such memory controllers as well. That is,
It is configured to connect and control cache memory,
Data written to the external auxiliary storage device is also stored in the cache memory. If the stored data is the same as the data subsequently requested by the host processor, the cache memory is accessed and the data is passed to the host processor. No external auxiliary storage access is required.

[0005]

[Problems to be Solved by the Invention] In this way, data in response to a data write request from the host processor is stored in the cache memory and also written in the external auxiliary storage device, but the data is first stored in the interface unit. is transferred to cache memory from
It is then transferred from the cache memory to the buffer memory and therefore to the external auxiliary storage device. This is because data transfer is performed using a DMA (direct memory access) method, and DMA transfer between the interface unit and cache memory and DMA transfer between buffer memory and cache memory are performed on mutually independent transfer channels. As a result, the time it takes to write data from the host processor to the external auxiliary storage device is doubled compared to a device without a cache memory.

Accordingly, it is an object of the present invention to provide an improved memory controller for performing data transfers between a host processor and external auxiliary storage.

Another object of the present invention is to provide a memory controller that reduces the time required to complete data writing based on a data write request.

[0008]

[Means for Solving the Problems] A memory controller according to the present invention detects that both an interface unit and a buffer memory are in a ready state, and simultaneously transfers data from the interface unit to both memories. It is a feature.

More specifically, both the interface unit and the buffer memory detect the occurrence of a data transfer request, and the interface unit receives a data read signal and the buffer memory and cache memory receive a data write signal, respectively. At the same time, the data read from the interface unit is transferred to both memories.

[0010] With this configuration, extra data transfer cycles are not required, and data write time is shortened.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing part of an information processing system having a memory controller according to an embodiment of the present invention. The controller 1 is configured as a semiconductor integrated circuit device and includes an interface unit 30, a data transfer control unit 40, a buffer memory 50, and a format control unit 60. In this embodiment, the interface unit 30 is SCSI (Small
Computer System Interface
ce) system, and is therefore connected to the host processor 2 via the terminal 10 and the SCSI bus 21. The format control unit 60 is connected to the external auxiliary storage device 4 via the terminal 12 and the communication bus 41, and reads/writes data to/from the device. In this embodiment, a hard disk drive is used as the device 4. floppy disk drive, optical disk drive,
The same applies to cartridge magnetic tape. Data to be written to the storage device 4 and data read from the storage device 4 are transferred between the format control unit 60 and the buffer memory 50 via the bus 20. FIFO (F
irst-in-first-out) memory can be used as buffer memory 50. Units 30, 40 and 60 and buffer memory 50 are interconnected via internal processor bus 17. The bus 17 is further connected to the microprocessor 3 via a terminal 11 and an external processor bus 31 . The processor 3 controls the entire operating sequence of the controller 1.

The data transfer control unit 40 transfers data using the DMA transfer method. That is, the unit 40 includes the interface unit 30 and the buffer memory 50.
It receives first and second data transfer request signals DRQ1 and DRQ2 from. Signal DRQ1 indicates that unit 30 is ready to output data from host processor 2 onto data bus 19 or accept data on bus 19, and signal DRQ2 indicates that memory 30 is ready to output data from unit 60 onto bus 19. Can be output on or bus 1
9 indicates that it is ready to receive the data above. In response to the request signal DRQ1, the unit 40 returns an acknowledge signal DAK1 to the unit 30 to activate the unit 30. Similarly, an acknowledge signal DAK2 is returned to the buffer memory 50 in response to the request signal DRQ1. The data transfer control unit 40 further supplies data read and data write signals to the unit 30 or the memory 50 to output data and take in data, respectively. , IOW1 and data read and write signals to the buffer memory 50 IOR2, IOW2
is set up separately. Data read signal IOR1
, IOR2 instruct the unit 30 and memory 50 to output internal data onto the bus 19, respectively, and data write signals IOW1 and IOW2 instruct the timing to take in data on the bus 19. data bus 1
A transfer control unit 40 and a terminal 13 are also connected to the terminal 9, and a cache memory 5 provided externally is connected to the terminal 13. Transfer control unit 40 further generates address information and memory read and write signals MRD and MWR. Address information is supplied to memory 5 via bus 21 and terminal 14, and signals MRD and MWR are supplied via terminals 15 and 16, respectively.

Referring to FIG. 2, data transfer unit 4
0 has a pair of parameter registers 401, 501, a pair of data transfer sequencers 403, 503, and a pair of address counters 404, 504. register 4
01, the sequencer 403 and the counter 404 are the first
Assigned as a channel to control data transfer between buffer memory 50 and cache memory 5, register 5
01, sequencer 503 and counter 504 are assigned as a second channel to control data transfer between interface unit 30 and cache memory. In each of the registers 401 and 501, parameter data is set by the microprocessor 3, including information specifying the data transfer direction, information indicating the number of bytes of data to be transferred, information indicating whether to permit data transfer, etc. be done. Each of the address counters 404 and 504 includes
The data transfer start address for the cache memory 5 is also set by the microprocessor 3. Register 401 (501) and data transfer request signal D
In response to RQ1 (DRQ2), sequencer 403 (5
03) are the signals DAK1 (DAK2) and IORD mentioned above.
1 (IORD2), IOWR1 (IOWR2), MRD
and MWR are generated according to a predetermined sequence, and the contents of the counter 404 (504) are updated. Data transfer control unit 40 further comprises four AND gates 601, 603, 605, 608, three OR gates 604, 606, 607, and an inverter 450 according to the invention. Furthermore, the parameter register 501 has a mode flag 502. The flag 502 is set to "1" when data transfer from the interface unit 30 to the buffer memory 50 and cache memory 5 is executed simultaneously, and is reset to "0" at other times.

Next, the operation will be explained. When the interface unit 30 receives a command from the host processor 2 to write data to the external auxiliary storage device 4, the unit 30 supplies the same command to the microprocessor 3 via the buses 17, 31 and the terminal 11. The microprocessor 3 decodes the command and performs the following operations to cause simultaneous data transfer from the unit 30 to the memories 50 and 5. That is, control information is given to the format controller 60 to write data to the device 4, and information necessary for data transfer from the interface unit 30 to the cache memory 5 is set in the parameter register 501 and counter 504. Mode flag 502 is set to "1". Data transfer prohibition information is given to the parameter register 401 in order to deactivate the sequencer 403. Thus, simultaneous data transfer from interface unit 30 to cache memory 5 and buffer memory 50 is enabled.

In order to perform simultaneous data transfer, interface unit 30 and buffer memory 50 are required.
both need to be in the ready state. Such state detection is performed by AND gates 603 and 605 checking the generation of both data transfer request signals DRQ1 and DRQ2. As shown in FIG. 3, both the unit 30 and the memory 50 are in the ready state and the request signals DRQ1, DR
When Q2 becomes active, sequencer 503 receives a data transfer request signal. In response, sequencer 503 returns an acknowledge signal DAK1 to unit 30. Since sequencer 403 is inactive, it does not generate acknowledge signal DAK2 even if it receives request signal DRQ2. However, the acknowledge signal DAK1
The generation of is caused by AND gate 601 and OR gate 606
As a result, the acknowledge signal ACK2 is generated as shown in FIG. Sequencer 503 further outputs the address of address counter 504, and generates data read signal IOR1 and memory write signal MWR. In response to signal IOR1, interface unit 30 outputs data from host processor 2 onto bus 19. Sequencer 403 receives data write signal IO
WR is not generated, but the memory write signal MWR is AN
D gate 608 and OR gate 607 generate data write signal IOWR2. Thus, data read from unit 30 on bus 19 is transferred to both cache memory 5 and buffer memory 50 simultaneously. Thereafter, the address of counter 504 is updated. Furthermore, in response to signals IOR1 and IOW2, unit 30 and buffer memory 50 invert their respective request signals DRQ1 and DRQ2 to low level. When unit 30 and memory 50 become ready again, the operations described above are performed.

In this way, data from interface unit 30 is transferred to both cache memory 5 and buffer memory 50 simultaneously.

If mode flag 502 is left at "0", data from unit 30 is transferred only to cache memory 5. The data stored in memory 5 is then transferred to buffer memory 50 using sequencer 403 and counter 404.

Referring to FIG. 4, a data transfer control unit in a memory controller according to another embodiment of the present invention is shown. Functional parts that are the same as those in FIG. 2 are indicated by the same numbers, and their explanations will be omitted. In this embodiment, data can be transferred simultaneously from the buffer memory 50 to the cache memory 5 and the interface unit 30, and four AND gates 451, 453, 454,
458, three OR gates 452, 456, 457 and an inverter 450 are further provided. Further, a mode flag 402 is provided in the parameter register 401.

When the interface unit 30 receives a data request command from the host processor 2, the command is supplied to the microprocessor 3 and decoded. Although not shown, the microprocessor 3 is provided with a memory that stores sector information and tag information indicating the data area of the external storage device 4 that is stored (copied) by the cache memory 5. Based on that information,
Microprocessor 3 determines whether cache memory 5 stores the data requested by host processor 2. If it is determined that the data is being stored, the microprocessor 3 transfers the information necessary for data transfer to the parameter register 5.
01 in the counter 504, and on the other hand, information for inactivating the sequencer 403 is written in the parameter register 401. Mode flags 402 and 502 are reset to "0". When the sequencer 503 receives the data transfer request signal DRQ1 from the unit 30, it sends an acknowledge signal D.
AK1 is returned through OR gate 456. counter 50
4 to the cache memory 5, and further outputs the data write signal IOWR1 and memory read signal MR.
Generates D. As a result, data is read from cache memory 5 and transferred to interface unit 30. The data is sent to host processor 2. Such operations are performed until the requested number of data is reached. Thus, no access is made to the external storage device 4, and high-speed data transfer is performed.

On the other hand, when the cache memory 5 does not store the data requested by the host processor 2, the data must be obtained from the external storage device 4. At this time, in preparation for another request from the host processor 2,
Data read from device 4 is stored in cache memory 5 and simultaneously transferred to unit 30.

That is, the microprocessor 3 supplies information necessary for reading data from the external storage device 4 to the format control unit 60, and also supplies information necessary for data transfer between the memories 50-5 to the parameter register 401 and counter 404. give. The mode flag 401 is “
1”.The register 501 contains the sequencer 5.
Information to deactivate 03 is given.

As shown in FIG. 5, when the buffer memory 50 and the interface unit 30 are both ready, that is, when the buffer memory 50 holds data from the storage device 4 and the unit 30 is ready to accept data, the AND gate 451 is activated. , 453, the sequencer 403 receives the data request signal. In response, the acknowledge signal DACK2 is returned to the buffer memory 50, and the acknowledge signal DACK2 is also returned to the unit 30 by the AND gate 454 and the OR gate 456.
1 will be returned. Sequencer 402 causes counter 404 to output an address, and generates data read signal IORD2 and memory write signal MWR. Memory write signal MWR causes AND gate 458 and OR gate 457 to generate data write signal IOWR1. Thus, the data read from the buffer memory 50 is stored in the cache memory 5 via the bus 19 and is also transferred to the interface unit 30 at the same time.

As described above, in this embodiment, simultaneous data transfer from the interface unit 30 to the cache memory 5 and the buffer memory 50, and simultaneous data transfer from the buffer memory 50 to the cache memory 5 and the interface unit 30 are performed. .

It is clear that the present invention is not limited to the above embodiments and can be modified as appropriate. For example, the microprocessor 3 and the cache memory 5 can be combined with the controller 1 into a single chip.

[0026]

As described above, according to the present invention, a memory controller is provided which can simultaneously transfer data from an interface unit on the host processor side to both a cache memory and a buffer memory on an external storage device side, and the data transfer rate is improved. can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing part of an information processing system using a memory controller according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of the data transfer control unit shown in FIG. 1;

FIG. 3 is a timing diagram showing the operation of this embodiment.

FIG. 4 is an internal configuration diagram of a data transfer control unit used in a memory controller according to another embodiment of the present invention.

FIG. 5 is a timing diagram showing the operation of this embodiment.

Claims (2)

[Claims] 1. A first memory that temporarily stores data to be written to an external storage device; a second memory; an interface unit that manages an interface operation with a host processor and temporarily stores data from the host processor; a control unit coupled to a first memory, said second memory and said interface unit for simultaneously transferring data from said host processor from said interface unit to said first and second memories. memory controller. 2. A first memory that temporarily stores data to be written to an external storage device and data read from the external storage device; and a second memory that controls interface operations with a host processor and receives data from the host processor. and an interface unit coupled to the first memory, the second memory and the interface unit to temporarily store data from the host processor to the first and second memory. simultaneously transfer the read data to the first memory.
a control unit that simultaneously transfers data from the second memory to the second memory and the interface unit.