JPS631756B2 - - Google Patents

Info

Publication number
JPS631756B2
JPS631756B2 JP55093613A JP9361380A JPS631756B2 JP S631756 B2 JPS631756 B2 JP S631756B2 JP 55093613 A JP55093613 A JP 55093613A JP 9361380 A JP9361380 A JP 9361380A JP S631756 B2 JPS631756 B2 JP S631756B2
Authority
JP
Japan
Prior art keywords
semiconductor element
inner lid
container
semiconductor
metallized wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55093613A
Other languages
Japanese (ja)
Other versions
JPS5718340A (en
Inventor
Tetsushi Wakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9361380A priority Critical patent/JPS5718340A/en
Publication of JPS5718340A publication Critical patent/JPS5718340A/en
Publication of JPS631756B2 publication Critical patent/JPS631756B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特にその外囲器
（パツケージ）の構造に関するものである。一般
に半導体装置は、たとえばセラミツクあるいはコ
バールなどの支持台上に半導体素子を固着し、そ
の半導体素子を、たとえばセラミツクなどの壁部
材および蓋部材などを用いて気密封入している。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of its envelope (package). Generally, in a semiconductor device, a semiconductor element is fixed on a support base made of ceramic or Kovar, and the semiconductor element is hermetically sealed using a wall member made of ceramic, a lid member, and the like.

この封入されるべき半導体素子が高密度の集積
回路、特にMOSデバイスや電荷転送デバイスな
どで構成される場合、外囲器構成部材特に封止材
からの放射線照射、特にα線照射により半導体素
子に例えば一般にソフトエラーと称される記憶情
報の破壊等の特性劣化を生ずる恐れがある。 When the semiconductor element to be encapsulated is composed of a high-density integrated circuit, especially a MOS device or a charge transfer device, the semiconductor element may be exposed to radiation from the envelope components, especially the encapsulant, especially α-ray irradiation. For example, there is a risk that characteristic deterioration such as destruction of stored information, generally referred to as a soft error, may occur.

これは、自然界に存在し放射性崩壊する際にα
線を生ずるウラニウム（Ｕ）あるいはトリウム
（Th）等の放射性同位元素が、前記封止材として
の低融点ガラスや鉛と錫等から成るソルダーの中
に含まれていることによる。 This exists in the natural world and when radioactively decays, α
This is because radioactive isotopes such as uranium (U) or thorium (Th) that generate lines are contained in the low-melting glass or solder made of lead and tin as the sealing material.

発生したα線は半導体素子内に侵入すると、正
孔と電子の対を発生し、該正孔あるいは電子のい
ずれかが該半導体素子内の活性領域に注入され
て、例えば前述の如く記憶情報の破壊を招く。 When the generated α rays enter the semiconductor element, they generate pairs of holes and electrons, and either the holes or the electrons are injected into the active region within the semiconductor element, and for example, as described above, storage information is generated. Invite destruction.

従つて、該半導体素子において活性領域が形成
されている半導体基板表面領域へのα線の照射、
侵入の防止を図ることが重要であり、前記外囲器
にあつて一般に該半導体素子の表面付近に位置す
る蓋部材及び封止材から発生するα線の抑制が必
要となる。 Therefore, irradiation of α rays to the semiconductor substrate surface region where the active region is formed in the semiconductor element,
It is important to prevent intrusion, and it is necessary to suppress alpha rays generated from the lid member and sealing material of the envelope, which are generally located near the surface of the semiconductor element.

蓋部材から発生されるα線は、該蓋部材の内面
すなわち半導体素子に対向する面に例えばシリコ
ン板あるいはポリイミド板等を粘り付けることに
より、α線の半導体素子への侵入を阻止すること
ができるとされている。しかしながらかかるシリ
コン板、ポリイミド板等のみでは封止材から発生
されるα線を有効に阻止することができない。一
方封止材を金―錫（Au―Sn）等の金系鑞材から
構成すればα線の発生が極めて少ない。しかしな
がら金系鑞材の使用は当該半導体装置の高価格化
を招いてしまう。 The alpha rays generated from the lid member can be prevented from entering the semiconductor element by attaching, for example, a silicon plate or a polyimide plate to the inner surface of the lid member, that is, the surface facing the semiconductor element. It is said that However, such silicon plates, polyimide plates, etc. alone cannot effectively block α rays generated from the sealing material. On the other hand, if the sealing material is made of a gold-based brazing material such as gold-tin (Au-Sn), the generation of α rays is extremely small. However, the use of gold-based brazing material increases the cost of the semiconductor device.

本発明は前述の点に鑑みなされたもので、その
目的は半導体素子表面への放射線照射、特にα線
照射をより簡単な構造をもつて阻止し、α線照射
による半導体素子の特性化を防止することができ
る構造を有して成る半導体装置を提供することに
ある。 The present invention has been made in view of the above-mentioned points, and its purpose is to prevent radiation irradiation, particularly alpha ray irradiation, to the surface of a semiconductor element with a simpler structure, and prevent the characteristics of the semiconductor element due to alpha ray irradiation. An object of the present invention is to provide a semiconductor device having a structure that allows for

このため本発明によれば、半導体素子と、前記
半導体素子を収容する収容容器と、前記半導体素
子を前記収容容器内に気密封止する憲とを備えた
半導体装置において、前記半導体素子上に、半導
体素子の側面と前記半導体素子の側面に対向する
容器内面とを仕切る仕切り板を有する内蓋を配設
してなる半導体装置が提供される。 Therefore, according to the present invention, in a semiconductor device including a semiconductor element, a housing container for housing the semiconductor element, and a cover for hermetically sealing the semiconductor element in the housing container, on the semiconductor element, A semiconductor device is provided that includes an inner lid having a partition plate that partitions a side surface of a semiconductor element and an inner surface of a container facing the side surface of the semiconductor element.

次に本発明を実施例をもつて詳細に説明する。 Next, the present invention will be explained in detail using examples.

第１図は本発明による半導体装置の第１の実施
例を示し、容器の長手方向（外部接続端子配列方
向）に沿う断面を示す。また第２図は第１図A1
―A1断面を示す。 FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, and shows a cross section along the longitudinal direction of the container (external connection terminal arrangement direction). Also, Figure 2 is the same as Figure 1 A 1
-A shows 1 cross section.

図において、１１は半導体集積回路素子、１２
は該素子１１を金―シリコン（Au―Si）等の鑞
材１３をもつて固着し収容してなる多層セラミツ
ク製容器、１４は該容器１２に半田等の封止材１
５をもつて固着され容器１２内を気密封止するセ
ラミツク製蓋である。また１６は外部接続端子で
あり、前記素子１１の電極は金線又はアルミニウ
ム線からなるリード線１７及び該リード線１７が
接続されるモリブデン又はタングステン等を主体
とするメタライズ配線層１８を介して外部接続端
子１６に接続される。一般にメタライズ配線層１
８の表面には予め金めつき処理が施される。この
ような半導体集積回路素子の気密封止構造は周知
である。 In the figure, 11 is a semiconductor integrated circuit element, 12
14 is a multilayer ceramic container in which the element 11 is fixed and housed with a solder material 13 such as gold-silicon (Au-Si), and 14 is a sealing material 1 such as solder in the container 12.
This is a ceramic lid which is fixed with a clasp 5 and hermetically seals the inside of the container 12. Reference numeral 16 denotes an external connection terminal, and the electrode of the element 11 is externally connected via a lead wire 17 made of gold wire or aluminum wire and a metallized wiring layer 18 mainly made of molybdenum or tungsten to which the lead wire 17 is connected. It is connected to the connection terminal 16. Generally, metallized wiring layer 1
The surface of 8 is pre-plated with gold. Such hermetically sealed structures for semiconductor integrated circuit elements are well known.

本発明はこのような半導体装置において、素子
１１と蓋１４との間に素子１１表面を覆う如くα
線遮蔽用内蓋１００を配設する。内蓋１００はコ
バール、アルミニウム、42アロイ等から選択され
た原さ300μm〜0.1mmの金属の板又は箔からプレ
ス法等により形成され、半導体装置の長手方向に
延長された延長部１０１が容器１２内に設けられ
た段部１２Ａにおいて機械的に支持されて該容器
内に収容される。該段部１２Ａの高さは予め選択
され、内蓋１００とリード線１７との接触が防止
される。また内蓋１００は容器１２内の素子収容
部空間とほぼ同一の幅を有し、素子１１部にあつ
ては素子１１の側面にほぼ平行に延在して素子１
１の表面よりも下方に延び該素子１１の側面と該
素子１１の側面に対向する容器１２の内壁面さら
に、本発明では、リード線１７、素子１１上のリ
ード線接続部及びメタライズ配線層１８も内蓋１
００で覆われており、内蓋１００は、半導体セル
全域を覆うことができ、α線遮へい効果をより完
全なものとしている。なお内蓋１００の延長部１
０１は段部１２Ａに固定される必要はなく、内壁
１００は容器１２内において移動可能とされてよ
い。内壁１００は質量が小であるため移動しても
容器１２及び蓋１４等に損傷を与えない。かかる
内蓋１００のみを第３図に示す。 In such a semiconductor device, the present invention provides α between the element 11 and the lid 14 so as to cover the surface of the element 11.
A line shielding inner cover 100 is provided. The inner lid 100 is formed by a pressing method or the like from a metal plate or foil selected from Kovar, aluminum, 42 alloy, etc. and having an original size of 300 μm to 0.1 mm. It is mechanically supported by a stepped portion 12A provided therein and housed in the container. The height of the stepped portion 12A is selected in advance to prevent contact between the inner lid 100 and the lead wire 17. Further, the inner lid 100 has approximately the same width as the element accommodating space in the container 12, and extends approximately parallel to the side surface of the element 11 in the case of the element 11 portion.
Furthermore, in the present invention, the lead wire 17, the lead wire connection portion on the element 11, and the metallized wiring layer 18 Inner lid 1
00, and the inner lid 100 can cover the entire semiconductor cell, making the α-ray shielding effect more complete. Note that the extension part 1 of the inner lid 100
01 need not be fixed to the stepped portion 12A, and the inner wall 100 may be movable within the container 12. Since the inner wall 100 has a small mass, it does not damage the container 12, the lid 14, etc. even if it moves. Only such an inner lid 100 is shown in FIG.

このような本発明による半導体装置にあつて
は、蓋１４、封止材１５等から発生し素子１１へ
向うα線は内蓋１００によつて阻止され、素子１
１表面へは到達しない。また容器１２内の側壁面
から発生するα線も内蓋１００及びその仕切り板
１０２により有効に阻止され素子１１表面へは到
達しない。前記容器の段部１２Ａの側壁面と素子
１１との間にはリード線１７が配設されることに
より仕切り板の配設は困難であるが、該段部１２
Ａの側壁面から発生するα線の素子１１の表面へ
の入射角は小であり、該段部１２Ａの側壁面の存
在は実質的に問題とならない。 In such a semiconductor device according to the present invention, alpha rays generated from the lid 14, the sealing material 15, etc. and directed toward the element 11 are blocked by the inner lid 100, and
1 does not reach the surface. Further, α rays generated from the side wall surface inside the container 12 are effectively blocked by the inner lid 100 and its partition plate 102, and do not reach the surface of the element 11. Since the lead wire 17 is disposed between the side wall surface of the stepped portion 12A of the container and the element 11, it is difficult to provide a partition plate.
The angle of incidence of α rays generated from the side wall surface of A onto the surface of the element 11 is small, and the presence of the side wall surface of the stepped portion 12A does not substantially pose a problem.

本発明の第２の実施例を第４図及び第５図に示
す。 A second embodiment of the invention is shown in FIGS. 4 and 5.

本実施例において前記第１の実施例に対応する
箇所には同一符号を付す。なお第５図は第４図の
A2―A2断面を示す。 In this embodiment, parts corresponding to those in the first embodiment are given the same reference numerals. Note that Figure 5 is similar to Figure 4.
A 2 - A 2 cross section is shown.

本実施例においては、容器１２の内蓋１００の
支持部１２Ｂがメタライズ配線層１８の表面に塗
布された例えばアルミナペーストの硬化層からな
る絶縁層から構成される。また内蓋１００の延長
部１０１の端部１０１Ａは容器内方向にほぼ直角
に曲げられ該内蓋１００とリード線１７との接触
を防止する。該内蓋１００も仕切り板１０２を有
し、また容器１２内において移動可能とされてよ
い。かかる内蓋１００のみを第６図に示す。 In this embodiment, the support portion 12B of the inner lid 100 of the container 12 is composed of an insulating layer made of, for example, a hardened layer of alumina paste applied to the surface of the metallized wiring layer 18. Further, the end portion 101A of the extension portion 101 of the inner lid 100 is bent at a substantially right angle toward the inside of the container to prevent contact between the inner lid 100 and the lead wire 17. The inner lid 100 also has a partition plate 102 and may be movable within the container 12. Only such an inner lid 100 is shown in FIG.

このような本発明による半導体装置にあつて
は、蓋１４、封止材１５等から発生し素子１１へ
向うα線は内蓋１００によつて阻止され、素子１
１表面へは到達しない。また容器１２内の側壁面
から発生するα線も内蓋１００及びその仕切り板
１０２により有効に阻止され素子１１表面へは到
達しない。また、前記支持部１２Ｂは塗布形成さ
れた絶縁層から構成されるためその端部の表面積
は極めて小さく、かかる絶縁層の端部表面から発
生するα線の素子１１の表面への入射角は前記第
１の実施例に比較しても小さくかかる絶縁層の存
在は実質的に問題とならない。 In such a semiconductor device according to the present invention, alpha rays generated from the lid 14, the sealing material 15, etc. and directed toward the element 11 are blocked by the inner lid 100, and
1 does not reach the surface. Further, α rays generated from the side wall surface inside the container 12 are effectively blocked by the inner lid 100 and its partition plate 102, and do not reach the surface of the element 11. Further, since the supporting portion 12B is composed of an insulating layer formed by coating, the surface area of the end portion thereof is extremely small, and the incident angle of α rays generated from the end surface of the insulating layer onto the surface of the element 11 is as described above. The presence of the insulating layer, which is smaller than that of the first embodiment, does not substantially pose a problem.

第７図は前記本発明の第２の実施例における内
蓋１００の変形例を示す。本実施例にあつては延
長部１０１の各隔部１０１Ｂがほぼ直角に曲げら
れ前記第２の実施例における端部１０１Ｂと同様
内蓋１００のリード線１７との接触を防止する。 FIG. 7 shows a modification of the inner lid 100 in the second embodiment of the present invention. In this embodiment, each partition 101B of the extension 101 is bent at a substantially right angle to prevent contact with the lead wire 17 of the inner lid 100, similar to the end 101B in the second embodiment.

なお本発明の第２の実施例並びにその変形例に
あつては封止処理の際に容器１２内へ収容されて
いる内蓋１００の上面が封止材１５により濡れる
ことを防止するために、内蓋１００の上面が容器
１２の封止面１２Ｃの高さよりも0.1〜0.15〔mm〕
程低くなるよう内蓋１００の端部１０１Ａ，１０
１Ｂの高さを設定する。 In addition, in the second embodiment of the present invention and its modifications, in order to prevent the upper surface of the inner lid 100 housed in the container 12 from getting wet by the sealing material 15 during the sealing process, The upper surface of the inner lid 100 is 0.1 to 0.15 mm higher than the sealing surface 12C of the container 12.
The ends 101A, 10 of the inner lid 100 are
Set the height of 1B.

以上実施例をもつて説明したように、本発明に
よれば容器内において、半導体素子と蓋、封止材
との間に金属板又は金属箔からなる内蓋が配設さ
れる。このため蓋、封止材等から発生する放射線
特にα線はかかる内蓋によつて阻される。またか
かる内蓋は、半導体素子のリード線が導出されな
い方向の側面にほぼ平行に延びる仕切り板を有
し、該半導体素子の側面に位置する容器内壁面及
び封止材から発生するα線の該半導体素子への到
達を阻止することができる。 As described above with reference to the embodiments, according to the present invention, an inner lid made of a metal plate or metal foil is provided between the semiconductor element, the lid, and the sealing material in the container. Therefore, radiation, especially alpha rays, generated from the lid, sealing material, etc. are blocked by the inner lid. Further, the inner lid has a partition plate extending substantially parallel to the side surface of the semiconductor element in the direction from which the lead wires are not led out, and the inner lid has a partition plate that extends substantially parallel to the side surface in the direction from which the lead wires of the semiconductor element are led out, and is used to absorb alpha rays generated from the inner wall surface of the container and the sealing material located on the side surface of the semiconductor element. It is possible to prevent it from reaching the semiconductor element.

このような内蓋の配設は当該半導体装置の組立
て工程に工程の増加を来たすが、前述の如く封止
材として金―錫等からなる鑞材を用いるよりも製
造コストを低下させることができ、より低価格化
が要求される半導体装置の製造においては有利で
ある。 Providing such an inner cover increases the number of steps in the assembly process of the semiconductor device, but as described above, it can reduce manufacturing costs compared to using a solder material made of gold-tin or the like as a sealing material. This is advantageous in the manufacture of semiconductor devices, which requires lower costs.

なお前記実施例にあつては、内蓋としてコバー
ル、アルミニウム、42アロイ等の金属からなる板
又は箔を用いる例を掲げたが、これらの金属板又
は箔の表面を耐熱性樹脂、例えばポリイミドによ
り被覆してリード線等との接触を防止してもよ
い。またかかるポリイミド樹脂はα線の阻止部材
として有効とされていることから、内蓋をポリイ
ミド樹脂のみで構成してもよい。更に内蓋はその
延長部において適当な固着材をもつて容器内に固
着されてもよい。 In the above embodiments, a plate or foil made of metal such as Kovar, aluminum, or 42 alloy was used as the inner lid. It may be covered to prevent contact with lead wires and the like. Moreover, since such polyimide resin is effective as a blocking member for alpha rays, the inner lid may be made of only polyimide resin. Furthermore, the inner lid may be secured within the container at its extension with a suitable securing material.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は本発明の半導体装置の第１
の実施例を示す断面図であり、第２図は第１図
A1―A1断面を示す。第３図は本発明の第１の実
施例に適用される内蓋を示す外観斜視図である。
第４図及び第５図は本発明の半導体装置の第２の
実施例を示す断面図であり、第５図は第４図A2
―A2断面を示す。第６図は本発明の第２の実施
例に適用される内蓋を示す外観斜視図である。第
７図は本発明の第２の実施例に適用される内蓋の
変形例を示す外観斜視図である。 図において、１１……半導体集積回路素子、１
２……容器、１４……蓋、１５……封止材、１６
……外部接続端子、１００……内蓋、１０２……
仕切り板。 FIGS. 1 and 2 show a first diagram of a semiconductor device of the present invention.
FIG. 2 is a sectional view showing an example of FIG.
A 1 - A 1 cross section is shown. FIG. 3 is an external perspective view showing the inner cover applied to the first embodiment of the present invention.
4 and 5 are cross-sectional views showing a second embodiment of the semiconductor device of the present invention, and FIG.
-A shows 2 cross sections. FIG. 6 is an external perspective view showing the inner cover applied to the second embodiment of the present invention. FIG. 7 is an external perspective view showing a modification of the inner cover applied to the second embodiment of the present invention. In the figure, 11...semiconductor integrated circuit element, 1
2... Container, 14... Lid, 15... Sealing material, 16
...External connection terminal, 100...Inner cover, 102...
Partition board.

Claims (1)

【特許請求の範囲】 １ 半導体素子と、 前記半導体素子を収容するものであつて、 前記半導体素子が固定されている底部と、 前記底部外側に存在し、互いに向かい合つてな
る１組の第１の段差部と、 前記第１の段差部上方に設けられ、リード線を
介して前記半導体素子と接続されているメタライ
ズ配線層と、 前記メタライズ配線層外側に存在し、互いに向
かい合つてなる１組の 第２の段差部と、 前記第２の段差部上方に設けられた平担部と、 封止材により前記平担部と接着された収容容器
蓋 とを有する半導体収容容器と、 長方形状の平板部と、 前記平板部の対向している第１の辺の各々の中
央部から下向きに設けられている長方形の仕切り
板とを有し、 前記平板部の対向している第２の辺が、前記メ
タライズ配線層と前記平担部の間の部分で支持さ
れ、 前記仕切り板が半導体素子の側面と前記半導体
素子の側面に対向する収容容器内面とを仕切る内
蓋と を有することを特徴とする半導体装置。 ２ 前記第２の辺が下側に折り曲げられてなる内
蓋を有することを特徴とする特許請求の範囲第１
項の半導体装置。 ３ 前記平板部の四隅が下側に折り曲げられてな
る内蓋を有することを特徴とする特許請求の範囲
第１項の半導体装置。 ４ 前記メタライズ配線層と前記平担部との間に
内蓋を支持するための第３の段差部を設けてなる
ことを特徴とする特許請求の範囲第１項の半導体
装置。[Scope of Claims] 1. A semiconductor element, a bottom part that accommodates the semiconductor element and to which the semiconductor element is fixed, and a first set of first parts that are located outside the bottom part and face each other. a metallized wiring layer provided above the first stepped part and connected to the semiconductor element via a lead wire; and a pair of metallized wiring layers located outside the metallized wiring layer and facing each other. a second stepped portion; a flat portion provided above the second stepped portion; and a container lid adhered to the flat portion with a sealing material; and a rectangular partition plate provided downward from the center of each of the opposing first sides of the flat plate part, wherein the opposing second sides of the flat plate part are , the inner lid is supported at a portion between the metallized wiring layer and the flat part, and the partition plate partitions a side surface of the semiconductor element and an inner surface of the container facing the side surface of the semiconductor element. semiconductor devices. 2. Claim 1, characterized in that it has an inner lid formed by bending the second side downward.
Section Semiconductor Devices. 3. The semiconductor device according to claim 1, further comprising an inner lid formed by bending the four corners of the flat plate portion downward. 4. The semiconductor device according to claim 1, further comprising a third stepped portion for supporting an inner lid between the metallized wiring layer and the flat portion.
JP9361380A 1980-07-09 1980-07-09 Semiconductor device Granted JPS5718340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9361380A JPS5718340A (en) 1980-07-09 1980-07-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9361380A JPS5718340A (en) 1980-07-09 1980-07-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5718340A JPS5718340A (en) 1982-01-30
JPS631756B2 true JPS631756B2 (en) 1988-01-13

Family

ID=14087173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9361380A Granted JPS5718340A (en) 1980-07-09 1980-07-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5718340A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2854757B2 (en) * 1992-06-17 1999-02-03 三菱電機株式会社 Semiconductor power module
US6611054B1 (en) * 1993-12-22 2003-08-26 Honeywell Inc. IC package lid for dose enhancement protection

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5637655A (en) * 1979-09-03 1981-04-11 Mitsubishi Electric Corp Semiconductor memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162650U (en) * 1980-04-30 1981-12-03

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5637655A (en) * 1979-09-03 1981-04-11 Mitsubishi Electric Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPS5718340A (en) 1982-01-30

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