JPH0117257B2 - - Google Patents

Info

Publication number
JPH0117257B2
JPH0117257B2 JP58213250A JP21325083A JPH0117257B2 JP H0117257 B2 JPH0117257 B2 JP H0117257B2 JP 58213250 A JP58213250 A JP 58213250A JP 21325083 A JP21325083 A JP 21325083A JP H0117257 B2 JPH0117257 B2 JP H0117257B2
Authority
JP
Japan
Prior art keywords
package
integrated circuit
radiation
metal shield
shield plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58213250A
Other languages
Japanese (ja)
Other versions
JPS60106150A (en
Inventor
Noboru Shiono
Shoichi Shimaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58213250A priority Critical patent/JPS60106150A/en
Publication of JPS60106150A publication Critical patent/JPS60106150A/en
Publication of JPH0117257B2 publication Critical patent/JPH0117257B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H01L2924/167—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

【発明の詳細な説明】 本発明は宇宙環境や原子炉環境等の放射線環境
下で使用する半導体装置のパツケージに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a package for a semiconductor device used in a radiation environment such as a space environment or a nuclear reactor environment.

従来のパツケージはハーメチツク封止とプラス
チツクモールド封止が主なものである。ハーメチ
ツク封止であるセラミツクDIP（デユアルライン
パツケージ）パツケージの例を第１図に示す。半
導体集積回路チツプ２は絶縁体であるセラミツク
（Al2O3）の基板１と蓋４により被覆され気密封
止されている。なお、３はボンデイングワイヤ、
５はパツケージリードである。プラスチツクモー
ルドパツケージでは、セラミツクの代りにプラス
チツクモールド材で半導体集積回路チツプを被覆
しているものである。 Conventional packages are mainly hermetically sealed and plastic molded. An example of a ceramic DIP (dual line package) package that is hermetically sealed is shown in FIG. A semiconductor integrated circuit chip 2 is covered and hermetically sealed with a substrate 1 made of ceramic (Al 2 O 3 ), which is an insulator, and a lid 4. In addition, 3 is bonding wire,
5 is a package lead. In a plastic mold package, a semiconductor integrated circuit chip is covered with a plastic mold material instead of ceramic.

しかし、これら従来のパツケージで封止された
集積回路を高エネルギー電子線・陽子線等の放射
線環境で使用する場合、パツケージ材のセラミツ
クやプラスチツクモールド材を通して放射線が集
積回路チツプへ照射され、集積回路機能を劣化さ
せるという欠点があつた。 However, when integrated circuits sealed in these conventional packages are used in a radiation environment such as high-energy electron beams or proton beams, the integrated circuit chips are irradiated with radiation through the ceramic or plastic molding material of the package, and the integrated circuit The drawback was that it degraded functionality.

本発明は、これらの欠点を解決するため、放射
線の集積回路チツプへの侵入を防止した耐放射線
パツケージを提供するものである。 The present invention addresses these drawbacks by providing a radiation-resistant package that prevents radiation from entering integrated circuit chips.

以下図面により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.

第２図は本発明の実施例であつて、１はセラミ
ツク基板、２は集積回路チツプ、３はボンデイン
グワイヤ線、４はセラミツク蓋、５はパツケージ
リードの従来のセラミツク封止パツケージを金属
シールドキヤツプ６と金属シールド板７によつて
被覆し、集積回路チツプ２からすべての方向に放
射状に延びる直線が必らず金属シールドキヤツプ
６と金属シールド板７によつて阻止されるように
したものである。この金属シールドにより放射線
のパツケージ内部への侵入を防止し、集積回路機
能の劣化を防ぐことが出来る。ここで、金属シー
ルドキヤツプ６はパツケージの側面も被覆し、ど
の方角からも放射線が集積回路チツプ２へ到達す
ることのない構造とする。側面のキヤツプ６はパ
ツケージリード５と絶縁性接着剤で接着しても良
いしパツケージリード５との間に空間を持たせる
構造でも良い。 FIG. 2 shows an embodiment of the present invention, in which 1 is a ceramic substrate, 2 is an integrated circuit chip, 3 is a bonding wire line, 4 is a ceramic lid, and 5 is a conventional ceramic sealed package with a package lead, and a metal shield cap. 6 and a metal shield plate 7, so that straight lines extending radially from the integrated circuit chip 2 in all directions are necessarily blocked by the metal shield cap 6 and metal shield plate 7. . This metal shield prevents radiation from entering the inside of the package and prevents deterioration of integrated circuit functionality. Here, the metal shield cap 6 also covers the side surfaces of the package, so that radiation does not reach the integrated circuit chip 2 from any direction. The side cap 6 may be bonded to the package lead 5 with an insulating adhesive, or may have a structure in which a space is provided between the cap 6 and the package lead 5.

第３図は論理VLSI（Very Large Scale
Integration）用多ピンパツケージでの実施例を
示す。パツケージリード５の部分を除いて金属シ
ールドキヤツプ６と金属シールド板７により放射
線のパツケージ内部への侵入を防止するものであ
る。この場合は、パツケージリード５を通つて侵
入する放射線を防ぐことは出来ないが、集積回路
チツプ２とパツケージリード５との距離を離すこ
とにより集積回路チツプ２へ到達する放射線を防
ぐことが出来る。他の種類のパツケージについて
も、セラミツクパツケージ、モールド封止パツケ
ージによらずパツケージリードを除いて金属シー
ルドキヤツプ６と金属シールド板７により全面を
被覆することにより、放射線の集積回路チツプ２
への侵入を防止することが出来る。 Figure 3 shows the logic VLSI (Very Large Scale)
An example of a multi-pin package for integration is shown below. Except for the package lead 5, a metal shield cap 6 and a metal shield plate 7 prevent radiation from entering the inside of the package. In this case, it is not possible to prevent radiation from entering through the package lead 5, but by increasing the distance between the integrated circuit chip 2 and the package lead 5, the radiation reaching the integrated circuit chip 2 can be prevented. For other types of packages as well, regardless of whether they are ceramic packages or mold-sealed packages, by covering the entire surface of the package with a metal shield cap 6 and a metal shield plate 7, excluding the package leads, it is possible to protect the integrated circuit chip 2 from radiation.
It is possible to prevent intrusion into the

第４図には簡易シールド実施例を示す。第２
図、第３図で示した側面シールドを省略し、パツ
ケージの上下面に金属シールド板７を接着する構
造である。第４図にはDIPパツケージの例を示し
たが、他のパツケージにも同様に適用出来る。こ
の実施例では、パツケージの上下より侵入する放
射線を阻止することが出来るが、パツケージの側
面より侵入する放射線を阻止することが出来な
い。しかし、パツケージは薄いので側面より侵入
する放射線の割合いは少なくほとんどの放射線を
阻止することが出来る。 FIG. 4 shows a simple shield embodiment. Second
In this structure, the side shields shown in FIGS. 3 and 3 are omitted, and metal shield plates 7 are bonded to the upper and lower surfaces of the package. Although FIG. 4 shows an example of a DIP package, it can be similarly applied to other packages. In this embodiment, it is possible to block radiation from entering the package from above and below, but it is not possible to prevent radiation from entering from the sides of the package. However, since the package is thin, the percentage of radiation that enters from the sides is small, and most of the radiation can be blocked.

第５図にはさらに効果的なシールドの実施例で
パツケージ内部で下面と側面をシールドする例を
示す。集積回路チツプ２を接着する部分の下面と
側面を金属シールド板８で覆つている。この際、
側面シールド板の高さをチツプの厚さより高くし
ている。下面の金属シールド板８上をメタライズ
し、チツプ接着を行いワイヤボンド後金属シール
ド板の蓋９により気密封止を行つている。この構
造では、金属シールド板の蓋９の面積をチツプ面
積の２倍以上とすることにより、集積回路チツプ
２から全方向に放射状に延びる直線が必らず金属
シールド板８と蓋９で阻止して全方向からの放射
線の侵入を阻止することが出来る。 FIG. 5 shows a more effective shielding embodiment in which the bottom and side surfaces are shielded inside the package. The bottom and side surfaces of the part where the integrated circuit chip 2 is bonded are covered with a metal shield plate 8. On this occasion,
The height of the side shield plate is made higher than the thickness of the chip. The lower surface of the metal shield plate 8 is metallized, chips are bonded, and after wire bonding, airtight sealing is performed with a lid 9 of the metal shield plate. In this structure, by making the area of the lid 9 of the metal shield plate at least twice the area of the chip, straight lines extending radially in all directions from the integrated circuit chip 2 are not necessarily blocked by the metal shield plate 8 and the lid 9. It is possible to prevent radiation from entering from all directions.

第６図には集積回路チツプ２の下面をパツケー
ジ内部の金属シールド板１０で被覆し、チツプの
上面と側面はパツケージ外部の金属シールドキヤ
ツプ６で被覆する実施例を示す。このように、パ
ツケージ内外で金属シールドの各種組合せによ
り、全方向からの放射線の侵入を阻止することが
出来る。 FIG. 6 shows an embodiment in which the bottom surface of the integrated circuit chip 2 is covered with a metal shield plate 10 inside the package, and the top and side surfaces of the chip are covered with metal shield caps 6 outside the package. In this way, by using various combinations of metal shields inside and outside the package, it is possible to prevent radiation from entering from all directions.

第７図に、Alシールド板を通して一方向から
1MeV及び2MeVの電子線をドース量が1014e／cm2
になるようにMOSキヤパシタに照射した後のフ
ラツトバンド電圧VFBの変動とシールド厚さの関
係を示す。対象放射線の飛程の0.5倍程度よりシ
ールド効果が現れ、飛程以上の厚さのシールドに
より、電子線損傷を著しく低減することが出来
る。 Figure 7 shows the view from one direction through the Al shield plate.
1 MeV and 2 MeV electron beam at a dose of 10 14 e/cm 2
The relationship between the fluctuation of the flat band voltage V FB and the shield thickness after irradiating the MOS capacitor so that The shielding effect appears from about 0.5 times the range of the target radiation, and a shield that is thicker than the range can significantly reduce electron beam damage.

陽子、α線等の荷電粒子に対してもそのエネル
ギーに対する飛程以上の厚さのシールドにより、
損傷を著しく低減することが出来る。 Even against charged particles such as protons and alpha rays, the shield is thicker than the range that can withstand the energy.
Damage can be significantly reduced.

シールド材の材質は、対象放射線の飛程（単位
ｇ／cm2）以上の面密度を持つものであればいずれ
の物質でもよいが、体積密度の大きい金属、特に
重金属が薄い厚さで大きな面密度を得ることが出
来るので有利である。但し、第５図及び第６図に
示した実施例の集積回路チツプ接着部の金属は接
着の信頼性を保つため、Siの熱膨張係数に近い金
属のMo，Ｗを用いることが望ましい。 The material of the shielding material may be any material as long as it has a surface density equal to or higher than the range of the target radiation (unit: g/cm 2 ), but metals with high volume density, especially heavy metals, with a thin thickness and a large surface area may be used. This is advantageous because density can be obtained. However, in order to maintain the reliability of the bonding, it is preferable to use Mo and W, which are metals with a coefficient of thermal expansion close to that of Si, as the metal of the integrated circuit chip bonding portion in the embodiments shown in FIGS. 5 and 6.

以上説明したように、本発明は集積回路パツケ
ージ外部あるいは内部の金属シールド板により、
放射線の集積回路チツプへの侵入を阻止すること
が出来るので、集積回路の機能劣化を防止するこ
とが出来るという利点がある。比較的飛程の短い
電子線・陽子線等の荷電粒子線に対しては薄い金
属シールドでそれらの侵入を阻止することが出来
るので、電子線や陽子線が主な放射線である人工
衛星環境での耐放射線パツケージの利用は特に有
効である。 As explained above, the present invention uses a metal shield plate outside or inside an integrated circuit package to
Since it is possible to prevent radiation from entering the integrated circuit chip, there is an advantage that functional deterioration of the integrated circuit can be prevented. A thin metal shield can prevent the intrusion of charged particle beams such as electron beams and proton beams, which have a relatively short range, so they can be used in artificial satellite environments where electron beams and proton beams are the main radiation. The use of radiation-resistant packages is particularly effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のセラミツクパツケージの断面
図、第２図、第３図、第４図、第５図、第６図は
本発明装置の実施例の断面図、第７図は放射線シ
ールド効果を実験的に明らかにした特性例図であ
る。 １……セラミツク基板、２……集積回路チツ
プ、３……ボンデイングワイヤ、４……セラミツ
ク蓋、５……パツケージリード、６……金属シー
ルドキヤツプ、７……金属シールド板、８……集
積回路チツプ直下と側面の金属シールド板、９…
…金属シールド及び気密封止板、１０……集積回
路チツプ直下の金属シールド板。 Fig. 1 is a sectional view of a conventional ceramic package, Figs. It is a diagram showing an example of characteristics experimentally clarified. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... Integrated circuit chip, 3... Bonding wire, 4... Ceramic lid, 5... Package lead, 6... Metal shield cap, 7... Metal shield plate, 8... Integrated circuit Metal shield plate directly below the chip and on the side, 9...
...Metal shield and hermetic sealing plate, 10...Metal shield plate directly below the integrated circuit chip.

Claims (1)

【特許請求の範囲】 １ 集積回路パツケージの外部を該集積回路パツ
ケージ内の集積回路チツプより全方向に放射状に
延びる直線が必らず金属シールド板で阻止される
ように金属板で被覆するとともに該金属板の厚さ
が対象放射線の飛程の0.5倍以上に設定されてい
ることを特徴とする耐放射線パツケージ。 ２ 集積回路パツケージ内の集積回路チツプの接
着部が金属シールド板で構成され、パツケージ外
部の金属シールド板との組合せにより前記集積回
路チツプより全方向に放射状に延びる直線が必ら
ず前記金属シールド板で阻止される構造とすると
とにも該金属板の厚さが対象放射線の飛程の0.5
倍以上に設定されていることを特徴とする耐放射
線パツケージ。[Scope of Claims] 1. The outside of the integrated circuit package is covered with a metal plate so that straight lines extending radially in all directions from the integrated circuit chip in the integrated circuit package are necessarily blocked by a metal shield plate, and A radiation-resistant package characterized in that the thickness of the metal plate is set to 0.5 times or more the range of the target radiation. 2. The adhesive part of the integrated circuit chip in the integrated circuit package is composed of a metal shield plate, and in combination with the metal shield plate outside the package, straight lines extending radially in all directions from the integrated circuit chip are not necessarily connected to the metal shield plate. In addition, the thickness of the metal plate is 0.5 of the range of the target radiation.
A radiation-resistant package characterized by being more than double the radiation resistance.
JP58213250A 1983-11-15 1983-11-15 Radiation proof package Granted JPS60106150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58213250A JPS60106150A (en) 1983-11-15 1983-11-15 Radiation proof package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58213250A JPS60106150A (en) 1983-11-15 1983-11-15 Radiation proof package

Publications (2)

Publication Number Publication Date
JPS60106150A JPS60106150A (en) 1985-06-11
JPH0117257B2 true JPH0117257B2 (en) 1989-03-29

Family

ID=16635988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58213250A Granted JPS60106150A (en) 1983-11-15 1983-11-15 Radiation proof package

Country Status (1)

Country Link
JP (1) JPS60106150A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE340959T1 (en) * 1988-05-06 1990-08-16 Digital Equipment Corp., Maynard, Mass. CIRCUIT CHIP PACK FOR PROTECTION AGAINST ELECTROMAGNETIC INTERFERENCES, ELECTROSTATIC DISCHARGES AND THERMAL AND MECHANICAL VOLTAGES.
US6613978B2 (en) 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US5880403A (en) 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
US5635754A (en) * 1994-04-01 1997-06-03 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US7382043B2 (en) 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7191516B2 (en) 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices
JP4509806B2 (en) * 2005-01-18 2010-07-21 株式会社日立メディコ IC package and X-ray CT apparatus using the same
DE102006055340A1 (en) * 2006-11-23 2008-05-29 Siemens Ag Explosion-proof module construction for power components, in particular power semiconductor components and its manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643614A (en) * 1979-09-17 1981-04-22 Nippon Telegr & Teleph Corp <Ntt> Production of plug for optical fiber connector
JPS56165341A (en) * 1980-05-23 1981-12-18 Nec Corp Semiconductor device
JPS57196547A (en) * 1981-05-28 1982-12-02 Nec Corp Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970347U (en) * 1982-11-02 1984-05-12 ティーディーケイ株式会社 integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643614A (en) * 1979-09-17 1981-04-22 Nippon Telegr & Teleph Corp <Ntt> Production of plug for optical fiber connector
JPS56165341A (en) * 1980-05-23 1981-12-18 Nec Corp Semiconductor device
JPS57196547A (en) * 1981-05-28 1982-12-02 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS60106150A (en) 1985-06-11

Similar Documents

Publication Publication Date Title
US4541003A (en) Semiconductor device including an alpha-particle shield
US5635754A (en) Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US5998867A (en) Radiation enhanced chip encapsulant
US7148084B2 (en) Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US5679975A (en) Conductive encapsulating shield for an integrated circuit
JPS60180150A (en) Semiconductor device
JPH0117257B2 (en)
WO1996022669B1 (en) Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
EP0021643B1 (en) Semiconductor device having a soft-error preventing structure
JPS62125651A (en) Radiation resistant package
US5150180A (en) Packaged semiconductor device with high energy radiation absorbent glass
US6239479B1 (en) Thermal neutron shielded integrated circuits
JPS628032B2 (en)
EP0029858A1 (en) Semiconductor device
US6121672A (en) Raised pedestal radiation shield for sensitive electronics
JP2755360B2 (en) Semiconductor module with alpha particle shielding function
JPS5942983B2 (en) semiconductor equipment
JP3229176B2 (en) Radiation hardened package
JP2877292B2 (en) Semiconductor container and semiconductor device
JPS6028139Y2 (en) semiconductor equipment
JPS631755B2 (en)
JPS631756B2 (en)
JPS6138861B2 (en)
JP4127645B2 (en) Electronic component mounting equipment
JPH01300547A (en) Radiation-resistant package