JPS63175296A - Vertical rom - Google Patents

Abstract

PURPOSE:To realize a high-speed operation with a vertical ROM by providing a pull-up means between the word lines of each memory block and a voltage terminal corresponding to the non-selection level of the word line. CONSTITUTION:Word line selection signals produced from a common decoder circuit XPDCR are selectively transmitted to the word lines W0-Wm of memory blocks MB0 and MB1 via switch MOSFETs Q7-Q9. In such constitution, pull-up means Q10-Q12 are added to set the word line of each memory block at a non-selection level respectively. As a result, the lines W0-Wm are kept at the non-selection levels although the blocks MB0 and MB1 are set under the non- selection states. Then a memory MOSFETQm can be read at a high speed in relevant memory access.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a vertical ROM (read-only memory). It relates to techniques that are effective when used to substantially reduce the amount of waste.

[Conventional technology]

Memory MOSFETs are series-connected (v/1 type), which are either depression run type or enhancement type depending on the storage information.
A ROM connected to the ROM is known.

Regarding such a vertical ROM, for example, Japanese Patent Application Laid-Open No. 59-1
There is a publication No. 16993.

[Problem that the invention seeks to solve]

In the above-mentioned vertical ROM, the storage MOSFETs are connected in series to essentially constitute a data line (bit line or digit line), so it is suitable for increasing storage capacity. be.

In the above-mentioned vertical ROM, when the number of series MOSFETs increases as the storage capacity increases, the read current flowing therein becomes a minute current, so it is conceivable to divide it into a plurality of memory blocks.

In this case, as shown in FIG.
A predecoder XPDCR is provided to form a common selection signal for word lines WO to Wm such as O and MB1,
By transmitting the selection signal to the selected memory block via the switch MOSFET, the decoder circuit can be shared. For example, switch MOSFETQ7 corresponds to word lines WO to Wm of memory block MBO.
~Q9 is provided, and this switch MO5FETQ7~Q9
A selection signal formed by a decoder circuit DCRO provided corresponding to the memory block MBO is supplied to the gate of the memory block MBO. The selection signal formed by the decoder circuit DCRO is also transmitted to the gate of the switch MO5FETQI that connects one end of each series MOSFET of the memory block MBO to the common data vADO. Similar switch MO for other memory blocks MBI
A SFET and a decoder circuit DCR1 are provided.

In such a configuration, word lines of memory blocks placed in a non-selected state are placed in a floating state.

If the non-selected state continues for a relatively long time, the level of each word line WO to Wm decreases to a low level like the ground potential of the circuit due to leakage current or the like. Therefore, in the read operation of the memory block, one of the word lines WO-Wm is set to a low selection level, and all the remaining word lines are set to a high non-selection level, and reading of the memory cell is started. This slows down the read operation. That is, when reading a memory cell, one word line is set to low level, and the storage MOS F connected to that word line is read.
If the ET is a depletion type, current will flow; if it is an enhancement type, no current will flow.The above read current is generated by setting the word line of the other series MOSFET to a high non-select level, regardless of whether it is a depletion type or an enhancement type. It must be turned on. Therefore, when the word line is set to low level as described above, reading from the selected storage MOS FET will not be performed unless it is set to high level.

In this case, as described above, the non-selection level (
In a configuration in which a high level) is transmitted through a word line, as the word line rises to a high level, the switch MOSFET
The transfer voltage supplied between the gate and source of Q7 etc. is reduced and its conductance is reduced, so the rise of the word line is slow. Therefore, the drop in the word line level in the unselected memory block is This is a major cause of slow operation.

Furthermore, since the many word lines are set to high level all at once, a relatively large peak current flows, generating noise in the power supply line of the circuit. This noise on the power supply line also appears on the ground line of the circuit due to capacitive coupling with the ground potential line of the circuit, causing a reduction in the operating margin of the sense amplifier SA that performs a minute current sensing operation.

An object of the present invention is to provide a vertical ROM that operates at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a configuration in which a word line selection signal formed by a common decoder circuit is selectively transmitted to each word line of a plurality of memory blocks via a switch MOS FET, a puller is used to set the word line in each memory block to a non-select level. It is provided with a lifting means.

[For production]

According to the above-mentioned means, even if the memory block is placed in a non-selected state, each word line is maintained at a non-selected level.
T can be read out at high speed.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. Although not particularly limited, the vertical ROM of this embodiment is composed of an N-channel MOSFET. Integrated circuits are therefore formed on semiconductor substrates consisting of single-crystal P-type silicon. The N-channel MOSFET consists of a source region, a drain region, and a polysilicon film formed on the semiconductor substrate surface between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode.

The memory array includes memory blocks MBO and MBI, as exemplarily shown by broken lines in the figure. Each memory block MBO and MBI is formed by a plurality of storage MOSFETQm connected in series. Each storage MOS FETQm is formed as either a depression type or an enhancement type depending on the storage information.

Although not particularly limited, the storage MOSFETQm is formed into a depletion type, and is selectively made into an enhancement type according to storage information. That is, by forming a wiring made of aluminum or the like on the surface of the channel region of the depletion type MOSFET and then introducing an impurity of a conductivity type opposite to that of the substrate gate, an enhancement type memory MOS having a positive threshold voltage can be created. F
In this case, writing to form an ET can be performed by the ion implantation method described above in the final step of assembling a semiconductor integrated circuit. This makes it possible to standardize the manufacturing process for semiconductor integrated circuits, thereby improving manufacturing efficiency.

In this embodiment, one series storage MOS FET is provided in each memory block MBO and MBI for one data line DO. Series M of memory blocks MBO provided on one data line DO
One end of the OS F 87 circuit is connected to the data line DO via a switch MOS F ETQl that receives a selection signal formed by a decoder circuit DCRO, which will be described later. Similarly, switches MO5FETQ2 to Q3 are provided in the series MOSFETs corresponding to the other data lines or Dn of memory block MBO.

Further, each series circuit of memory block MBI is also connected to the data lines no to Dn via switch MOS FETs Q4 to Q6 that receive a selection signal formed by a corresponding decoder circuit DCR1.

Of the memory MOSFETs in series in each of the memory blocks MBO and MBI, the memory MOSFETs corresponding to the horizontal direction
The gates of the 3FETQm are commonly connected to each of the word lines WO to Wm. The word lines WO to Wm of these memory blocks MBO and Ml are respectively coupled to the output selection line of a common predecoder XPDCR via switches MOSFE Ta2 to Q9 and Q13 to Q15, respectively. .

Switch MOS compatible with the above memory block MBQ
A selection signal formed by the decoder circuit DCRO is supplied to the gates of FETQ7 to Q9.

In addition, switch MOS compatible with memory block MBI
A selection signal formed by the decoder circuit DCR1 is supplied to the gates of FETQI3 to Q15.

In this configuration, the common predecoder circuit XP
Since the DCH forms a common selection signal for a plurality of memory blocks such as memory blocks MBO and M1, the circuit can be simplified. Furthermore, since the word lines can be arranged in accordance with the pitch between the gates of the series storage MOSFETQm, memory blocks and word line selection signal lines can be arranged with high density.

The data lines Do to Dn are connected to the column decoder YDC.
A switch MOSF receiving a selection signal formed by R
Connected to common data line CD via ETQI 9 to Q21. Although not particularly limited, if there are 512 data lines DO to Dn and 512 word lines WO to Wm, one memory block MBO has a storage capacity of about 256 bits. Therefore, when constructing a vertical ROM having a storage capacity of approximately 4 Mbits, a total of 16 memory blocks similar to those described above are provided.

The common data line CD is connected to the input terminal of the sense amplifier SA. Although not particularly limited, the sense amplifier SA may include a storage MO in the series form of the memory block.
Dummy array D consisting of a memory circuit similar to SFET
The sensing operation is performed with reference to the reference voltage V ref formed by C. That is, dummy array D
In C, all the storage MOSFETs Qm are constituted by enhancement type MOSFETs, and the power supply voltage Vcc is constantly supplied to the gate thereof, so that the memory MOSFET Qm is constantly turned on. Then, the composite conductance is the memory MOS F in the series form of the memory block.
It is set to approximately 1/2 of the composite conductance of ET.

The vertical ROM of this embodiment is configured as a static type circuit. That is, the sense amplifier SA has a read current source, and has a read current source, and is connected to the common data [CD and data lines as well as the selected serial storage MOS FET Q m
The read operation is performed by sensing whether or not current flows through the dummy array DC by referring to the current flowing through the dummy array DC.

In this embodiment, in order to prevent the potential of the word lines WO to Wm from decreasing due to the non-selected state of the memory block MBO, each word line WO to Wm is connected to the power supply voltage Vcc. MOSFETs QIO to Q12 for pull-up are provided between them. In order to turn on these MOSFETs QI O to Q12 when memory block MBO is in a non-selected state, in other words, to perform a pull-amplification operation when memory block MBO is in a non-selected state, the decoder circuit described above is used. An inverter circuit N1 is provided to receive the output signal of the DCRO. The output signal of this inverter circuit N1 is transmitted to the gates of the MOSFETs QIO to Q12.

Similarly, in other memory blocks MBI, word lines WO to W are placed in a non-selected state.
In order to prevent the potential of m from decreasing, pull-up MOSFETs Q13 to Q15 are provided between each word line WO to Wm and the power supply voltage Vcc. These MOSFETs Q13 to Q15 are switch-controlled by the output signal of the inverter circuit N2 that receives the output signal of the decoder circuit DCRI, so that when the memory block MBI is in a non-selected state, each word line WO to Wm is pulled up. I do.

The address selection operation of the vertical ROM in this embodiment will be explained next.

The predecoder XPDCR decodes a row (X) system address signal (not shown), sets its selection level to a low level, and sets its non-selection level to a high level. That is, when word lines wO to Wm are composed of 512 as described above, one word line selected from among the 512 word lines is set to low level, and the other 511 word lines are set to high level. . Further, the decoder circuit DCRO and the like form a selection signal for the corresponding memory block MBO and the like.

Therefore, for example, when the decoder circuit DCRO sets its output signal to a high selection level, the word line selection signal formed by the predecoder circuit XPOCR is applied to each word pWQ-Wm of the memory block MBO via the switch MOSFETs Q7 to Q9. Reportedly. Therefore, if the storage MOSFET Qm coupled to the selected word line in memory block MBO is of the depressing type, a current bus is formed in the series circuit, and if it is of the enhancement type, no current bus is formed. At this time, the output signal of the inverter circuit N1 becomes low level depending on the selection level of the decoder circuit DCRO, and the pull amplifier MOSFETs Q10 to Q12 are turned off.

Each series circuit of the memory block MBO outputs data *DO via switches MOSFETQI to Q3, which are turned on according to the selection level of the decoder circuit DCRO.
~Dn.

Column decoder YDCR, for example, connects data lines DO to D.
When n is composed of 512 data lines as described above, one data line is selected from among the 512 data lines and coupled to the common data line CD. This allows one memory MOS
The information stored in the FET is read out.

When the selected storage MOSFET Qm is the enhancement type MOSFET, the actual reading is performed when the word line level changes from a high level (non-selection level) such as the power supply voltage Vcc to a low level such as the ground potential of the circuit. It is started when the level reaches the threshold voltage vth or lower. At this time, it is necessary that the levels of the other word lines be at the non-select level.

In this embodiment, in the memory block MBI placed in the non-selected state at this time, the corresponding decoder circuit DC
Since the output signal of RI is at a low level, which is a non-selection level, the output signal of the inverter circuit N2 becomes a high level, and the MO5FETs Q16 to Q18 for pull amplifiers are turned on. As a result, the unselected memory block MB
In I, etc., all word lines WO to Wm are set to a high level, a non-selection level.

Therefore, even in the memory block MBO, when it is placed in a non-selected state, all the word lines WO to Wm have been set to the high non-selected level in the same way as above, so the predecoder circuit XPDCR is substantially In this case, the level of one selected word line is pulled from high level to low level. As mentioned above, switch MOSFET (one MOS from Q7 to Q9
When applying a signal voltage through a MOSFET (FET), a drive voltage (transfer voltage) such as the power supply voltage Vcc is applied between its gate and source, so the switch MOSFET must be turned on with a large conductance characteristic. Can be done. As a result, the word line can be brought down to the selection level, or in other words, the accumulated charge accumulated in the parasitic capacitance of the word line to be selected can be quickly extracted. This allows the selected storage MOS
This allows the actual reading start timing of FETQm to be earlier.

In this way, when a memory block is brought into a non-selected state, it is brought into a selected state by turning on the pull-up MOSFET and bringing all word lines WO to Wm to the high non-selected level. MO for memory of time
The actual read operation of SFETQm can be made faster.

Also, when a memory access is performed, in other words, when a read operation is performed, one of the 512 word lines is pulled from a high level to a low level (because it is a low level, it flows to the ground potential line of the circuit). The peak radio waves will be minute.

Therefore, noise generated in the ground potential line of the circuit can be suppressed to a minimum. This makes it possible to increase the operating margin of the sense amplifier SA that senses whether or not current flows through the series circuit.

The effects obtained from the above examples are as follows. That is, (1) In a configuration in which a word line selection signal formed by a common predecoder circuit is selectively transmitted to each word line of a plurality of memory blocks via a switch MOSFET, the word line in each memory block is set to a non-select level. By providing a pull-up means, each word line can be placed at an unselected level when the memory block is placed in an unselected state. As a result, when accessing the memory block, the storage MO5FET
The effect is that reading can be performed at high speed.

(2) According to (l) above, when a memory access is performed, one word line is pulled from high level to low level, so that the current flowing through the ground potential line of the circuit can be minimized. This makes it possible to minimize the noise generated in the ground line of the circuit, resulting in the effect that the operating margin of the sense amplifier can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the pull-up means may include a MOS FET that is turned on when the corresponding memory block is in a non-selected state, or a polysilicon layer that allows a small current to flow to compensate for leakage current in the word line. It may also consist of high resistance means. In this case, the size of the resistive element can be reduced by being able to form it integrally with the polysilicon layer, etc. that constitutes the word line, and the control signal line is not required, so the pull-up means can be used to reduce the packaging density of the word line. At the same time, it can be formed with high density. A pair of serial storage MOS FETs are provided corresponding to one data line in one memory block, and the data line is extended in the center, and the serial storage MOS FET is connected to either the left or right side of the data line. Alternatively, the MOSFET for use may be selected. Selection of such a serial configuration is performed by a decoder circuit that selects the memory block, and
It is sufficient to provide a decoder circuit that selectively selects the left and right series storage MOSFETs. In this configuration,
Storage MOS in series form coupled to one data line
Since the number of FETs can be doubled, a large storage capacity can be obtained with a small number of memory blocks.

In addition, the vertical ROM memory array and its peripheral circuits are
N-channel MOSFET and P-channel MOS F
It may be constructed from a CMOS circuit in combination with ET. In this case, if the switch MOSFET that transmits the predecode output to the word line of the memory block is an N-channel MOSFET, and the pull-up MOSFET is a P-channel MOSFET, the output of the decoder circuit can be shared by the gates of these MOSFETs. can be supplied to In other words, the inverter circuits Nl, N2, etc. shown in FIG. 1 can be omitted. The readout method of the series storage MOSFET is such that the precharged voltage is connected to the selected series MOSFET.
It may be performed using a ratioless type (dynamic type) logic system in which reading is performed depending on whether or not it is discharged via an ET circuit.

In the present invention, a switch MOS is connected to a word line to which the gates of storage MOSFETs arranged in series are respectively coupled.
It can be widely used in vertical ROMs that supply selection signals via FETs.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a configuration in which a word line selection signal formed by a common predecoder circuit is selectively transmitted to each word line of a plurality of memory blocks via a switch MOSFET, a pull-up is used to set the word line in each memory block to a non-select level. By providing means, each word line can be placed at an unselected level when the memory block is placed in an unselected state. As a result, when accessing the memory block, the storage MOS
FET reading can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a vertical ROM considered prior to the present invention. MBO, MBI...Memory block, XPDCR...Pre-decoder circuit, DCRO, DCRI...Decoder circuit, YDCR...Column decoder circuit, SA...Sense amplifier, and -\Representative Patent Attorney Katsuma Ogawa <' Ni, % . Figure 1 21S21

Claims (1)

[Claims] 1. A first decoder circuit that forms a plurality of selection signals corresponding to a plurality of word lines of a plurality of memory blocks, and a first decoder circuit that generates a selection signal formed by the first decoder circuit of the memory block. A switch M consisting of a plurality of switches that communicate to each word line
A pull-up means provided between the OSFET, a second decoder circuit that forms a selection signal to be supplied to the gate of the switch MOSFET, and a voltage terminal corresponding to a word line and a non-selection level of the word line in each memory block. A vertical ROM characterized by comprising: 2. The pull-up means receives the selection signal formed by the second decoder circuit and selects the first switch M.
The vertical ROM according to claim 1, wherein the vertical ROM is a switch MOSFET that operates complementary to an OSFET.