JPS63174452U - - Google Patents

Info

Publication number
JPS63174452U
JPS63174452U JP16721286U JP16721286U JPS63174452U JP S63174452 U JPS63174452 U JP S63174452U JP 16721286 U JP16721286 U JP 16721286U JP 16721286 U JP16721286 U JP 16721286U JP S63174452 U JPS63174452 U JP S63174452U
Authority
JP
Japan
Prior art keywords
hybrid
substrate
semiconductor device
cap
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16721286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16721286U priority Critical patent/JPS63174452U/ja
Publication of JPS63174452U publication Critical patent/JPS63174452U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案になる半導体装置の好適な一実
施例を示す分解斜視図、第2図はベースとハイブ
リツドICとの組立状態を示す外観斜視図、第3
図は本考案になる半導体装置の他の実施例を示す
要部の一部を構成するベースの外観斜視図、第4
図は従来の半導体装置の縦断側面図である。 10……半導体装置、12……ハイブリツドI
C、13,22……ベース(基板)、14……キ
ヤツプ、15,20……リードピン、17,23
……凹部。
FIG. 1 is an exploded perspective view showing a preferred embodiment of the semiconductor device according to the present invention, FIG. 2 is an external perspective view showing an assembled state of a base and a hybrid IC, and FIG.
FIG.
The figure is a vertical side view of a conventional semiconductor device. 10...Semiconductor device, 12...Hybrid I
C, 13, 22... Base (board), 14... Cap, 15, 20... Lead pin, 17, 23
...Concavity.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に配置したハイブリツドICをキヤツプ
にて封止したパツケージ型の半導体装置であつて
、前記ハイブリツドICと接続するための前記基
板に植設したリードピンの周辺部に凹部を形成し
たことを特徴とする半導体装置。
A package type semiconductor device in which a hybrid IC arranged on a substrate is sealed with a cap, characterized in that a recess is formed around a lead pin implanted in the substrate for connection with the hybrid IC. semiconductor devices.
JP16721286U 1986-10-30 1986-10-30 Pending JPS63174452U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16721286U JPS63174452U (en) 1986-10-30 1986-10-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16721286U JPS63174452U (en) 1986-10-30 1986-10-30

Publications (1)

Publication Number Publication Date
JPS63174452U true JPS63174452U (en) 1988-11-11

Family

ID=31098932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16721286U Pending JPS63174452U (en) 1986-10-30 1986-10-30

Country Status (1)

Country Link
JP (1) JPS63174452U (en)

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