JPS63172139U - - Google Patents
Info
- Publication number
- JPS63172139U JPS63172139U JP6564087U JP6564087U JPS63172139U JP S63172139 U JPS63172139 U JP S63172139U JP 6564087 U JP6564087 U JP 6564087U JP 6564087 U JP6564087 U JP 6564087U JP S63172139 U JPS63172139 U JP S63172139U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor
- semiconductor pellet
- sealed
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000008188 pellet Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図ａは本考案の一実施例の平面図、同図ｂ
は同図ａのＡ―Ａ断面図、第２図および第３図は
それぞれ第１図の半導体装置を絶縁型および非絶
縁型として使用する場合の断面図、第４図は本考
案の他の実施例の断面図、第５図および第６図は
それぞれ従来の絶縁型および非絶縁型半導体装置
の断面図である。 １……半導体ペレツト、２……リードフレーム
、３，８，９……封止樹脂、４……幅広溝、５…
…複数の溝、６……基板、７……放熱体。
は同図ａのＡ―Ａ断面図、第２図および第３図は
それぞれ第１図の半導体装置を絶縁型および非絶
縁型として使用する場合の断面図、第４図は本考
案の他の実施例の断面図、第５図および第６図は
それぞれ従来の絶縁型および非絶縁型半導体装置
の断面図である。 １……半導体ペレツト、２……リードフレーム
、３，８，９……封止樹脂、４……幅広溝、５…
…複数の溝、６……基板、７……放熱体。
Claims (1)
- リードフレームに半導体ペレツトを搭載し樹脂
封止した半導体装置において、前記リードフレー
ムの前記半導体ペレツト搭載部の裏面を覆う封止
樹脂が、前記リードフレームに達する部分まで溝
状に除去されていることを特徴とする半導体装置
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6564087U JPS63172139U (ja) | 1987-04-28 | 1987-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6564087U JPS63172139U (ja) | 1987-04-28 | 1987-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63172139U true JPS63172139U (ja) | 1988-11-09 |
Family
ID=30902902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6564087U Pending JPS63172139U (ja) | 1987-04-28 | 1987-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63172139U (ja) |
-
1987
- 1987-04-28 JP JP6564087U patent/JPS63172139U/ja active Pending