JPS63171500A - Memory device - Google Patents
Memory deviceInfo
- Publication number
- JPS63171500A JPS63171500A JP62002781A JP278187A JPS63171500A JP S63171500 A JPS63171500 A JP S63171500A JP 62002781 A JP62002781 A JP 62002781A JP 278187 A JP278187 A JP 278187A JP S63171500 A JPS63171500 A JP S63171500A
- Authority
- JP
- Japan
- Prior art keywords
- memory cells
- memory
- initialization
- signal
- address decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 210000004556 brain Anatomy 0.000 description 1
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、記憶装置に関し、特にランダムアクセスメモ
リ（ＲＡＭ）の記憶内容を高速に初期化を行うようにし
た記憶装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and particularly to a storage device in which the contents of a random access memory (RAM) are initialized at high speed.
従来、記憶装置の記憶内容を初期設定するには、書き込
み場所（アドレス）を変更しながら書き込み動作を繰り
返し行うことで、全ての内容を初期化した。Conventionally, to initialize the contents stored in a storage device, all the contents were initialized by repeatedly performing a write operation while changing the write location (address).
初期化の範囲が広い場合、その初期化には多大の時間音
必要とする。例えば、サイクルタイム３００ｎＳ、６４
Ｘ１ビツトの初期化にはＤＭＡバースト書き込みでも２
０ ｍ５ｅｃ、プロセッサを用いたプログラム転送では
数１０Ｏｎ＋Ｓｅｃから数秒を必要する。If the range of initialization is wide, initialization requires a large amount of time and sound. For example, cycle time 300nS, 64
Initializing the X1 bit requires 2 bits even with DMA burst writing.
0 m5ec, and program transfer using a processor requires several tens of On+Sec to several seconds.
この為、実時間処理に応用しようとすると、高価なバイ
ポーラメモリやバイポーラプロセッサを用いるか、必要
な量の数倍の容量のメモリを用意し、空き時間に初期化
するといった複雑な手段が必要である。Therefore, if you try to apply it to real-time processing, you will need to use expensive bipolar memory or bipolar processors, or you will need to prepare a memory several times the amount needed and initialize it during free time. be.
本発明の記憶装置は、記憶単位（メモリセル）と、その
選択回路（アドレスデコーダ）との間に初期化要求信号
とのゲートを入れることで、初期化の場合、全てのメモ
リセルが選択、書き込みが行なわれるようにしたもので
ある。In the memory device of the present invention, by inserting a gate with an initialization request signal between a memory unit (memory cell) and its selection circuit (address decoder), in the case of initialization, all memory cells are selected, This allows writing to be performed.
第１図は、本発明の小規模な実施例として、８×１ビツ
ト構成の回路図を示す。第２図は本発明の大規模な実施
例として８に×８ビット構成のブロックダイヤグラムを
示す。FIG. 1 shows a circuit diagram of an 8.times.1 bit configuration as a small-scale embodiment of the invention. FIG. 2 shows a block diagram of an 8×8 bit configuration as a large-scale embodiment of the invention.
第１図では、それぞれ１ビット分のメモリセル１１〜１
８と同数のＯＲゲート２１〜２８をアドレスデコーダ３
の後に入れ、初期化信号１０１がアクティブの時は、ア
ドレスＡ。、Ａ、、Ａ２に無関係に全てのメモリセル１
１〜１８が選択される。In FIG. 1, memory cells 11 to 1 for one bit each
8 and the same number of OR gates 21 to 28 as the address decoder 3.
and when the initialization signal 101 is active, the address A. , A, , all memory cells 1 regardless of A2
1 to 18 are selected.
一方、この時読み出し、書き込み切り換え信号１０２に
関係なくメモリセル１１〜１８は書き込み状態となり、
データ入力信号１０３の内容が全てのメモリセル１１〜
１８に書き込まれる。なお、１０４はデータ出力を、１
０５は出力制御信号を示す。On the other hand, at this time, the memory cells 11 to 18 are in the write state regardless of the read/write switching signal 102.
The contents of the data input signal 103 are all memory cells 11~
Written in 18. In addition, 104 is the data output, 1
05 indicates an output control signal.
本装置は、ＯＲゲートがメモリセルと同数必要であり、
集積度が低下してしまう。しかし、現在のＬＳＩは、ア
ドレスデコーダがＸ、Ｙの二次元構造となっており、そ
の場合の本発明の実施例が第２図に示すものである。こ
の場合はメモリセル６５．５６３ケに対し、追加となる
ＯＲゲートは６４＋１２８＝１９２個であり、集積度は
ほとんど低下しない。図において、３１．３２はデコー
ダ、４はメモリプレーン、ＡＱ〜Ａ１２はアドレス信号
である。This device requires the same number of OR gates as memory cells,
The degree of integration will decrease. However, in current LSIs, the address decoder has a two-dimensional structure of X and Y, and an embodiment of the present invention in this case is shown in FIG. In this case, the number of additional OR gates is 64+128=192 for 65.563 memory cells, and the degree of integration hardly decreases. In the figure, 31 and 32 are decoders, 4 is a memory plane, and AQ to A12 are address signals.
以上説明したように、本発明は、記憶装置のアドレスデ
コーダを変更することにより、１回の書き込み動作で全
てのメモリセルの初期化が完了するため、安価なＭＯＳ
メモリでも、バイポーラメモリ以上の速度で初期化でき
る効果がある。As explained above, the present invention enables initialization of all memory cells to be completed in a single write operation by changing the address decoder of the storage device.
Even memory has the effect of being able to be initialized faster than bipolar memory.
第１図は本発明の一実施例のブロック図、第２図は本発
明の他の実施例のブロック図である。
３・・・アドレスデコーダ、１１〜１８・・・メモリセ
ル、２１〜２８・・・ＯＲゲート、３１．３２・・・デ
コーダ、４・・・メモリブレーン、ＡＯ〜ＡＩ２・・・
アドレス信号、１０１・・・初期化信号、１０２・・・
読み出し書き込み切換え信号、１０３・・・データ入力
、１０４・・・データ出力、１０５・・・出力制御信号
。
Ａ４１ｈ Ａｓ ＡＩ Ａ＋ｅん、ん２第２図FIG. 1 is a block diagram of one embodiment of the invention, and FIG. 2 is a block diagram of another embodiment of the invention. 3... Address decoder, 11-18... Memory cell, 21-28... OR gate, 31.32... Decoder, 4... Memory brain, AO-AI2...
Address signal, 101... Initialization signal, 102...
Read/write switching signal, 103...Data input, 104...Data output, 105...Output control signal. A41h As AI A+e N, N2 Figure 2
Claims (1)
ようにしたことを特徴とする記憶装置。A storage device characterized in that a single write operation writes to multiple storage units at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002781A JPS63171500A (en) | 1987-01-09 | 1987-01-09 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002781A JPS63171500A (en) | 1987-01-09 | 1987-01-09 | Memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171500A true JPS63171500A (en) | 1988-07-15 |
Family
ID=11538879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62002781A Pending JPS63171500A (en) | 1987-01-09 | 1987-01-09 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171500A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222180A (en) * | 1990-01-25 | 1991-10-01 | Nec Corp | Large capacity semiconductor memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59152596A (en) * | 1983-02-18 | 1984-08-31 | Canon Inc | Storage circuit |
-
1987
- 1987-01-09 JP JP62002781A patent/JPS63171500A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59152596A (en) * | 1983-02-18 | 1984-08-31 | Canon Inc | Storage circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222180A (en) * | 1990-01-25 | 1991-10-01 | Nec Corp | Large capacity semiconductor memory device |
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