JPS63169043A - Method of forming wiring in semiconductor device - Google Patents
Method of forming wiring in semiconductor deviceInfo
- Publication number
- JPS63169043A JPS63169043A JP43787A JP43787A JPS63169043A JP S63169043 A JPS63169043 A JP S63169043A JP 43787 A JP43787 A JP 43787A JP 43787 A JP43787 A JP 43787A JP S63169043 A JPS63169043 A JP S63169043A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- wiring
- film
- contact hole
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 238000002844 melting Methods 0.000 claims abstract description 18
- 230000008018 melting Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000007257 malfunction Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000005381 potential energy Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000283973 Oryctolagus cuniculus Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＬＳＩなどにおける半導体素子の配線形成方法
に係り、詳しくはコンタクト孔への金属の埋込み方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming interconnections of semiconductor elements in LSIs and the like, and more particularly to a method for filling metal into contact holes.
サブミクロンのＬＳＩ配線ではコンタクト孔のアスペク
ト比（高さ／径）が１以上になる。比較的段差被覆性の
良いバイアススパッタやＣＶＤでＡＱを堆積しても、コ
ンタクト孔では側壁が互いに被着ＡΩ粒子の陰になり底
部におけるへΩ膜厚が極めて薄くなる。従って、コンタ
クト孔付近で断線やエレクトロマイグレーションにょる
導通不良が発生する。このため、金属を加熱溶融してコ
ンタクト孔全体に埋込む技術が提案されている。In submicron LSI wiring, the aspect ratio (height/diameter) of a contact hole is 1 or more. Even if AQ is deposited by bias sputtering or CVD, which has relatively good step coverage, the sidewalls of the contact hole are shaded by the adhering AΩ particles, and the thickness of the AQ film at the bottom becomes extremely thin. Therefore, conduction failure due to disconnection or electromigration occurs near the contact hole. For this reason, a technique has been proposed in which metal is heated and melted to fill the entire contact hole.
この種の技術として関連するものに特開昭６１−９３６
５０号がある。Related to this type of technology is Japanese Patent Application Laid-Open No. 61-936.
There is No. 50.
加熱溶融法の金属には一般にＡＱが用いられているが、
溶融するには６６０℃以上に加熱処理する必要がある。AQ is generally used for metals processed by heat melting, but
To melt it, it is necessary to heat it to 660°C or higher.
このため、溶融したＡＱと接する配線層の下地や、コン
タクト孔の側壁の５ｉＯｚにＡＱが拡散し、クラックが
入り膜質がもろくなる。他には、コンタクト孔の底面で
はＡＱがＳｉ中に拡散しＰｎ接合を突き抜ける。Therefore, AQ diffuses into the base of the wiring layer in contact with the melted AQ and the 5iOz sidewall of the contact hole, causing cracks and making the film brittle. In addition, at the bottom of the contact hole, AQ diffuses into the Si and penetrates the Pn junction.
このように上記従来技術は溶融金属とこれに接する絶縁
膜間に拡散を防ぐ配慮が必ずしもなされておらず、導通
歩留り及び信頼性の低下を引き起す大きな要因になって
いる。As described above, in the above-mentioned conventional technology, consideration is not necessarily taken to prevent diffusion between the molten metal and the insulating film in contact with the molten metal, which is a major factor causing a decrease in the conduction yield and reliability.
本発明の目的はこのような問題点を解決するためになさ
れたもので、コンタクト孔部で配線層が薄くなり断線や
エレクトロマイグレーションによる不良をなくし、かつ
溶融金属と接する絶縁膜との拡散や、反応を防いで信頼
性の優れた半導体装置の配線の形成方法を得ることにあ
る。The purpose of the present invention was to solve these problems, and the purpose of the present invention is to eliminate defects caused by disconnection and electromigration by thinning the wiring layer at the contact hole, and to prevent the diffusion of molten metal and the insulating film in contact with it. An object of the present invention is to obtain a method for forming interconnections of a semiconductor device that prevents reactions and has excellent reliability.
ｃ問題点を解決するための手段〕
本発明の半導体装置の配線の形成方法は絶縁膜を形成し
た基板の主表面上にコンタクトを開孔し。Means for Solving Problem c] In the method of forming wiring for a semiconductor device of the present invention, contacts are formed on the main surface of a substrate on which an insulating film is formed.
主な配線層となる第１の金属被膜を被着する０次に第１
の金属被膜上に第１の金属より溶融温度の低い第２の金
属被膜を前記コンタクト孔の領域及びその近傍のみに残
るように被着する。上記目的はこの第２の金属被膜を融
点以上の温度に加熱処理し、これにより前記コンタクト
孔の近傍の第２の金属被膜を前記コンタクト孔の領域内
に移動せしめて埋込むことにより達成される。The 0th-order first layer deposits the first metal film that will become the main wiring layer.
A second metal coating having a lower melting temperature than the first metal is deposited on the metal coating so that it remains only in the area of the contact hole and its vicinity. The above object is achieved by heat-treating the second metal coating to a temperature above its melting point, thereby moving the second metal coating near the contact hole into the area of the contact hole and embedding it. .
第１金属被膜は配線用の金属であり、比較的厚く形成さ
れる。コンタクトを開孔した基板上に第１の金ｌ−も被
膜を被着したコンタクト孔領域には金Ｊρ（被膜が完全
に埋込まれないために凹ができる。The first metal film is a metal for wiring, and is formed relatively thick. In the contact hole area where the first gold film is deposited on the substrate in which the contact hole is formed, a depression is formed because the gold film is not completely buried.
第２の金属被膜は配線用金属ではなく上記の凹部を埋め
るコンタクト孔の平坦化用金属である。コンタクト孔領
域及びその近傍の第２の金属被膜をその融点以上に加熱
し一時的に金属を固相から液相に変化せしめると位置の
エネルギーと表面張力によりコンタクト近傍の第２の金
属被膜はコンタクト孔領域の凹部内に移動し、コンタク
ト孔領域の配線の表面がほぼ平坦化され。第２の金属被
膜とＳｉｎｇなどの絶縁膜やコンタクト孔底面のＳＬと
の間には比較的厚い第１の金属被膜が中間層として介在
するため、両方が直接接することはない。The second metal film is not a metal for wiring but a metal for flattening the contact hole filling the above-mentioned recess. When the second metal film in and around the contact hole area is heated above its melting point to temporarily change the metal from a solid phase to a liquid phase, the second metal film near the contact becomes a contact due to potential energy and surface tension. It moves into the recess in the hole region, and the surface of the wiring in the contact hole region is almost flattened. Since the relatively thick first metal film is interposed as an intermediate layer between the second metal film and the insulating film such as Sing or the SL at the bottom of the contact hole, the two do not come into direct contact with each other.
従って、溶融した第２の金属被膜が５ｉＯｚやＳｉ中に
拡散したり、反応するのを阻止できるため、絶縁膜にク
ラックが入り膜質を低下させたり。Therefore, it is possible to prevent the molten second metal coating from diffusing into 5iOz or Si and from reacting, which may cause cracks in the insulating film and deteriorate the film quality.
Ｐｎ接合を突き抜ける問題を解決できる。This can solve the problem of penetrating the Pn junction.
本発明の一実施例を第１図により説明する。第１図（ａ
）において、１は半導体基板で、フィールド酸化膜２を
形成した後、コンタクト孔形成領域にリソグラフィによ
って所定のパターンを形成する。次に、ＲＩＥ等により
シリコン酸化膜２を半導体基板１に達するまでエツチン
グしてコンタクト孔３を形成する。次に、第１図（ｂ）
のように半導体基板１上にバイアススパッタなどでＡＱ
を全面に被着し、配線用の第１の金属被膜４を形成する
。この後、第１図（ｃ）に示すようにＡＱを被着した半
導体基板１上にレジストあるいはポリイミド（７）を塗
布し、コンタクト孔３の領域付近に所定のパターンを形
成する９このパターンの大きさは、コンタクト孔３に配
線用の第１の金属被膜４を形成した接にコンタクト孔に
できる凹部５を第２の金属被膜７で完全に埋込むに必要
な量を確保できる寸法である。従って、被着する第２の
金属被膜７の膜厚にもよるが、一般的にはコンタクト孔
領域の凹部より大きく形成する。次に、コンタクト孔３
領域にパターンニングしたレジスト６上にＡＱ−１２％
Ｓｉから成る溶融魚釣５８０℃の第２の金属被膜７を被
着する。An embodiment of the present invention will be explained with reference to FIG. Figure 1 (a
), 1 is a semiconductor substrate, and after a field oxide film 2 is formed, a predetermined pattern is formed in a contact hole formation region by lithography. Next, the silicon oxide film 2 is etched by RIE or the like until it reaches the semiconductor substrate 1 to form a contact hole 3. Next, Figure 1(b)
AQ is applied to the semiconductor substrate 1 by bias sputtering as shown in FIG.
is deposited on the entire surface to form a first metal film 4 for wiring. After this, as shown in FIG. 1(c), a resist or polyimide (7) is applied onto the semiconductor substrate 1 on which AQ has been deposited, and a predetermined pattern is formed near the area of the contact hole 3 (9) of this pattern. The size is such that it can secure the amount necessary to completely fill the recess 5 that will be formed into the contact hole by forming the first metal film 4 for wiring in the contact hole 3 with the second metal film 7. . Therefore, although it depends on the thickness of the second metal film 7 to be deposited, it is generally formed larger than the recess in the contact hole region. Next, contact hole 3
AQ-12% on the resist 6 patterned in the area
A second metal coating 7 made of Si at a temperature of molten 580° C. is applied.
第２の金属被膜７はＭ ｇ ｔ Ｓ ｎ ｔ Ｚ ｎな
どの金属や、Ｓｉ、Ｃｕ、Ｚｎを含むアルミニウムロウ
などの複合材や、高温で流動する導電性有機物でも良い
。次に、第１図（ｄ）のようにホトレジスト６のリフト
オフ法を°用いてコンタクト領域３及びその付近にのみ
に第２の金属被膜７が残る様にして、不要な領域部を除
去する。この後、半導体基板（１）を赤外あるいはレー
ザー等のラビットアニールで第２の低融点金属被膜７の
ＡＱ−１２％Ｓｉの融魚釣５８０℃まで加熱する。する
と、第１図（ｅ）のように低融点金属被膜７のＡＱ−１
２％Ｓｉは固相から液相状態に瞬時に変化し、溶融した
金属が表面張力や位置のエネルギーのためにコンタクト
領域３の近傍にあった低融点金属被膜７はコンタクト領
域の凹部５に流れ込み、くぼみが埋められ配線の表面が
平坦に近づく。このため、コンタクト部での断線やエレ
クトロマイグレーションによる不良がなくなる。The second metal film 7 may be a metal such as M g t S n t Z n, a composite material such as aluminum wax containing Si, Cu, or Zn, or a conductive organic material that flows at high temperatures. Next, as shown in FIG. 1(d), by using a lift-off method of the photoresist 6, unnecessary regions are removed so that the second metal film 7 remains only in and around the contact region 3. Thereafter, the semiconductor substrate (1) is heated to a melt temperature of 580° C. of AQ-12% Si of the second low melting point metal coating 7 by rabbit annealing using infrared or laser. Then, as shown in FIG. 1(e), the AQ-1 of the low melting point metal coating 7
2% Si instantly changes from a solid phase to a liquid phase, and due to the surface tension and potential energy of the molten metal, the low melting point metal coating 7 that was near the contact area 3 flows into the recess 5 in the contact area. , the depressions are filled and the wiring surface becomes nearly flat. Therefore, defects caused by disconnection or electromigration at the contact portion are eliminated.
また、第１図（ｂ）において、配線用の第１の金属被膜
４は被着後、リソグラフィによって第２図に示すように
パターンニングして配線４′を形成してから、その後、
前記したように第２の低融点金属７を溶融してコンタク
ト孔領域の凹部５に埋込んでも良い。Further, in FIG. 1(b), after the first metal film 4 for wiring is deposited, it is patterned by lithography as shown in FIG. 2 to form wiring 4', and then,
As described above, the second low melting point metal 7 may be melted and filled into the recess 5 in the contact hole region.
なお、上記実施例では一層目の配線のコンタクト孔の場
合について示したが１本発明の技術的範囲は多層配線に
おけるスルホール孔等の広義のコンタクト孔の場合にも
適用できるものである。In the above embodiments, the case of a contact hole in a first layer wiring is shown, but the technical scope of the present invention can also be applied to a contact hole in a broader sense such as a through hole in a multilayer wiring.
また、上記実施例では第１及び第２の金属被膜をＡＱ、
ＡＵ−１２％Ｓｉについて示したが、この金属材料に限
定されるものではなくあらゆる金属、その複合材及びそ
の複合層や、高温で流動性のある熱硬化性の導電性有機
物質の場合にもこの発明は同様な効果を得ることができ
る。In addition, in the above embodiment, the first and second metal coatings are AQ,
Although it is shown for AU-12%Si, it is not limited to this metal material, and can also be applied to all metals, composite materials and composite layers thereof, and thermosetting conductive organic substances that are fluid at high temperatures. This invention can achieve similar effects.
本発明の方法によれば配線用金属被膜を形成してできる
コンタクト孔の凹部に低融点金属被膜を溶融して埋込む
際に、配線用全屈が低融点金属と絶縁膜やＳｉ層との中
間層として作用し、互の反応を防ぐため、絶縁膜の膜質
の劣化による絶縁耐圧の低下や接合の突き抜けを防止す
る効果がある。According to the method of the present invention, when melting and embedding a low melting point metal film into the concave portion of a contact hole formed by forming a metal film for wiring, the total bending for the wiring is caused by the contact between the low melting point metal and the insulating film or Si layer. Since it acts as an intermediate layer and prevents mutual reactions, it has the effect of preventing a decrease in dielectric strength voltage and penetration of the bond due to deterioration of the film quality of the insulating film.
また、本発明の方法によれば配線用金属被膜の被着後の
コンタクト孔に残る凹部はいかなる断面形状をしていて
も配線の表面で平坦になるように完全に埋込むことがで
きる他、金属が溶融する界面は金属同志になるので濡れ
性が良く完全な埋込みができるのでコンタクト孔部で断
線やエレクトロマイグレーションによる不良がなくなり
、信頼性が向上される。Furthermore, according to the method of the present invention, the concave portion remaining in the contact hole after the metal coating for wiring is deposited can be completely filled in so that it becomes flat on the surface of the wiring, regardless of the cross-sectional shape. Since the interface where the metal melts becomes metal-to-metal, it has good wettability and complete embedding, eliminating defects due to disconnection or electromigration at the contact hole, improving reliability.
第１図は本発明の半導体装置の配線形成方法の一実施例
を工程順に示す縦断面図、第２図は本発明の半導体装置
の配線形成方法の他の実施例を示す平面図である。
■・・・半導体基板、２・・・ＳｉＯｚＭ縁膜、３・・
・コンタクト孔、４・・・第１の金属被膜、６・・・レ
ジスト、７・・・第２の金属被膜。FIG. 1 is a longitudinal cross-sectional view showing one embodiment of the method for forming interconnects in a semiconductor device according to the present invention in the order of steps, and FIG. 2 is a plan view showing another embodiment of the method for forming interconnects in a semiconductor device according to the present invention. ■...Semiconductor substrate, 2...SiOzM edge film, 3...
- Contact hole, 4... First metal coating, 6... Resist, 7... Second metal coating.
Claims (1)
にコンタクトを開口し、金属膜を被着して機能素子から
の引き出し配線を形成する半導体装置の製造方法におい
て、前記配線用の第１の金属被膜を被着し、第１の金属
被膜より融点の低い第２の金属被膜を被覆してコンタク
ト部とその近傍に残し、加熱処理して第２の低融点金属
被膜を前記コンタクト部に溶融して移動せしめて凹部を
埋め、パターンニングして表面が平坦化された配線を形
成することを特徴とする半導体装置の配線形成方法。1. A method for manufacturing a semiconductor device in which a contact is opened on a semiconductor substrate that constitutes a functional element and is covered with an insulating film, and a metal film is deposited to form a lead-out wiring from the functional element. A second metal coating having a melting point lower than that of the first metal coating is coated and left on the contact portion and its vicinity, and heat treatment is performed to form the second low melting point metal coating on the contact portion. 1. A method of forming wiring for a semiconductor device, comprising: melting and moving the wiring to fill a recess, and patterning the wiring to form a wiring whose surface is flattened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43787A JPS63169043A (en) | 1987-01-07 | 1987-01-07 | Method of forming wiring in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43787A JPS63169043A (en) | 1987-01-07 | 1987-01-07 | Method of forming wiring in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63169043A true JPS63169043A (en) | 1988-07-13 |
Family
ID=11473789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43787A Pending JPS63169043A (en) | 1987-01-07 | 1987-01-07 | Method of forming wiring in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63169043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204013A (en) * | 1995-01-06 | 1996-08-09 | Lg Semicon Co Ltd | Wiring formation of semiconductor device |
-
1987
- 1987-01-07 JP JP43787A patent/JPS63169043A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204013A (en) * | 1995-01-06 | 1996-08-09 | Lg Semicon Co Ltd | Wiring formation of semiconductor device |
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