JPS63168613A - Automatic focus detector - Google Patents

Abstract

PURPOSE:To obtain a sufficient color temperature detection output regardless of a low luminance to correct the focus detection error by operating color temperature detecting photodetectors as the integral type. CONSTITUTION:Color temperature detecting photodetectors 13 and 14 are operated as the integral type, and capacitors and switching transistors are provided between color temperature detecting photo diodes 13 and 14 and buffers 29 and 30, between a monitor photo diode MPD and a buffer 28, and in preceding stages of buffers 31 and 31'. Outputs of color temperature detecting photodetectors 13 and 14 are stored in a storage means like a capacitor for prescribed time. The output voltage based on all of the electric charge stored (integrated) for the prescribed time is outputted as a color temperature detection signal. Consequently, even if an object has a low luminance and the quantity of photoelectric charge per time generated from color temperature detecting photodetectors 13 and 14 is small, the color temperature detection signal is outputted as a relatively large value as the result of integration for the prescribed time. Thus, color temperature correction is sufficiently performed even for a lower luminance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic focus detection device used for autofocus in a camera.

Conventional technology As a conventional example of such an automatic focus detection device, for example, Japanese Patent Application Laid-open No. 5
Some of them are described in No. 8-59413 and JP-A-58-86504. The former method specifically extracts the photoelectric signal of visible light and the photoelectric signal of near-infrared light from the luminous flux from the subject, and focuses the light of the desired wavelength on the in-focus position detected by the light of all incident wavelengths. A correction value up to the focus position is determined based on the photoelectric signal specifically extracted.

Furthermore, even in the latter case, a detection error due to color temperature in a focus detection section that is sensitive to visible light and light other than visible light is corrected using the output of a separately provided color temperature measuring means. However, although these conventional examples disclose how to use the output obtained from a light receiving element such as a photodiode according to the purpose, they do not explain how to operate the light receiving element and obtain the output. nothing has been touched.

Problems to be Solved by the Invention Therefore, in the conventional example described above, the color temperature detection output is useless when the subject is dark and has low brightness, and the intended purpose cannot be achieved.

Therefore, an object of the present invention is to make it possible to obtain a sufficient color temperature detection output even at low luminance and to correct focus detection errors.

Means for Solving the Problems The second aspect of the present invention provides a photoelectric conversion type focus detection light receiving element that receives object light that has passed through a photographic lens.

and a focus detection means for detecting a focus state based on the output of the focus detection light receiving element.

A color temperature detection means comprising a plurality of photoelectric conversion type color temperature detection light receiving elements provided with filters having mutually different spectral characteristics in order to detect the color temperature of the subject light.

a correction means for correcting the output of the focus detection means based on the output of the color temperature detection means;

A control means for controlling the focus detection light receiving element to operate in an integral type that accumulates photocharges generated by light reception for a predetermined time and outputs the accumulated photocharges.

In the automatic focus detection device, the configuration is characterized in that the color temperature detection light-receiving element also operates in an integral type.

Further, a second aspect of the present invention is a similar configuration including a light-shielded dark-time compensation light-receiving element for canceling the dark-time charge output of the color temperature detection light-receiving element.

The output of the light-receiving element for detecting the working color temperature is stored in storage means such as a capacitor for a predetermined period of time, for example. Then, an output voltage based on the total charge accumulated (integrated) during the predetermined period is output as a color temperature detection signal. Therefore, even if the subject has low brightness and the amount of photoelectric charge generated per time from the color temperature detection light receiving element is small, the color temperature detection signal will have a relatively large value as a result of integration over the predetermined period. This will be output as follows. Therefore, sufficient color temperature correction can be performed even at low luminance. In addition, in the following embodiments, the predetermined period is determined based on the period from the start of integration to a preset value by a monitoring light receiving element (monitor photodiode) provided to monitor the integration state, or If the monitor output does not reach a predetermined value, it is determined based on a command from the system controller.

Further, the output of the light-shielded dark-time compensation light-receiving element in the second aspect of the invention differs from an undesired output component due to dark-time charge generated in the color temperature detection light-receiving element without being based on light irradiation. This helps eliminate that unwanted output component. In this case, the color temperature detection signal will be extremely accurate.

Embodiment As shown in FIG. 1, the focus detection optical system (OF) constituting the focus detection device of the camera is an infrared optical system provided behind the planned focal plane (F) behind the photographic lens (1). A light cut filter (lO), a condenser lens (2), a pair of re-imaging lenses (4a) (4b) with an aperture mask (3) located behind them, and these re-imaging lenses (
4a) A charge-coupled device (
A focus detection light receiving section (CCD) having a light receiving element (CCD) as a light receiving element.
It is composed of the main parts (6), (7), etc. of a photo sensor array for AP (autofocus) as a component of RF).

When a material such as silicon, which has a relatively flat spectral sensitivity within visible light (v), is used as the AF photosensor array, the long wavelength component ( For example, λ = 720 nm) (U
) moves to the rear of the intended focal plane (F) due to the axial chromatic aberration of the photographic lens (1). The distance (2u) is visible light (V) [center of gravity (λ""560n
m) is larger than the image interval (XV) (corresponding to the focal position detection signal) corresponding to an object containing a large number of reflected light components in ).

FIG. 2 shows the configuration of an AF sensor module (MF) that integrates the above-described focus detection device. This person F sensor module (MP) has a built-in optical path conversion mirror (8), and above this mirror (8) is the above-mentioned condenser lens (2), field mask (9), and a diameter of 750n+* or more. An infrared light cut filter (10) that cuts infrared light in the wavelength range is arranged.

Here, the infrared light cut filter (10) not only removes unnecessary infrared light to minimize the adverse effects of chromatic aberration, but also protects against long wavelength incident light, which is seen in semiconductor line sensors such as CCDs. This also prevents the reliability of the focusing signal from deteriorating due to an increase in the variation in photosensitivity of each pixel.

Each of these components is supported by a lens holder (II), and is arranged perpendicularly to the optical axis converted by the optical path conversion mirror (8), including an aperture mask (3) and a pair of re-imaging lenses. It has a basic structure in which a substrate (5) having (4a) and (4b) and a photoelectric conversion element (12) containing the aforementioned photosensor array are supported.

FIG. 3 shows the configuration of the photoelectric conversion element (12) of the AF sensor module (MF).

In the photoelectric conversion element (12), a focus detection light receiving part (R
F) for configuring the photo sensor array (in Fig. 3, the main parts (6) and (7) of the two photo sensor arrays shown in the principle diagram of Fig. 1 are shown as continuous). , a pair of color temperature detection water diodes (13)
(14) are lined up almost parallel to each other. Then, the two re-imaging lenses (4a) and (4b) are used to detect the photo sensor array and color temperature detection photodiode (13).
) (14) A subject image is formed above.

Figure 4 shows the spectra of the photodiodes (FD'') that make up the color temperature detection photodiodes (13) and (14), and the dye filter placed above them, with wavelength on the horizontal axis and relative spectral sensitivity on the vertical axis. This shows the sensitivity characteristics.

Here, (13= ) is the yellow pigment filter, (14'
) indicates the spectral sensitivity characteristics of the red dye filter. Therefore, the spectral sensitivity characteristics of the color temperature detection photodiodes (13) and (14) are (13゛) (1
4').

The color temperature detecting photodiodes view approximately the same subject using different re-imaging lenses.

The graph in FIG. 5 is drawn together with the spectral energy distribution of light from various light sources. The horizontal axis is wavelength, and the vertical axis is relative spectral sensitivity or energy.

The curves (A), (B), and (C) in the figure are, respectively,
Light from standard light source A such as tungsten lamp, sunlight 1
．． It shows the spectral energy distribution of light from a white fluorescent lamp. In addition, (13'), (14') and (PD
'') curve is in accordance with Fig. 4.

In addition, in the figure, the two-dot chain line (IR) at the 750 nm position is
The cut wavelength by the infrared light cut filter (10) described above is shown.

As will be described later, based on the output currents from the color temperature detection photodiodes (13) and (14), which are the pair of color temperature correction light receiving sections, specifically, based on the ratio, the focus detection It detects the spectral energy distribution of the measurement light.

That is, as can be seen from the graph, the difference in output from both photodiodes (13) and (14) is significant.
Since the area is about 600 na+ or more, if the area of both is designed to be 1:1, the output from both photodiodes (13) and (14) will be almost the same for the light from the white fluorescent lamp, and the ratio is approximately It is 1.0. Also, standard light source A
Under the light of , the ratio of the outputs from both photodiodes (13) and (14) is large, and is approximately 2.0, since the light energy becomes significant when the light energy exceeds 60 Ons. Furthermore, the distribution of light energy in the infrared light region of sunlight is approximately between the light from a white fluorescent lamp and the light from standard light source A, and the output from both photodiodes (13) (14) The ratio is approximately 1.5.

Further, a first color temperature detection photodiode (13),
A second color temperature detection photodiode (14) is provided on the same chip adjacent to a reference part and a reference part of a photodiode array section, which will be described later, and is viewing approximately the same subject as the reference part and reference part. .

Next, the structure of the photoelectric conversion element will be explained using FIGS. 6 to 13. First, as shown in FIG. 6, the photoelectric conversion element (12) includes a photoelectric conversion section (15) having a photodiode, a shift register, etc. that generates a photocharge according to the amount of irradiated light, and a photoelectric conversion section (15) that has a photoelectric conversion element (15) that generates photocharges according to the amount of light irradiated. A data output control unit (16) that controls charge transfer to the register side, control of charge transfer in the shift register, and signal processing timing of the analog processing unit (described later), integration time of the photoelectric conversion unit (15), etc. an analog processing section (18) that processes analog signals from the photoelectric conversion section (15), and a temperature detection section that supplies temperature information to a system controller (described later) due to temperature changes. section (19), and I10 control section (2
0). And this photoelectric conversion element (
12) is formed as a one-chip IC with each of the above-mentioned components provided on one substrate.

The photoelectric conversion section (15) includes the aforementioned pair of color temperature detection photodiodes (13) (14), a photodiode array section (21), a barrier gate (22), an accumulation section (23) for temporarily accumulating charges, and an accumulation section. Department clear gate (24),
It is composed of each main element of a shift gate (25) and a shift register (26), and each of their output buffers, that is, an output buffer (
27), an output buffer (28) for a monitor photodiode (MPD) inserted into the photodiode array as described later, and a color temperature detection photodiode (28).
13) (14) output buffer (29) (30)
, a monitor output compensation signal output buffer (31) for dark-time correction of the monitor photodiode (MPD) output, and a color temperature detection signal (OSY) (O5R).
It is equipped with a standard voltage buffer (31').

Furthermore, photodiodes for color temperature detection (13) (14)
and the buffer (29) (30), and between the monitor photodiode (MPD) and the buffer (28),
Furthermore, capacitors and switching transistors are provided in the preceding stages of the buffers (31) and (31'), respectively, and the details of these capacitors and transistors will be explained in detail with respect to the specific circuit configuration of the photoelectric conversion section (15) shown in FIG. I will add this in the explanation. Data output control section (
16) is composed of a signal processing timing generation section and a transfer lock generation section, and generates a transfer lock (φ+
) (φ2), it also generates a shift gate pulse (SH) to the shift gate (25). It also provides the analog processing section (18) with a signal useful for creating a timing signal for switching the sampling signal and the signal output from the photoelectric conversion element (12) to the outside.

The integration time control section (17) monitors the signal (AGCOS) given from the monitoring photodiode (MPD) of the photoelectric conversion section (15) through the buffer (28), and controls the output of the pass gate 1-(22) according to the monitoring result. , storage section (23), and storage section clear game) (24), respectively (BG) (ST) (STICG)
is output as appropriate to control the integration time. During the monitoring, the integral time control section (17) controls the monitor signal (AG
COS) is compensated for in the dark using a monitor output compensation signal (AGCDO5) given from a buffer (31). The integral time control section (17) is the Mari I10 control section (20).
Signals are exchanged with the system controller via the system controller, and one of the signals given to the system controller is an integration completion signal (TINT). Furthermore,
This integral time control unit (17) is configured to forcibly control the integral value by a command signal (SHM) from the system controller when the integral value at the photoelectric conversion unit (15) does not reach a predetermined integral value within a predetermined time. The integration is completed, but in order to correct the insufficient integration output accompanying this at the analog processing stage, an automatic gain control signal (AGC) corresponding to the integrated value is generated and sent to the analog processing section (18). I also do things. The basic functions of the analog processing section (18) are the signal (O5) from the shift register (26) and the output signal (O5) from the color temperature detection photodiodes (13) and (14).
3Y) Performs various analog processing such as removing noise components from (OSR), dark output signal compensation, and automatic gain control. As will be described in detail later, this analog processing section (18) is also provided with a configuration for performing reference voltage clamping in order to match the output signal with the dynamic range of the A/D conversion section of the system controller.

110 control section (20) includes a signal processing timing generation section (16B) and an integral time control circuit (16B) shown in FIG.
17b) refers to the human output buffers distributed in the transfer lock generation unit (16A). In Figure 6 I
10 The external device connected to the control section (20) is connected to the terminal (T
, ) ~ (T, ) and (T'l + ) (T I □), (TI) (Tz) is the integral start mode, low brightness integral mode, high brightness integral mode, and gives an integral output to the system controller. An input terminal that receives a mode signal (MD I) (qoz) that selectively specifies the data dump mode, (T,) is an integral clear signal < IC3 related to the start of integration.
) input terminal, (T4) is a data request terminal for forcibly ending integration and requesting data from the shift register (26), (T, ) is an external (system controller) input terminal when in data dump mode. to A/D conversion start signal (
(T,) is the terminal that outputs the basic clock (C
This is the input terminal of P). Furthermore, (T,) is a terminal that outputs an integration completion signal (TINT), and (TIz) is a terminal group that outputs data for automatic gain control (AGC). In addition, the terminals (T?) (is) shown at positions apart from the I10 control section (20) are respectively connected to the power supply (Vc
c) input terminal and ground terminal. (T,) is an analog signal output terminal, (TI.) is a reference voltage (Vre
f) is an input terminal.

Next, the specific configuration of each part of the photoelectric conversion element (12) will be described in detail. First, the entire photoelectric conversion section (15) is configured as shown in FIG. 7, and the portion including main elements such as photodiodes and shift registers will be explained using FIGS. 8 to 13. . As shown in FIG. 8, the photodiode array section (21) has a plurality of pixel photodiodes (PD) and monitor photodiodes (MPD) arranged therebetween alternately. One longitudinal end of each pixel photodiode is open, while the other end is coupled to the source of a first MO8 transistor (TRI) forming a barrier gate (22).

The drain of this MD3) transistor (TR,) is coupled to the next stage storage section (23), and the gate is coupled to the barrier gate signal supply terminal (32). Although the storage section (23) is shielded from light by an aluminum film and is not irradiated with light, so-called dark charges are generated. The output end of the storage section (23) is connected to the second MD3 forming the storage section clear gate (24).
The source of the transistor (TRz) and the shift gate (
25) the third MOS transistor (TR3) forming
The drain of the second M05) transistor (TR1) is coupled to the power supply terminal (T7) to which the power supply (Vcc) is applied, and the gate is connected to the storage section clear gate signal supply terminal (33). ing. On the other hand, the third? The drain of the 10S) transistor (TR3) is coupled to the segment (26a) constituting the shift register (26), and the gate is coupled to the shift gate signal supply terminal (34).

The monitor photodiodes (?IPD) are connected to each other by photodiodes at the upper end of the figure, and therefore the monitor output is the total output of the plurality of connected monitor photodiodes (MPD).

By combining a plurality of monitoring photodiodes in this way, a subject brightness monitoring photodiode device having a wide field of view can be realized.

The physical structure of the photodiode array section (21) is schematically illustrated in FIG. 9, which shows a cross section taken along line A-A' in FIG.
A channel made of P is applied to the upper n-type region (37) to separate the mold head region (36), the implanted n-type region (37), and the pixel photodiode (PD) and monitor photodiode (MPD). It consists of a stopper (38) and a P0 film (39) provided on the surface to suppress the dark output of each photodiode and suppress the surface depletion layer. A positive potential is applied to the substrate (35) from the outside, and a ground potential is applied to the intermediate P-type head area (36). Note that the n-type region (37) is formed by phosphorus implantation, and the p-type head region (36) is formed by boron diffusion.

By the way, the charge accumulated in the pixel photodiode (PD) mentioned above is transferred to the accumulation section (22) through the barrier gate (22).
3) The time required to transfer the data to the pixel photodiode (
PD) long I! , ) is known to be approximately proportional to the square of . On the other hand, as a focus detection device, the total area of each pixel photodiode (PD) is increased by increasing the length 2) so that it can operate even for subjects with considerably low brightness, and the amount of generated charge is increased. However, increasing the width of the pixel photodiode (PD) is not preferable because it deteriorates the accuracy of the focus detection device. In order to satisfy these contradictory demands, the present inventors proposed the above-mentioned P
``We considered changing the depth of the n-type region (37) just below the film (39) along the longitudinal direction. That is, Fig. 10 (a
) is cross-sectionally taken in the direction shown by the dotted line (40) in the same figure (c), which shows the structure of its main part (portion near the surface). Regarding the mold region creation, the n-jI region (37a
) and form an n 9M region (37b). If you do this,
As shown in FIG. 2B, the potential of the pixel photodiode (PD) gradually decreases toward the barrier gate (22), and the charge tends to move to the left (towards the barrier gate). This means that the time required to transfer the charge accumulated in the pixel photodiode (PD) is reduced. Therefore, the pixel photodiode (PD)
By increasing the longitudinal length (j2) of the photodiode, it is possible to increase the amount of charge generated by the photodiode and to quickly transport the generated charge toward the storage section. Furthermore, the first
In figure 0, (41) (42) (43) (44
) are the barrier gate (22) and the storage section (23), respectively.
, shift gate h (25), and shift register (26), and aluminum material is usually used to form these electrodes. (45) is an insulating film formed in 5 in 1 or the like.

Next, the structure of the entire photoelectric conversion section will be explained with reference to FIG.

The pixel photodiode (PD), monitor photodiode (MPD), and barrier gate (22
), storage section (23), storage section clear game) (24),
(25) A large number of cascaded combinations of shift registers (26) are arranged in the horizontal direction, and for example, there are 128 shift registers (26) in terms of the number of segments. However, as seen at the right end of the array, the pixel photodiode (PD), monitor photodiode (M
PD), barrier gate (22), storage section (23), storage section clear gate 1- (24), and shift gate (25)
The number of segments is the shift register (26
) is 5 fewer than . Conversely, shift register (
Only the number of segments 26) is 5 more formed on the right end side, and this is due to the following reason.

A capacitor (C) receives the output of the shift register (26).
I) is formed integrally with the shift register (26), and specifically, as shown in the conventional example of FIG. Head area (
47) is formed by the junction capacitance generated between However, a distribution volume 1t (C') also occurs between the light-shielding aluminum film (49) coated on the surface via the insulating film (48) and the n'' region (46).This undesired distribution As shown in FIG. 11(c), the capacitor (C') is connected in parallel to the original capacitor (CI) formed of a junction capacitor, increasing the output capacitance and, as a result, decreasing the photosensitivity. Furthermore, the distributed capacitance (C') generated between the light-shielding aluminum film (49) and the n'' region (46) varies widely, which is undesirable because it causes variation in photosensitivity from product to product. Therefore, as shown in FIG. 11(b), the portion of the aluminum film (49) located in the output stage portion is removed (50). In this way, the distributed capacitance (C') is almost eliminated 1, and the output capacitor (
C2) is hardly affected, and the photosensitivity increases. On the other hand, the removed portion is shielded from light by a visual field mask (9) shown in FIG. That is, the junction capacitance portion as the capacitor (C4) is covered with a field mask (9).
Place it away from the window. This is because the capacitor (
The configuration is not limited to C1), and the aluminum film on the top of the capacitors (C2) to (C5) provided in each output stage is also removed.

Figure 12 shows this configuration as a schematic shape of the photoelectric conversion section (15) seen from the field mask side, and (51) is connected to the photodiode array (21) and color temperature detection photodiodes (13) and (14). (52)
reveals the projection of the window of the field mask (9). The condensers (C3) to (C8) are arranged at a position away from the projected image of the window, and therefore at a position not exposed to light. Here, the opening areas of the capacitors (CI) to (C8) are set equal to each other. With this configuration, the output voltages of the capacitors (C1) to (C8) can be made equal for the same output from the light receiving elements of the same size. Of these capacitors (CI) to (C6), only capacitor (C8) is located further away from the shift register segment corresponding to the light receiving part, so a second segment is required to connect them. The segments are the first to fifth segments shown in FIG. Therefore, these five segments merely function as photo-charge transfer paths. Since the capacitors (C2) to (C6) directly input the output of the light receiving section, they do not require the above-mentioned extra segments. The output of the shift register (26) is transferred and locked (φ, ) (φ2) when the transistor (Ql) is turned on instantaneously by the reset signal (O3RST).
is applied to the capacitor (C8) by the buffer (
27).

In FIG. 7, among the pixel photodiodes (PD) and the monitor photodiodes (MPD), five on the right end and three on the left end are shielded from light by an aluminum film. These light-shielded photodiodes generate a dark charge that is used, for example, for dark correction of the output of the pixel photodiode. A part of the photodiode array (21) is assigned as a reference part (M.) and another part as a reference part (M,).

For example, the reference portion (M) includes 40 pixel photodiodes and the reference portion (MI) includes 50 combinations of pixel photodiodes and monitor photodiodes. However, structurally speaking, the standard part (M
. ) and the reference part (shadow), but they are distinguished by software processing in the system controller, which will be described later.

Regarding the unnecessary parts between the standard part (M) and the reference part (Ml), only the shift register (26) is left, and other pixel photodiodes, monitor photodiodes, barrier gates, storage parts, and storage parts are added. The clear gate and shift gate have been deleted from the drawing. This deleted part (
Shown as S). Each segment (26a) of the shift register corresponding to the deleted portion (S) has a pitch that is smaller than that of other portions in order to reduce the number of transfer locks required to transfer all pixel outputs and shorten the total charge transfer time. It is formed to grow larger.

The monitor photodiode (?IPD) is in the reference section (M.

) and the reference part (PI+) are connected to each other so that only those located in the reference part (PI+) are used, and those located in other parts are not used. However, it is desirable to stabilize the unused monitor photodiode (MPD) by connecting it to the power supply terminal (T7) as shown in FIG. This is because if it is electrically floating, it will receive induction from other pixel photodiodes or cause induction to other pixels, eventually affecting other pixel photodiodes.

The output of the monitor photodiode is a capacitor (C2)
buffer (28)
The signal is output as a monitor signal (AGCO3) via the . In order to remove power supply fluctuations and temperature-dependent components of this monitor signal (AGCO5), a transistor (O
At the same time, the output (AGCDO3) from the capacitor (C3) initialized by 3) is prepared. A photodiode (D,) shielded from light by an aluminum film and having approximately the same size as the monitor photodiode (MPD) is connected to this capacitor (C3) as shown in the figure. Transistor (Qz) (Q, ) is integrated clear gate signal (IC
G) is turned on simultaneously during the application period.

Next, a pair of color temperature detection photodiodes (13) (1
4) are respectively arranged in the standard part (10) and the reference part (Ml) as shown in the figure, and these two photodiodes (
13) The output of (14) is the integral clear gate signal (IC
A capacitor (C4) (cs) is initially set by a transistor (Qri) that is turned on by G), and a transistor (cs) is turned on by a color temperature detection gate signal (PDS).
O4) (QS), the yellow temperature detection signal (
O3Y) is output as a red temperature detection signal (OSR). These color temperature detection photodiodes (13)
A color filter (not shown) is provided on the surface of (14). Here, the output buffer following the shift register (26), the output buffer for the red temperature detection signal, and the output buffer for the yellow temperature detection signal are formed in the same manner, and a pixel photodiode (PD) and a color temperature detection photodiode (13) are formed. (14), the output voltages of the yellow temperature detection signal (O5Y) and the red temperature detection signal (OSR) can be set to be the same as that of the reference part (M.) and the reference part (Ml). The output is the product of the average output of the pixel photodiode and the transmittance of the color filter. Therefore, this red temperature detection signal (OSR) and yellow temperature detection signal No. 3 (O
5Y) has a dynamic that is approximately equal to the output voltage of the pixel photodiode (PD), and can be used as a processing circuit for the pixel signal (O3) by processing it in a time-sharing manner in the analog processing section at the subsequent stage. Furthermore, since the size of the color temperature detection photodiodes (13) and (14) is the same as the size of the light-shielded pixel photodiode (OPD), the difference between the output voltage of the light-shielded pixel photodiode (OPD) must be taken. It is also possible to compensate for dark output. In addition, Fig. 7 shows the color temperature detection signal (O5Y).
Output (P
A capacitor (C8) for generating DDO3) and a switching transistor (Q, ) are also provided.

In Fig. 7, color temperature detection photodiodes (13) (1
4) The output signal (osY) (OsR) is connected to a separate transistor (QJ (Qs), capacitor (Cd) (C5)
, buffers (29), (30), etc., but it is also possible to take out using the output system of the pixel output (O3) without installing a separate output system like this. .

FIG. 13 shows an embodiment based on this viewpoint, in which any one of the three light-shielding pixel photodiodes (OPDs) arranged on the left side of FIG.
), and the output signal of the red temperature detection photodiode (14) is sent to the shift register (26) using the barrier gate, storage section, and shift gate sequentially coupled thereto. This output signal is transferred from the shift register (26) to the capacitor (Ct
) and further output via a buffer (27). FIG. 13 shows the red temperature detection photodiode (14) corresponding to the reference part (M,) as described above, and shows one end of the second light-shielded pixel photodiode (OPD) from the left end that is shielded from light by an aluminum film. The reference part (?IO
) The output end of the yellow temperature detection photodiode (13) corresponding to the yellow temperature detection photodiode (13) is similarly formed long and connected to any one of the five light-shielding pixel photodiodes (OPD) on the right side in FIG.

Next, FIG. 14 shows the photoelectric conversion section (15) as one block, and also shows other parts of the photoelectric conversion element (12) in detail, and also shows the system controller (
53) and its peripheral circuits.

The system controller (53) is formed by a one-chip microcomputer, and includes the photoelectric conversion element (1).
An A/D converter (54) that converts the analog signal (Vout) from 2) into a digital signal, and a lens data output unit (61) that includes a ROM for the photographing lens (interchangeable lens).
, data such as defocus amount, lens extension amount conversion coefficient (KL), color temperature defocus amount (dpt), etc., which are different for each lens, are input in advance, and digital data from the A/D converter (54) is input. Store them one by one,
A memory section (55) formed of a RAM, and a focus detection section (55) that detects a focus based on the output of the memory section (55).
56), a correction calculation unit (57) that calculates a correction amount from the detected focus data and lens data, etc., and sends a signal for driving the lens to a lens drive circuit (63) based on the correction amount. In addition, to monitor whether the integral value at the lens drive control section (58) that receives data on the movement status of the lens from the motor encoder section (64) and the photoelectric conversion section (15) reaches a predetermined value in a predetermined time. A timer circuit (59) for measuring time and a photoelectric conversion element (1
2) and the sensor control section (6) that sends and receives signals.
0). In addition, (65) is a lens drive motor,
(62) is a display circuit controlled by the system controller (53). The photoelectric conversion element (12) and the system controller (53) are formed separately with one chip each, so that the image sensing system is composed of two chips in total.

The integral time control section (17) in FIG. 6 includes a brightness determination circuit and an integral time control circuit, and in FIG. 14, this brightness control circuit (17a) and the integral time control circuit (1
7b) is shown separately. Further, the signal processing timing generation section (16B) shown in FIG. 14 is included in the data output control section (16) shown in FIG.

The I10 control section (20) in FIG. 6 is distributed into the signal processing timing generation section (16B), the integral time control circuit (17b), and the transfer lock generation section (16A) in FIG. 14. The system controller (53) first gives a basic tarok (CP) to the photoelectric conversion element (12). This basic clock (CP) is used by the transfer lock generation unit (1
6A) and an integral time control circuit (17b), respectively. The system controller (53) also sends a mode signal (MD+) (MDz
)give. The mode signal consists of 2 bits,
Four modes can be expressed: initialization mode, low-luminance integration mode, high-luminance integration mode, and data dump mode of the photoelectric conversion element (12), and are transmitted using two lines.

In the initialization mode, the transfer lock generation section (1
6A) to the photoelectric conversion unit (15) is a transfer lock (φ,
) (φ2) is supplied at a high frequency, and the charge that was unnecessarily accumulated in the shift register (26) before the transfer lock is supplied is discharged to the capacitor (C1) on the output side of the shift register (26). The charge discharged to the capacitor (C1) is transferred to the reset signal (O5R) by the transistor (Q,) in Figure 7.
When turned on by ST), it is discharged to the power supply (Vcc). In addition, in the initialization mode, the analog processing section (18)
is also initialized.

Next, the system controller (53) first instructs the low brightness integration mode and supplies an integration clear signal (ICS) shown in FIG. 16 to the integration time control circuit (17b). By inputting this integral clear signal (IC3), the integral time control circuit (17b) controls the integral clear signal (ICS3).
), the integral clear gate signal (ICG), the barrier gate signal (BG), and the storage section clear gate signal (ST
ICG) is generated and applied to a predetermined portion of the photoelectric conversion unit (15) shown in FIG. Integral clear gate signal (
ICG) is a monitor output signal (AGCO3), a monitor output compensation signal (8GCDOS), a color temperature detection output signal (
OSR) (O5Y), color temperature detection compensation signal (PDDO
S) are respectively initialized, while the barrier gate signal (B
G) and the storage section clear gate signal (STICG) initialize the pixel photodiode (PD) and the storage section (23).

When the integral clear signal (IC3) disappears, the integral clear gate signal (ICG), barrier gate signal (BG),
The storage section clear gate signal (STICG) also disappears. As a result, the transistor (qz) (C3) turns off, and the capacitor (C2), which was initially charged to the power supply voltage (Vcc), begins to drop in voltage in proportion to the charge generated by the monitor photodiode (MPD). , capacitor (C
3) drops the voltage slightly in response to a small amount of charge generated by the light-shielded photodiode (Dl). Also, (PDS)
is given to the transistor (C4) (as), and the capacitor (C4) (cs) also changes from the initial power supply voltage (Vcc) to the color temperature detection photodiode (
13) The voltage is lowered according to the amount of charge generated in (14), while the barrier gate (22) and the storage unit clear gate (24) are turned off, and as a result, the pixel photodiode (PD) is exposed to the irradiated light. In response, photoelectric charge generation and accumulation are started, and the light shielding photodiode (MPD) starts accumulating minute dark output charges. Furthermore, the storage section (23
), the dark output charge generated by itself is accumulated.

As can be seen from FIG. 16(a), for the integral clear signal (IC3), the aforementioned (BG) (STICG)
(ICG) have the same pulse width. Therefore,(
The pulse width of IC5) is such that all the charges previously accumulated (i.e. before initialization) in the pixel photodiode (PD) are parsed (22), the storage section (23),
and the storage clear game) (24) to the power supply (Vc
c) is limited by the time required to discharge it. Specifically, the pulse width is selected to be 50 μs to 100 μs or more.

The integration operation of the photoelectric conversion unit (15) does not need to be performed forever; rather, it must be completed at some point, because once the integral value reaches a predetermined level, there is no need to continue integrating. Also, if it takes a long time for the integral value to reach a predetermined level, the time from pressing the shutter button to being able to release the camera will be significantly longer. This is because it is better to correct this at the signal processing stage.

The brightness determination circuit (17a) determines the integration state from the monitor output signal (AGCOS) of the monitor photodiode (MPD) and the monitor output correction signal (AGCDOS), and when it reaches a predetermined value, It generates an instruction signal (VyLa) and supplies it to the integration time control circuit (17b), and also outputs a gain control signal (AGC) corresponding to the shortfall in the integral value. Its gain control signal (
AGC) is supplied to an AGC subtraction circuit (71).

The AGC subtraction circuit (71) receives the input pixel output signal (O
3) and the gain of the color temperature detection output signal (O5R) (OSY). The AGC subtraction circuit (71) also has a function of performing dark output compensation of the pixel output signal (O3), as will be described later. The GC data is sent to the system controller (
53). This is to enable the system controller (53) to determine whether or not it is necessary to emit auxiliary light (not shown) based on the GC data. The brightness determination circuit (
The specific structure of 17a) is shown in FIG. In FIG. 15, the block indicated by the dotted line (17a) is the brightness determination circuit, and the other dotted line blocks are the AGC subtraction circuit (71).
It is. The brightness determination circuit (17a) converts the monitor output compensation signal (AGCDOS) into a resistance value of 1x, 2x, 4x,
Operational amplifier (A I ) (＾2) (83) (A
, ) is applied to the positive input (+). At this time, a constant current (1) flows through each resistor due to the constant current source (B), so the voltage drop due to the resistor is 1 times, 2 times, and 2 times, respectively.
The relationship is 4x and 8x. Operational amplifier (A,) ~ (8,
) is connected to the negative input terminal (=) of the monitor output signal (A
GCOS) is supplied, and the outputs are (AGCOS) and (A
However, as shown in Figure 7, there are capacitors (C2) and (C1), transistors (h) and (C3), buffers (28) and (3) on the same chip.
1) are designed identically, so both signals (
AGCOS) and (AGCDOS) are at the same potential immediately after the integral clear gate signal (ICG) is applied, and the monitor output signal (AGCOS) is the monitor photodiode (M
PD), the monitor output compensation signal (AGCDOS) remains unchanged and always maintains the initial potential of the monitor output signal. Therefore, by taking the difference between these signals, it is possible to monitor the amount of accumulated charge (integral value). Moreover, by taking the difference between the two signals, fluctuations in the power supply voltage can be canceled.Furthermore, if the dark output increases due to temperature rise, the light-shielding photodiode (D+) will respond to it, so the monitor output compensation signal (AGCDO3 ) includes the temperature fluctuation of the dark output, and the difference voltage between the two signals is the integral value at the 0 pixel photodiode (PD), which becomes the correct monitor information signal with temperature effects removed. is considered to have reached a predetermined value, the monitor output signal (A
GCOS) is I×8R1il lower than the initial potential, so the operational amplifier (A4) generates the instruction signal (VFI!), and the control signal (V FLG ) is supplied to the integration time control circuit (17b). Integral time control circuit (1
7b), upon receiving either the instruction signal (VFLG) or the forced integration completion signal (SHM), the photoelectric conversion unit (15
), a latch signal (LCK) is generated, and this launch signal (LCK) is sent to the D flip-flop (FF+) of the luminance determination circuit (17a).
) to (FFs) clock terminal <cp>, D
Flip-flops (FF+) to (FF, ) are connected to data terminals (
D) is connected, the monitor output signal (AGC
It becomes a latch state depending on the value of OS).

Each D flip-flop (FF, ) (FF O) (FF3)
The output terminal of is connected to the AND gate (Nl) (NZ) as shown in the figure, and as a result, the brightness determination circuit (17a)
1 in the output paths (72), (73), (74), and (75).
Gain control signals (AGC) corresponding to correction amounts of times, times, times, four times, and eight times are output. Incidentally, in a situation where the instruction signal (VFLG) is output within a predetermined time managed by the system controller (53), (AGC) is generated on the output path (72).

However, within the predetermined time, the instruction signal (VFLG
) does not occur, the integration is forcibly completed as described later, so the output path (72) (73
) (74) An AGC signal of either one of (75) will be generated.

An explanation of the low luminance integration mode will be added using the time chart of FIG. 16(a). The integration operation starts in the photoelectric conversion unit (15) from the time when the integration clear signal (IC3) disappears, and after a while, when the monitor output signal (AGCOS) drops to a level corresponding to a predetermined integral value, the instruction signal (
VFLll) is generated from the brightness determination circuit (17a).

In response to this, the integration time control circuit (17b) generates a storage section clear gate signal (STICG) to open the storage section clear gate (24) and remove the small amount of dark charge that was unnecessary accumulated in the storage section (23). It is discharged to the power supply (Vcc) side. Subsequently, the accumulation section clear gate (24) is closed as this accumulation section clear gate signal disappears. After this, the integral time control circuit (17b) immediately outputs the barrier gate signal (BG
), the barrier gate (22) is opened, and the accumulated charge in the pixel photodiode (PD) is transferred to the accumulation section (23). After the instruction signal (VFLG) is generated, it takes about 50 to 10 minutes until the transfer operation to the storage section (23) is completed.
A time (1) of 00 μs is required. After the charges accumulated in each pixel photodiode (FD) are transferred to the accumulation section (23) in this way, the integration time control circuit (17b
) gives an integration completion signal (TINT) to the system controller (53). In this embodiment, the transition from high level to low level in (TINT) represents the completion of integration.

This integration completion signal (TINT) is accepted as an interrupt signal in the system controller (53), and even while the system controller (53) is performing other processing, the processing is not important and therefore interrupts are disabled. If the other process is an interrupt disable process, the integration complete signal (TINT) is recognized immediately after that process is completed. Process. Based on this integration completion signal (TINT), the system controller (53) sets the address etc. for storing image information data in the memory section (55), and then sets the address etc. of the photoelectric conversion element (12).
A shift pulse generation signal (SHM) is supplied to the transfer lock generation section (16A) inside. As a result, the transfer lock generation section (16A) generates a shift pulse (SR), and applies this shift pulse (SH) to the shift gate (25) of the photoelectric conversion section (15) to transfer the shift pulse (SH) to the storage section (23). Transferring the charges accumulated to the appropriate integration level to the shift register (26) is carried out. Thereafter, the system controller (53) immediately sends the mode signal (MD
, ”) (MD2), a data dump mode signal is given to the photoelectric conversion element (12), and the photoelectric conversion element (12)
Set to data dump mode. In the above, the system controller (53) receives the integration completion signal (TI
Even if the completion of integration cannot be recognized due to interrupt disabling processing for about 101ls after reception of NT), the barrier gate signal (BG ) (22), the charge accumulated in the pixel photodiode (PD) during the loss has no effect on the desired charge accumulated in the accumulation section (23). It has no effect and its Io
The signal (ST) is set to low level in order to raise the potential level of the storage part during ns (details will be described later).
Therefore, the dark charge generated in the storage section (23) itself and added to the desired charge is extremely small and does not pose a problem. In FIG. 16(a), the shift pulse generation signal (
A shift pulse (which is approximately synchronized with SH and SHM)
The slight delay in the generation of SH) indicates that the processing of the integration completion signal (TINT) in the system controller (53) is delayed.

The integration time control circuit (17b) receives a barrier gate signal (
The color temperature detection gate signal (P
DS) also occurs. This color temperature detection gate signal (PD
S) indicates that during the period corresponding to the integral clear gate signal (ICG), the color temperature detection photodiode (13)
(14) The charge that was unnecessarily accumulated in the capacitor (
Color temperature detection photodiodes (13) (14) and capacitors (ca) (
Switching transistor between (Cs) (C4) (Qs)
is turned on, and even after the integral clear gate signal (ICG) disappears, it remains at a high level and the transistor (Qi) (
) are turned on, and charges generated in each color temperature detection photodiode (13) (14) are accumulated in each capacitor (C4) (cs). Then, from the generation of the instruction signal (V FLG) to the generation of the storage section clear gate signal (STICG), the barrier gate signal (BG) is generated.
When the color temperature detection gate signal (PDS) falls, the transistor (C4) (Qs) is turned off. As a result, the charge generated in each color temperature detection photodiode (13) (14) is transferred to the capacitor (
C4) The integration operation at (C%) is completed, and the potential at the time of completion is the color temperature detection output signal (O
SR) (O3Y).

The above explanation is for the low-luminance integration mode when the subject is comparatively light, but in the low-luminance integration mode when the subject is extremely dark, the integration completion operation etc. are slightly different. A time chart of each signal at this time is shown in FIG. 16(b). After starting the above-mentioned integration, the system controller (53)
While waiting for reception of the integration completion signal (TINT), the timer circuit (59) is used to measure the integration time. Then, if the integration continues even after 100 IIls have passed after the start of integration and the integration completion signal (TINT) is not received, the system controller (53) sends a shift pulse generation signal to force the photoelectric conversion element (12) to complete the integration. (
SHM). This shift pulse generation signal (SHM
), the integration time control circuit (17b) of the photoelectric conversion element (12) supplies the above-mentioned storage section clear gate signal (STICG) to the photoelectric conversion section (15) to clear the storage section (2).
3) After discharging unnecessary charges, the barrier gate signal (BG
) to transfer the accumulated charge of the pixel photodiode (PD) to the accumulation section (23). This completes the integration. The reason why the signal (ST) is not set to low level to raise the potential level of the storage section at this time is because there is almost no storage time in this storage section. The charges in each storage unit (23) are subsequently shifted to the shift register (26) by a shift pulse (SH) given from the transfer lock ordering unit (16A), and then transferred to the transfer lock (φ1) ( Sequentially capacitor (C1)
transferred to the side. In this way, when the integration is forced to complete based on a command from the system controller, the charge is not accumulated to the appropriate integration level, so the output level is small, which may cause a decrease in the S/N ratio or cause the system This may become inappropriate for the dynamic range of the A/D i converter (54) of the controller (53).

Therefore, in such a case, it is desirable to perform gain correction in the analog processing section (18). The brightness determination circuit (17a) described above in FIG. 15 determines the amount of gain correction, and depending on the amount of gain deficiency,
×4, ×8 output path (72) (73) (74) (
75) is selected (set to high level). The selected state is held until the next integration is completed and the monitor output signal is processed.

This concludes the explanation of the integration operation in the low-brightness integration mode. However, if integration is started in the low-brightness integration mode and the integration completion signal (TINT) is detected before 1ms, there will be many excessive integral components in the low-brightness integration mode. Therefore, the system controller (53) switches the mode signal (MO+) (MDz) to the high-luminance integration mode because the analog processing and ^/D conversion processing of the pixel output signal become saturated.

Next, the integration operation in this high brightness integration mode is shown in Figure 17 (
This will be explained with reference to the time chart of a).

First, the system controller (53) generates an integral clear signal (IC3) as in the low luminance integral mode.

This pulse width is chosen to be the same as in the low brightness integration mode.

Upon receiving this integral clear signal (IC5), the integral time control circuit (17b) sends an integral clear gate signal (ICG), an accumulation section clear gate signal (STICG), and a barrier gate signal ( At the 0th order, which generates BG), the integration clear signal (IC5) disappears and integration starts in the same way as in the low-luminance integration mode.
Since this time is a high-intensity integration, the barrier gate signal (BG) is output from the integration time control circuit (17b) as a high-level signal from the start to the end of the integration, as shown in FIG. 17(a). This means that the pixel photodiode (PD)
This means that integration is performed with the barrier gate (22) between the and the storage section (23) kept in an on state, and the charge generated in the pixel photodiode is stored in the storage section (23) from the beginning. Note that during this integration, the storage section clear gate (24) is turned off. Integration starts in this way, and the monitor output signal (AGCO5) changes to the monitor output compensation signal (AGCDO5) corresponding to its initial potential, as in the low-luminance integration mode.
When the instruction signal (VrLc) has decreased by a predetermined amount vth (= I x 8R) from the level of the luminance judgment circuit (
17a) and supplied to the integral time control circuit (17b). The integration time control circuit (17b) receives this instruction signal (Vrtc) and sets the barrier gate signal (BG) to a low level, thereby turning off the barrier gate (22) which has been off until that point. This stops the charge flow from the pixel photodiode (PD) to the storage section (23), and also stops the charge from flowing into the storage section (23).
) to send an integration completion signal (TINT). In this way, in the high-brightness integration mode, there is no need to transfer charge from the pixel photodiode (PD) to the storage section (23), which was seen in the low-brightness integration mode, but simply through the pass gate (22).
Since the integration completion operation can be completed simply by switching from the on state to the off state, the delay in completing the integration with respect to the instruction signal (VFLG) can be eliminated as shown in FIG. 17(a). On the other hand, in low-luminance integration mode, there is a time delay of 50 to 100 trs (
t) [see FIG. 16(a)] occurs. When the barrier gate (22) is turned off, the signal (ST) is set to a low level to raise the potential of the storage section and reduce the generation of dark charges. In this way, the storage part (2
3) The charge integrated to the appropriate integration level is transferred to the system controller (5) in the same way as in the low-luminance integration mode.
3) inputs the shift pulse generation signal (St(M)) and transfers the shift pulse (SFI) and lock (φI) (φ
2) is shifted to the shift register (26) under the control of the transfer lock generating section (16A) and sequentially transferred to the output capacitor (C1) of the shift register (26). The signal (ST) becomes high level in synchronization with the disappearance of the shift pulse (SH), thereby returning the charge in the storage section to its original state. The color temperature detection gate signal (PDS) that controls the integration of the output of the color temperature detection photodiodes (13) and (14) is here referred to as the barrier gate signal (
BG) and is output as a signal with the same value as the barrier gate signal (
The pixel photodiode (PD) falls at the falling edge of BG).
Color temperature detection output signal (O3R) at the time of completion of integration (
OSY) output is held.

Incidentally, a case where the brightness of the subject is extremely low in the high brightness integration mode is shown in the time chart of FIG. 17(b). In this case, since the integration completion signal is not generated within the predetermined time measured by the timer circuit of the system controller (53), the system controller side (TIN
(S) is generated before the reception of T), and the integration operation is completed. The operation for completing the integral operation is the same as that shown in FIG. 17 (5).

In the above, the integration operation of the photoelectric conversion unit (15) has been explained in the low-intensity integration mode and the high-intensity integration mode, respectively. Gate (22), storage section (23), shift gate (25), shift register (
26) schematically shows the physical operation.

Also, in these figures, the pixel photodiode (PD)
Other parts are indicated by symbols of applied signals. Furthermore, (OG
) shows an outgate attached to the end of the pixel photodiode (PD), and if necessary, for example, as shown in FIGS. In this case, this Aratogame-l-(
Unnecessary charges can be discharged through OG). 1st
FIG. 9 shows the low-brightness integration mode, and FIG. 20 shows the high-brightness integration mode.

In FIG. 19, (a) is during integration. (b) shows the integration completion operation (i) in which the charge in the storage section (23) is transferred to the storage section clear gate before the charge of the pixel photodiode (PD) is transferred.
) (24) to the power supply (Vcc). (C) shows the operation of transferring the charge of the pixel photodiode to the storage section (23) as the integration completion operation (ii). (d) shows the state at the time of completion of the integration, where the potential control signal of the storage section ( ST) is changed from a high level to a low level to raise the potential level of the storage section, and this is for the following reason. Pixel photodiode (PD)
In a state where the storage part (23) retains charge from a deep potential, dark charge is likely to occur in the storage part itself and the amount of stored charge changes. Therefore, by making the potential shallow, the storage part itself This is to suppress the generation of dark charge. Regarding this point, the same applies to the high brightness integration mode shown in FIG. 20. FIG. 19(e) shows initialization,
That is, it shows an integral clearing operation.

In high-intensity integration mode, Fig. 20(a) shows that during integration, (
b) shows the completion of integration, and (c) shows charge transfer to the shift register. Even in this case, the integration clearing operation is performed as shown in FIG. 19(e).

Next, regarding the analog processing section (18) shown in FIG.
This will be explained with reference to the time charts of FIGS. 16 to 18. As shown in FIG. 7, the first to fifth segments from the right of the shift register (26) do not have corresponding pixel photodiodes. Therefore, the buffer (27)
The first five of the pixel output signals (O3) outputted through are the outputs of the register segment without photodiode, followed by the output of the shaded pixel photodiode (OPD) from the 6th to the 10th, and then , the output of the pixel photodiode in the reference part (M.), the unnecessary part (
The output of the register segment corresponding to S), the reference part (
M, ), and finally the output of the light-blocking pixel photodiode (OPD) on the left side. The output waveform is shown in Figure 18 (
O8).

Initialization of the pixel output signal (O3) is performed by resetting the capacitor (C+) in FIG.

At that time, a reset pulse (OSRST) is applied to the gate of the transistor (Ql) to make the transistor (Ql) conductive and charge the capacitor (C3) to the power supply voltage (Vcc). At times, a signal induced by the clock field-through effect of the MOS transistor (Q+) is generated, and when this reset pulse (OSRST) ends, the capacitor (C+) is charged to approximately the power supply voltage and returns to its original reference level. However, this reference level varies depending on the power supply voltage fluctuation when the reset pulse (OSRST) is applied.
Next, at the falling edge of the transfer lock (φI), the shift register (26) transfers one phase, and the accumulated charge of the next pixel photodiode flows into the capacitor (C8) and is output.

The amount of voltage drop at this time is the pixel output signal V os (n) that is proportional to the amount of light incident on the pixel photodiode. Next, another reset pulse (OSRST) is applied to the transistor (Q, ) to reset the capacitor (C4), and at the next transfer lock (φ1), the pixel output signal V os (n + 1) of the next pixel photodiode is ) is obtained. Pixel output signals are sequentially output in this manner, and the series of pixel output signals output in this way is sent to the 18th pixel output signal in the first sample and hold circuit (66).
A circuit (67) that subtracts the differential with (v, ls) sampled and held at the timing of (RSS/H) in the figure.
By taking this value, the reset level of the differential output (OSdir) is adjusted to a constant value, and the voltage drop from that level becomes the value of the pixel output signal. This power supply noise removal ability is generally called a double sampling method.

Next, using the differential output (OSdir) thus obtained, a second sample and hold circuit (not shown) provided in the same subtraction circuit (67) performs sample and hold. This is to ensure time for keeping the input analog amount constant for the AID converter (54) in the system controller (53) at the subsequent stage. The subtraction circuit (67)
The pixel output signal sampled and held at is shown in Figure 18 (
V oss/H), VO3(n) and Vo
s(n+1), resulting in a signal with a value lowered by Vos(n+2).

Among the pixel output signals (Vos) processed in this way, the seventh to ninth dark pixel output signals are sampled and held in the next third sample and hold circuit (7o). As shown in FIG. 16, the sampling pulse (OBS/Fl) at this time is exactly equal to the pixel output signal (Vos).
Among them, the pulse is such as to extract the output signal of the light-shielding pixel photodiode (OPD) that is shielded from light by the seventh to ninth aluminum films. Note that the sixth signal is not sampled and therefore is not used.
This is due to the following reason. That is, the sixth pixel output signal is output from the light-shielded pixel photodiode (OPD) as shown in FIG.
Since it is located at the farthest end of these, it is easily affected by external noise, and therefore its output is not necessarily an accurate dark pixel output. Said (OB
The 7th to 9th dark pixel outputs sampled by S/H) are held at least until the output of the series of pixel photodiodes ends (until the 128th output in the shift register segment is processed). shall be taken as a thing.

In this way, the sampled and held dark pixel output (V
an) 7) The differential with the pixel output signal (Vos) outputted from the 11th and subsequent stages is calculated by the AGCfi calculation circuit (71) in the next stage.
By taking this, it is possible to obtain a pixel output signal (Vos) based only on the photocharge output with the dark output removed.

This subtraction is performed by the AGC subtraction circuit (71) shown in FIG.
). In Figure 15, (A,) is the terminal (
77) and the dark pixel output (■.,) input from the terminal (
This is an operational amplifier that takes a differential with the pixel output signal (Vos) input from 76). Furthermore, this operational amplifier (A,)
Resistor (r+) (rz) (rs) (r4) connected between the output terminal and negative input terminal (-) of
The resistor (r,) (r,) (r7) (rs) connected between the positive input terminal (+) and the analog switch (S+) is controlled by the gain control signal (AGC) mentioned above.
By switching through .about.(S,), the gain deficiency of the image output signal due to the forced stop of integration at low luminance is corrected. The signal passing through this AGC subtraction circuit (71) is output from the photoelectric conversion element (12) to the system controller (53). Therefore, the output level is adjusted to the dynamic range (1/3 V ref≦DR≦Vref) of the A/D converter (54) in the system controller (53), the pixel output in the dark is set to (Vref), and the pixel output ( If the AGC subtraction circuit (Vos) increases, the AGC subtraction circuit (
71) is configured. That is, when a pixel output voltage (Vos) equal to the dark output voltage (■.,) input to the terminal (77) is input to the terminal (76), the output of the operational amplifier (A,) is V ref, and the input (V
.

When S) becomes lower than (Vow), the operational amplifier (A,
) output becomes Vref-Vos.

On the other hand, the color temperature detection output signals (O5R) (O5Y) are differentiated from the color temperature detection compensation signal (PDDOS) which acts as a reference voltage output in the second and third subtraction circuits (68) and (69).

Furthermore, in order to compensate the differential output during dark time, make it an appropriate gain, and adjust it to the reference voltage, the above-mentioned AG
It is supplied to the C subtraction circuit (71). At this time, the timing of supply to the AGC subtraction circuit (71) is determined by the timing of supply to the subtraction circuit (67) (
68) Analog switch (ANl) following (69)
) (An operation is performed by control signals (ANS+) (ANSz) (ANS2) shown in FIGS. 16 and 17 given from the signal processing timing generator (16B) for AN (8N3).

As a result, in this embodiment, as shown in the pixel output signal (Vos) in FIGS. 16 and 17, during the output of the 10th pixel output signal immediately after the sampling of the dark output, the The yellow temperature detection signal (O3Y) is
During the output of the 11th pixel output signal, the red temperature detection signal (O5R) is sent to the AGC subtraction circuit (7
1). In addition, the color temperature detection signal (O31?)
(O5Y) is not output using a separate output buffer in the photoelectric conversion unit (15), but instead uses a light-shielded pixel photodiode (OPD) as shown in Figure 13, which is the same as the normal pixel output signal. In the case of outputting through the path, the signals are outputted from the buffer (27) as the 10th and 12727th elementary output signals. Therefore, these outputs are subjected to the aforementioned double sampling to remove noise components,
After the dark time output is compensated by taking the difference from the dark time output sampling value, it is supplied to the AGC subtraction circuit (71). In this case, the second and third subtraction circuits (6B) (6
9) and analog switches (ANI)
) is no longer needed.

This concludes the explanation of the analog processing section (18), and next the temperature detection section (19) will be explained. Among the autofocus detection mechanisms shown in Fig. 2, for example, the lens holder (9)
The acrylic material portion and the substrate (5) holding the re-imaging lenses (4a) (4b) expand depending on the temperature, causing subtle changes in the dimensions of predetermined portions.

This causes autofocus errors due to temperature.

From this point of view, a temperature detection section (19) is provided to electrically perform temperature compensation;
), as shown in Figure 21, a resistor (R+) (Rz) is connected in series between the reference voltage (V ref), which has a predetermined potential lower than the power supply (Vcc), and the ground, and the midpoint of the connection is connected to the operational amplifier. Connected to the positive input terminal (+) of (A,). Connect the negative input terminal (-) and output terminal directly.

Here, the resistance (R1) has a temperature coefficient βR+=5000pp
m ion-implanted resistance, (Rg) is the temperature coefficient βR2=
It is a polysilicon resistor of 500 pp-, and its resistance value at 25°C (1 (Rg) is 10 KΩ. In Fig. 21, the power supply voltage Vcc = 13 V, the reference voltage V
FIG. 22 shows the output characteristics of the temperature detection section when ref = 5V. The detection output is expressed by the voltage across the resistor (R+).

In the time charts of FIGS. 16 and 17, AG
The pixel output signal ('v
os), up to the 9th output is a photoelectric conversion element (
12) as the output signal of the system controller (53).
There is no need to provide it to the system controller (53
) is the red temperature detection signal (OSI?) located at the 10th position. Therefore, up to the ninth pixel output signal, the temperature detection signal (Vtts
) through the same output line to the system controller (
53). For this reason, analog switches (ANA) (AN,) are provided before the connection point (A) between the AGC subtraction circuit (71) and the temperature detection circuit (19), and these analog switches (AN,) (AN ,)
The gate signal (AN) shown in FIG. 16 (and FIG.
S4) (ANSS) is supplied.

Next, the specific configuration of the transfer lock generating section (16) will be explained in the second section.
6(a) and 26(b), of which the 26th
Figure (a) shows the part that forms the shift pulse (SH), and Figure 26 (b) shows the transfer lock (φl) (φ2), (O5R5T) (R5S/)l) (05S/H).
Figure 26(a) shows the part that generates (ADT) etc.
(16a) is a system controller (53)
This is the first frequency divider that divides the basic tarokk (CP) from (SHM)CICG)(TINT
), the frequency is divided by the second frequency divider (16c) which is reset by the output of the shift pulse forming section (16b) which forms the shift pulse (S11), and (QDO) (QD
I) (QD2) is generated. These outputs are shown in Figure 26 (
Decoded by the decoder section (16d) in b) and passed through the circuit following the decoder section (16d) (φ1) (φz)
(O3R3T) etc. are created.

FIG. 27 shows a specific example of the signal processing timing generator (20a), which inputs (φ+) (SR) (ICS) and generates (ANS,) to (ANSs) and (OBS/H).
(ADT) is generated. (ADT) is a control signal that triggers A/D conversion of the system controller (53).

Next, the system controller (53) will be explained.

A/D converter (54) in the system controller (53)
) is formed as shown in Fig. 23, and the terminal (78
) is the pixel output signal (
Vout) is input, and the reference voltage (Vr
ef), (ADT) is input to the terminal (80). Then, the AID conversion output is derived from the terminals (01) (Ot)...(On>).

The system controller (53) detects the color temperature of the subject by calculating the ratio R of the digital values (Vos++) (Vosy) of the A/D-converted color temperature detection signal (OSR) (O5Y), and detects the color temperature of the subject. Corrections are made according to the temperature, and the flowchart is shown in the second section.
Shown in Figure 4. FIG. 24 shows the flow of the entire focus detection operation, and FIGS. 25 (a), (b), (c) and (cl) show the flow of color temperature correction in particular.

First, an outline of the focus detection operation will be explained using FIG. 24. When the focus detection operation is started by pressing the shutter button on the camera, the system controller (53) resets the flag and inputs lens data including color temperature correction data from the lens data output section (61). The system controller (53) sets an integration mode (ST) in which the storage unit performs storage (signal MDI = low level, Mn2 = high level), and sets the maximum integration time to 2Qmsec. Then, an integration clear signal (IC5) is generated to start integration. At this time, the integration of the color temperature detection photodiodes (13) and (14) is also performed at the same time. Then, it waits for the integration end signal (TINT) indicating the end of integration to become low level, and when it becomes low level, it is determined that the integration has ended, and the time required for this is determined. If the time is within 1m5ec, the high-luminance flag (HLF) is set to set the next integration mode to the mode for integrating into the storage section (ST mode), and the time is 1m5ec.
If c~20+m5ec, the next integration mode will be the same as this time, and the integration end signal (TI
NT) does not become a low level, a low luminance flag (LLF) is set so that the next integration mode will be a mode (PD mode) for integrating into the light receiving section. In either case, a signal (SHM) is output to indicate the completion of the integration operation, and the process waits until the integration completion signal (TINT) becomes low level. This allows 20m5e in low brightness integration mode.
Only when the integration is not completed within c, it is waited for the integration end signal to become low level; otherwise, it is already low level. Note that pixel data is sent to the shift register by a shift pulse in terms of hardware.

Then, when the integration end signal (TINT) is at a low level, the system controller (53) sets the data input mode and inputs the AGC data of the digital signal.

Next, temperature data is input, but A/D conversion for this analog data is started by a pulse of a signal (ADT), and the end of this A/D conversion is waited. When the A/D conversion is completed, temperature data (SBT) is input and stored in a predetermined register. As described above, this temperature data input is at the timing of the ninth data input of the shift register (26) (see the time chart) (no data is input to the shift register).

Next, the system controller (53) sets the number of pixels of the captured data, including the number of color temperature detection photodiodes and the number of pixel output signals, and sets the input analog signal (V
os), stores the data in the internal memory every time an interrupt signal is generated due to the termination, and repeats this for the set number of times, thus converting the reference section stored in the memory (55). The digital signals corresponding to the images of the (?IG) and reference portion (Ml) are converted to the images of both portions (M.) (? Defocus df is calculated by determining the image interval of Ml). After calculating df+ by distance measurement calculation, temperature correction is also performed based on the output from the temperature detection section (19). Therefore, β is the temperature correction coefficient of the camera itself, SBT is temperature information, and 5BTo is basic temperature information at 25°C. The defocus df after performing this temperature correction is set so as to have a true value when the light source of the subject is sunlight.

This defocus IdfO is set to a predetermined value Tdf (=2~”
If it is larger than 3m+a), the color temperature correction value is not that large (approximately 100 to 200μm or less), so the correction value itself does not have a large effect, and the lens is driven and re-measurement is performed. When the predetermined value Tdf
When the following defocus is detected, a color temperature correction value Δdf is added. After the color temperature correction value △df is added in this way, focus is determined. If it is within the focus range, an in-focus display is performed, and if it is determined that it is out of focus, the color temperature correction value △df is defocused. The lens drive is started according to the detected defocus ldf added to ldf, and the routine from the step of starting integration by IC5 generation after setting the integration mode is repeated.

Here, we will add an explanation of the internal operation of color temperature correction.

As mentioned earlier, the lens color temperature correction data dF is input at the top of the flowchart.

This value is, for example, the amount of chromatic aberration of each lens with respect to 550 nm (daylight) when an 800 nm monochromatic light source is stored in the memory within the lens. On the other hand, the output signal (O5R) of the color temperature detection photodiode is integrally controlled simultaneously with each pixel photodiode and subjected to analog processing.
O5Y) is digitized by the A/D converter (54) of the system controller (53) and becomes (Vos+i) ('VO
! IY) in the memory (55).

As shown in FIG. 25(a), the system controller (53) controls the ratio R of (Vosm)(Vosy)
Calculate. When this ratio R is a predetermined value, for example, 1.8 or more, it is determined that the incident light from the subject has many long wavelength components and has a low color temperature, and the dF of the color temperature correction data is determined.

is multiplied by a predetermined coefficient k (0≦+≦1) to obtain the color temperature correction amount Δdf. Conversely, when the ratio R is 1.2 or less, the incident light from the subject has many short wavelength components (and the color temperature is determined to be low, and a predetermined coefficient -kt (0≦ is multiplied by 2≦-1), and the color temperature correction amount is Δdf.When the ratio R is between 1.2 and 1.8, the incident light from the subject has a component close to daylight. The color temperature correction amount Δdf is integrated by the light, and no color temperature correction is necessary, and the color temperature correction amount Δdf is set to Δdf = 0. In this way, the color temperature correction amount Δdf determined depending on the light from the subject.
is added to the defocus amount dfo obtained by distance measurement calculation to calculate the true detected defocus amount df.

Color temperature correction is performed in this way, but another method is to include the necessity of color temperature correction as lens data depending on the type of lens, and perform color temperature correction as shown in the flowchart in FIG. 25(b). By first determining whether or not to perform color temperature correction, if color temperature correction is not necessary, speed can be increased without going through an extra flow. Also, instead of determining each correction value discretely as in (a) and (b),
The second flow of determining the correction value continuously for the value of R is
This is shown in Figure 5(c). Here, R may show infinity for an object having a single wavelength component of a short wavelength, whereas the chromatic aberration of an optical system naturally has a finite value as long as it is visible light. To add restrictions for that, R
In the case of ≧2.5, the value of R is limited to 2.5, and the correction amount is determined from the color temperature defocus correction amount of the lens described above, a predetermined coefficient of 1, and the ratio R at the reference daylight color. 1.
Determined by multiplying by the value subtracted by 5.

Next, when performing discretely as shown in FIG. 25(a),
If it is possible to set the value of the correction amount Δdf for each lens, the correction amount Δdf will be R≧1 as shown in FIG. 25(d).
．． When R≦1.2, the value dfl is given to each lens, such as dr when R≦1.2, and dft when R≦1.2.

Become dfz.

In any case, in the embodiments described above, the color temperature of long wavelength components and short wavelength components within visible light is detected and corrected, so that the accuracy of focus detection is improved.

In the above embodiment, the light-shielded dark-time compensation light-receiving element for canceling the dark-time charge output of the color temperature detection light-receiving element of the present invention is an aluminum light-shielded light-shielding pixel photodiode ( OPD). This light-shielded pixel photodiode (OPD) is also used for dark-time output compensation of the pixel photodiode (PD) as a light-receiving element for focus detection, but without being limited to this example, it is possible to use a light-shielded pixel photodiode for dark-time compensation. The light receiving element for color temperature detection and the light receiving element for focus detection may not be used together, but may be provided separately.

Effects of the Invention According to the - aspect of the present invention, the output of the light receiving element for color temperature detection is obtained by an integral operation, so even if the subject is of low brightness, the output is large enough to serve as color temperature correction data. It has the effect of being able to give Note that if the photocharge accumulation time of the color temperature detection light receiving element is controlled to be the same as the photocharge accumulation time of the focus detection light receiving element, it can be expected that the configuration of the control system will be simplified. At that time, if the size of both photodetectors is the same,
Both detection signals can be suitably processed by the same signal processing system. Furthermore, if the output signal of the light receiving element for color temperature detection and the output signal of the light receiving element for focus detection are transmitted in a time-sharing manner through the same line to the circuit side where the focus detection means and correction means are located, the output line It is possible to realize a reduction in the number of terminals and a corresponding reduction in the number of terminals.

Further, according to the second aspect of the present invention, in addition to enjoying the effect at low luminance as in the invention (-), the output of the light-receiving element for color temperature detection is compensated for in the dark, so that the color temperature can be detected. The signal becomes extremely accurate and reliability increases.

[Brief explanation of the drawing]

All figures relate to the present invention, and FIG. 1 is a diagram showing the principle of an optical system related to focus detection. FIG. 2 is an exploded perspective view of the sensor module.
FIG. 3 is a schematic configuration diagram of a photoelectric conversion element. FIGS. 4 and 5 are characteristic diagrams for explaining the spectral sensitivity of the color temperature detection photodiode. FIG. 6 is a block circuit diagram of the photoelectric conversion element, and FIG. 7 is a diagram showing the circuit configuration of the photoelectric conversion section. FIG. 8 is an enlarged view of a part of FIG. 7, and FIG. 9 is a sectional view taken along the line A-A' in FIG. FIG. 10 is a structural diagram showing the physical structure of a pixel photodiode. FIG. 11 is a diagram showing the structure of the output section of the shift register in FIG. 7 in comparison with a conventional example. 12th
The figure is a diagram showing a schematic shape of a photoelectric conversion unit viewed from the light incident direction. FIG. 13 is a diagram of another embodiment corresponding to FIG. 8. FIG. 14 is a block circuit diagram showing the overall configuration of the image sensing system, and FIG. 15 is a specific circuit diagram of a portion thereof. 16 and 17 are time charts of each partial signal of FIG. 14 in the low-luminance integration mode and the high-luminance integration mode, respectively. FIG. 18 is a diagram of various signal waveforms for explaining the operation of the analog processing section in FIG. 14. FIGS. 19 and 20 are diagrams showing the physical operation of the photoelectric conversion section in the low-brightness integration mode and the high-brightness integration mode, respectively. FIG. 21 is a specific circuit diagram of the temperature detection section, and FIG. 22 is its output characteristic diagram. FIG. 23 is a circuit diagram of the A/D conversion section of the system controller. FIG. 24 is a flowchart showing the operation of the system controller, and FIG. 25 is a flowchart showing a portion thereof in detail. FIG. 26 is a specific circuit diagram of the transfer lock generation section, and FIG. 27 is a specific circuit diagram of the signal processing timing generation section. (1)...Taking lens, (13) (14)...
・Photodiode for color temperature detection (light receiving element for color temperature detection), (17)...integration time control section (control means),
(53)...System controller (56)・
...Focus detection section (focus detection means). (57)...Correction calculation unit (correction means) (PD)
...Pixel photodiode (light receiving element for focus detection),
(OPD)... Light-shielding pixel photodiode (dark time compensation light receiving element).

Claims (6)

[Claims] (1) A photoelectric conversion type focus detection light receiving element that receives the subject light that has passed through the photographic lens, a focus detection means that detects the in-focus state based on the output of the focus detection light receiving element, and the subject. A color temperature detection means consisting of a plurality of photoelectric conversion type color temperature detection light-receiving elements that are filtered with mutually different spectral characteristics in order to detect the color temperature of light; and a color temperature detection means based on the output of the color temperature detection means. an automatic control device comprising: a correction means for correcting the output of the focus detection means; and a control means for controlling the focus detection light receiving element to operate in an integral type that accumulates and outputs photocharges generated by light reception for a predetermined time. An automatic focus detection device, characterized in that the color temperature detection light receiving element also operates in an integral type. (2) The automatic focus detection device according to claim 1, wherein the photo charge accumulation time of the focus detection light receiving element and the color temperature detection light receiving element are controlled to be the same. (3) The automatic focus detection device according to claim 2, wherein the focus detection light receiving element and the color temperature detection light receiving element are formed to have substantially the same size. (4) The output signal of the focus detection light-receiving element and the output signal of the color temperature detection light-receiving element are time-divisionally transmitted through the same line to the circuit in which the focus detection means and correction means are present. An automatic focus detection device according to claim 1. (5) A photoelectric conversion type focus detection light receiving element used in an integral operation that accumulates and outputs photoelectric charge generated by receiving object light that has passed through a photographic lens for a predetermined time; and a plurality of photoelectric conversion type color temperature detection light receiving elements that are filtered with mutually different spectral characteristics in order to detect the color temperature of the subject light by an integral operation. a color temperature detection means comprising; a correction means for correcting the output of the focus detection means based on the output of the color temperature detection means; and a correction means for canceling the dark charge output of the color temperature detection light receiving element. An automatic focus detection device comprising: , a light-shielded dark-time compensation light receiving element; (6) The dark-time compensation light-receiving element is provided so as to be used for both dark-time compensation of the output of the light-receiving element for color temperature detection and dark-time compensation of the output of the light-receiving element for focus detection. The automatic focus detection device according to scope 5.