JPS63296477A - Image sensing system - Google Patents

Abstract

PURPOSE:To fetch an image signal in a wide range with a suitable level and in a condition almost regardless of a dark time-output by making an integration control form different in a low luminance time and in a high luminance time. CONSTITUTION:A first control means to make gate means 22 and 25 non- operative, to hold an electric signal by a light receiving means 21 for a photo-e lectric converting, to pulsatively operate the gate 22, to accumulate the held electric signal to an accumulating means 23, after that, to pulsatively operate the gate 25 and to move the accumulated electric signal to a shift resistor means 26 and a second control means to operate the gate means 22, to make the gate means 25 non-operative, to accumulate an electric signal the light receiving means 21 for the photo-electric converting outputs to the accumulating means 23, to make the gate 22 non-operative, after that, to pulsatively operate the gate means 25 in an instant and to move the accumulated electric signal to the shift resistor means 26 are equipped. Thus, respectively, in a low luminance time and in a high luminance time, a desirable integrating control can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image sensing system, and more specifically to the accumulation (integration) and utilization of charges generated in a light receiving means for photoelectric conversion according to the amount of incident light. The present invention relates to an image sensing system of the type described above.

Analysis Such an image sensing system is used, for example, in an automatic focus detection device of a camera. Image sensing systems used in such automatic focus detection devices are required to have faster autofocus and improved performance when the subject has low brightness. Therefore, efforts are being made to increase sensitivity by expanding the light-receiving area of the light-receiving means and increasing the photoelectric conversion efficiency. However, if this is done, the accumulated charge will quickly become saturated when the subject is of high brightness. Therefore, the integration time set in the system becomes very short. Therefore, short-time integral control is required.

On the other hand, when the brightness of the subject is low, such short-time integration control is not necessary; rather, even if the light receiving means is highly sensitive, it takes a relatively long time to accumulate (integrate) the charge, and the amount of incident light is Since undesired charges (dark charges) generated in unrelated storage sections cause errors and reduce reliability, an integral control method that is not affected by such dark charges is desired.

However, “Toshiba Review” 36 published in 1982
In the conventional system described in Volume 10, the integration form is uniform regardless of whether the luminance is low or high, and the above-mentioned consideration is not taken for each of low luminance and high luminance.

As mentioned above, in the conventional example, it was not possible to perform desirable integral control both at low brightness and high brightness.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensing system in which integral control forms are made different between low brightness and high brightness, and which are selectively switched.

In order to achieve the above-mentioned object, the image sensing system of the present invention comprises: a light receiving means for photoelectric conversion consisting of a plurality of light receiving element arrays that output electrical signals according to the intensity of incident light; the light receiving means for photoelectric conversion; an accumulation means having a plurality of accumulation parts for accumulating electrical signals respectively; a first gate means comprising a plurality of gates connected between the photoelectric conversion light receiving means and the accumulation means; Shift register means for receiving electrical signals and sequentially outputting them at timings according to predetermined clock signals; Second gate means comprising a plurality of gates connected between the storage means and the shift register means; Start of predetermined accumulation; In response to the signal, the first gate means and the second gate means are inactivated, and the electric signal is held by the light receiving means for photoelectric conversion, and in response to a predetermined accumulation end signal, the first gate means is first activated in a pulsed manner. is activated to cause the electric signal held in the photoelectric conversion light receiving means to be accumulated in the storage means, and then the second gate means is activated in a pulse manner to shift the electric signal stored in the storage means to the storage means. A first control means that operates the first gate means in response to a predetermined accumulation start signal and disables the second gate means to transfer the electric signal output from the photoelectric conversion light receiving means to the register means; In response to a predetermined accumulation end signal, the first gate means is deactivated, and the second gate means is then momentarily activated in a pulsed manner to discharge the electrical signal accumulated in the storage means. a second control means for controlling the first gate means and the second gate means so as to transfer the data to the shift register means; a switching means for selectively operating the first control means and the second control means; .

According to such a configuration, the first and jth units perform mutually different control operations. The second control means can be operated by switching means, for example, so that the first control means is activated when the brightness is low, and the second control means is activated when the brightness is high.

Then, when the first control means operates, charge accumulation (integration) based on the amount of incident light is performed only in the photoelectric conversion light receiving means while the first gate means is off. This charge can be accumulated independently of the dark charge generated in the storage section. For example, if the dark charge is discharged (discharged) in advance as an unnecessary signal at the end of accumulation (integration), then when the charge of the light receiving means is transferred to the storage section, the dark charge It will not be affected by charge at all.

When the second control means is activated, the charge generated in the photoelectric conversion light receiving means after the first gate means is activated is accumulated in the accumulation section, thereby performing an accumulation (integration) operation. The accumulation (integration) operation is completed when the first gate means becomes inactive. Therefore, the accumulation (integration) is completed in real time without any time delay.

This means that integral control can be quickly performed when the subject is of high brightness.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied as an image sensing system to an automatic focus detection device of a camera will be described below.

As shown in Figure 1, the focus detection optical system (OF) that constitutes the focus detection device of the camera is an infrared light cant located behind the planned focal plane (F) behind the photographic lens (1). A filter (10), a condenser lens (2), a pair of re-imaging lenses (4a) (4b) with an aperture mask (3) located behind them, and these re-imaging lenses (4a) (4b). AF (autofocus) as a component of a focus detection light receiving section (RF), which has a charge-coupled device (COD) provided on the image plane of the image plane as a light receiving element.
The photo sensor array consists of the main parts (6), (7), etc.

When using a photo sensor array for AF that has a relatively flat spectral sensitivity within visible light (V), such as silicon, for example, the long wavelength component ( For example, λ = 720nI11)
Because the imaging point of (IJ) moves to the rear of the planned focal plane (F) due to the axial chromatic aberration of the photographing lens (1), it is generally compatible with objects that contain many reflected light components. The image interval (fu) is visible light (V) [center of gravity (λ=5
Image interval Civ corresponding to a subject that contains many reflected light components of 6Or+m)) (corresponds to the focal position detection signal)
Become bigger.

FIG. 2 shows the configuration of an AF sensor module (MP) that integrates the above-described focus detection device. This AF sensor module (MF) has a built-in optical path converting mirror (8), and above this mirror (8) is the aforementioned condenser lens 2), a field mask (9), and a wavelength of 750 nm or more. Infrared light cut filter (
10) are arranged.

Here, the infrared light cut filter (10) not only removes unnecessary infrared light to minimize the adverse effects of chromatic aberration, but also protects against long wavelength incident light, which is seen in semiconductor line sensors such as CCDs. This also prevents the reliability of the goldfish signal from deteriorating due to increased variations in the light sensitivity of each pixel.

Each of these components is supported by a lens holder (11), and is arranged perpendicularly to the optical axis converted by the optical path conversion mirror (8), including an aperture mask (3) and a pair of re-imaging lenses. (4a) A substrate (5) having (4b),
It has a basic structure in which a photoelectric conversion element (12) containing the above-described photosensor array is supported.

FIG. 3 shows the configuration of the photoelectric conversion element (12) of the AF sensor module (MP).

In the photoelectric conversion element (12), a focus detection light receiving part (R
F) (in Fig. 3, the main parts (6) and (7) of the two photosensor arrays shown in the principle diagram of Fig. 1 are shown as continuous) , a pair of color temperature detection photodiodes (13)
(14) are lined up almost parallel to each other. Then, the two re-imaging lenses (4a) (4b) are used to detect the photo sensor array and color temperature detection photodiode (13).
) (14) A subject image is formed above.

Figure 4 shows the spectra of the photodiodes (PD') that make up the color temperature detection photodiodes (13) and (14), and the dye filter placed above them, with wavelength on the horizontal axis and relative spectral sensitivity on the vertical axis. This shows the sensitivity characteristics.

Here, (13') shows the spectral sensitivity characteristics of the yellow dye filter, and (14') shows the spectral sensitivity characteristics of the red dye filter. Therefore, the spectral sensitivity characteristics of the color temperature detection photodiodes (13) and (14) are obtained by multiplying (PD') in FIG. 4 by (13") and (14"), respectively.

The color temperature detecting photodiodes view approximately the same subject through separate re-imaging lenses.

The graph in FIG. 5 shows the spectral energy distribution of light from various light sources. The horizontal axis is wavelength, and the vertical axis is relative spectral sensitivity or energy.

The curves (A), (B), and (C) in the figure are, respectively,
It shows the spectral energy distribution of light from standard light 'aA' such as a tungsten lamp, sunlight, and light from a white fluorescent lamp. In addition, (13'), (14") and (PD
The curve ') is based on FIG.

In addition, in the figure, the two-dot chain line (IR) at the 750 nm position is
The cut wavelength by the infrared light cut filter (10) described above is shown.

As will be described later, based on the output currents from the color temperature detection photodiodes (13) and (14), which are the pair of color temperature correction light receiving sections, specifically, based on the ratio, the focus detection It detects the spectral energy distribution of the measurement light.

That is, as can be seen from the graph, the difference in output from both photodiodes (13) and (14) is significant.
Since the area is about 600 nm or more, if the area of both is designed to be 1:1, the output from both photodiodes (13) and (14) will be almost the same for the light from the white fluorescent lamp, and the ratio is approximately It is 1.0. Furthermore, under light from a standard light source, the light energy becomes significant above 600 r+m, so the ratio of the outputs from both photodiodes (13) and (14) is large, approximately 2.0. Furthermore, the distribution of light energy in the infrared light region of sunlight is approximately between the light from a white fluorescent lamp and the light from standard light source A, and the output from both photodiodes (13) (14) The ratio is approximately 1.5.

Further, a first color temperature detection photodiode (13),
The second color temperature detection photodiode (14) is provided on the same chip adjacent to a reference part and a reference part of the photodiode array section, which will be described later. There is.

Next, the structure of the photoelectric conversion element will be explained using FIGS. 6 to 13. First, as shown in FIG. 6, the photoelectric conversion element (12) includes a photoelectric conversion section (15) having a photodiode, a shift register, etc. that generates a photocharge according to the amount of irradiated light, and a photoelectric conversion element (15) that has a photoelectric conversion section (15) that has a photodiode, a shift register, etc. that generates a photoelectric charge according to the amount of irradiated light. A data output control section (16) that controls charge transfer to the register side, charge transfer in the shift register, and signal processing timing of the analog processing section (to be described later), integration time of the photoelectric conversion section (15), etc. an analog processing unit (18) that processes analog signals from the photoelectric conversion unit (15), and a temperature detection unit that supplies temperature information to a system controller (described later) due to temperature changes. section (19), and I10 control section (2
0). And this photoelectric conversion element (
12) is formed as a one-chip IC with each of the above-mentioned components provided on one substrate.

The photoelectric conversion section (15) includes the pair of color temperature detection photodiodes (13) and (14) described above, a photodiode array section (21), a barrier gate (22), an accumulation section (23) for temporarily accumulating charges, and an accumulation section. Department clear gate (24),
It is composed of each main element of a shift gate (25) and a shift register (26), and each of their output buffers, that is, an output buffer (
27), an output buffer (28) for a monitor photodiode (MPD) inserted into the photodiode array as described later, and a color temperature detection photodiode (28).
13) (14) output buffer (29) (30)
, a monitor output compensation signal output buffer (31) for dark-time correction of the monitor photodiode (MPD) output, and a color temperature detection signal (OSY) (OSR).
A reference voltage buffer (31') is provided for this purpose.

Furthermore, photodiodes for color temperature detection (13) (14)
and the buffer (29) (30), and between the monitor photodiode 0jPD) and the buffer (28),
Further, capacitors and switching transistors are provided in front of the buffers (31) and (31'), respectively, and the details of these capacitors and transistors will be explained with reference to the specific circuit configuration of the photoelectric conversion section (15) shown in FIG. I will add this in the explanation. Data output control section (
16) is composed of a signal processing timing generation section and a transfer lock generation section, and generates a transfer lock (φ1
)(φ2), it also generates a shift gate pulse (SH) to the shift gate (25). It also provides the analog processing section (18) with a signal useful for creating a timing signal for switching the sampling signal and the signal output from the photoelectric conversion element (12) to the outside.

The integration time control section (17) monitors the signal (AGCOS) given from the monitoring photodiode (MPD) of the photoelectric conversion section (15) through the buffer (28), and controls the output of the pass gate 1-(22) according to the monitoring result. , the storage section (23), and the storage section clear gate (24), respectively, by appropriately outputting control signals (BG) (S↑) (STICG) to control the integration time. During the monitoring, the integral time control section (17) controls the monitor signal (AGCO
S) is compensated for in the dark using a monitor output compensation signal (AGC005) given from a buffer (31). The integral time control section (17) communicates signals with the system controller via the Mari i10 control section (20), among which an integral completion signal (TINT) is given to the system controller. Furthermore, this integral time control section (17) controls a command signal (S
Integration is forcibly completed at t(M), but in order to correct the accompanying insufficient integral output at the analog processing stage, an automatic gain control signal (AGC) is generated according to the integral value and the analog It also provides the processing section (18).

The basic functions of the analog processing section (18) are the signal (O3) from the shift register (26) and the output signal (OS) from the color temperature detection photodiodes (13) and (14).
Y) It performs various analog processing such as removing noise components from (OSR), dark output signal compensation, and automatic gain control. Incidentally, as will be described in detail later, this analog processing section (18) also has a configuration for performing reference voltage clamping in order to match the output signal with the dynamic range of the A/D conversion section of the system controller.

110 control section (20) includes a signal processing timing generation section (16B) and an integral time control circuit (16B) shown in FIG.
17b) refers to the human output buffers distributed in the transfer lock generation unit (16A). In Figure 6, i
10 The external device connected to the control section (20) is connected to the terminal (T
, ) to (T6) and (r++)(r+z), (T
+) (Tz) is an input that receives a mode signal (MDI) (MIh>) that selectively specifies integration start mode, low brightness integral mode, high brightness integral mode, and data dump mode that provides integral output to the system controller. Terminal (T3) is the input terminal for the integration clear signal (IC5) related to the start of integration,
(T4) forces the integration to end and shifts the register (
26) a data request terminal for requesting data from the
(T,) is a terminal for outputting an A/D conversion start signal (ADT) to the outside (system controller) in the data dump mode, and (T6) is an input terminal for a basic tarlock (CP). Furthermore, (T11) is the integration completion signal (TINT)
(T, □) is a group of terminals that output automatic gain control data (AGC). Further, the terminals (T, ) (re) shown at positions apart from the I10 control unit (20) are an input terminal for voltage 1 (Vcc) and a ground terminal, respectively. Further, (T,) is an analog signal output terminal, and (T+.) is an input terminal for a reference voltage (Vref).

Next, the specific configuration of each part of the photoelectric conversion element (12) will be described in detail. First, the entire photoelectric conversion section (15) is configured as shown in FIG. 7, and the portion including main elements such as photodiodes and shift registers will be explained using FIGS. 8 to 13. . As shown in FIG. 8, the photodiode array section (21) has a plurality of pixel photodiodes (PD) and monitor photodiodes (MPD) arranged therebetween, which are alternately arranged. One longitudinal end of each pixel photodiode is open, while the other end is coupled to the source of a first MO8 transistor (TRI) forming a barrier gate (22).

The drain of this MOS transistor (TRI) is coupled to the next stage storage section (23), and the gate is coupled to a barrier gate signal supply terminal (32). Although the storage section (23) is shielded from light by an aluminum film and is not irradiated with light, so-called dark charges are generated. The output end of the storage section (23) is connected to the source of the second nO8 transistor (TR2) forming the storage section clear gate (24) and the shift gate (25).
) is coupled to the source of the third MOS transistor (TR3) forming the second MO3) transistor (
The drain of TRz) is coupled to a power supply terminal (T, ) to which electric current fi (Vcc) is applied, and the gate is connected to a storage section clear gate signal supply terminal (33). On the other hand, the third
The drain of the M0S transistor (TR3) is coupled to the segment (26a) constituting the shift register (26), and the gate is coupled to the shift gate signal supply terminal (34).

The monitor photodiodes (MPDs) are connected to each other by photodiodes at the upper end of the figure, so the monitor output is the total output of the plurality of connected monitor photodiodes (MPDs).

By combining a plurality of monitoring photodiodes in this manner, a subject forest monitoring photodiode device having a wide field of view can be realized.

The physical structure of the photodiode array section (21) is schematically illustrated in FIG. 9, which shows a cross section taken along the line A-A' in FIG.
A channel stopper made of P is applied to the upper n-type region (37) to separate the wall region (36), the implanted n-type region (37), and the pixel photodiode (PD) and monitor photodiode (MPD). (38) and a P4 film (39) provided on the surface to suppress the surface depletion layer in order to suppress the dark output of each photodiode. A positive potential is applied to the substrate 35) from the outside, and a ground potential is applied to the intermediate P wall region (36). Note that the n-type region (37) is formed by phosphorus implantation, and the P-wall region (36) is formed by boron diffusion.

By the way, the charge accumulated in the pixel photodiode (PD) mentioned above is transferred to the accumulation section (23) through the barrier gate (22).
) to the pixel photodiode (P
It is known that the length of D) is approximately proportional to the square of 1). On the other hand, as a focus detection device, the total area of each pixel photodiode (PD) is increased by increasing the length 1) so that it can operate even for subjects with considerably low brightness, and the amount of generated charge is increased. This is desirable. In this case, increasing the width of the pixel photodiode (PD) is not preferable because it deteriorates the accuracy of the focus detection device. In order to satisfy these contradictory demands, the present inventors developed the above-mentioned P° film (
It was considered to vary the depth of the n-type region (37) immediately below 39) along the longitudinal direction. That is, as shown in FIG. 10(c), which is a cross-section in the direction indicated by the dotted line (40) in the planar configuration diagram of FIG. 10(a), the structure of the main part (portion near the surface) is shown. Regarding the creation of the n-type region under (39),
The amount of phosphorus ion implanted in the longitudinal direction (horizontal direction in Figure 10)
n −81 region (37a) by changing along
and an n region (37b). In this way, the same figure (
As shown in b), the potential of the pixel photodiode (PD) gradually decreases toward the barrier gate (22), making it easier for the charge to move to the left (towards the barrier gate). This means that the time required to transfer the charge accumulated in the pixel photodiode (PD) is reduced. Therefore, it is possible to solve the problem of increasing the length (1) of the pixel photodiode (PD) in the longitudinal direction to increase the amount of charge generated by the photodiode and quickly transporting the generated charge toward the storage section. In FIG. 10, (41), (42), (43), and (44) are the electrodes of the barrier gate (22), the storage section (23), the shift gate (25), and the shift register (26), respectively. Aluminum material is usually used to form these electrodes. (45) is an insulating film formed by 5ift or the like.

Next, the structure of the entire photoelectric conversion section will be explained with reference to FIG.

The pixel photodiode (PD), monitor photodiode (MPD), and barrier gate (22
), storage section (23), storage section clear game) (24),
A large number of cascade combinations of shift gates (25) and shift registers (26) are arranged in the horizontal direction, and for example, there are 128 segments in the shift register (26). However, as seen at the right end of the array, the pixel photodiode (PD), monitor photodiode (MP
D) The number of segments of the barrier gate (22), storage section (23), storage section clear gate (24), and shift gate (25) is five fewer than that of the shift register (26) on the right end side. Conversely, the shift register (26
) is formed five more segments on the right end side, and this is due to the following reason.

A capacitor (C) receives the output of the shift register (26).
8) is formed integrally with the shift register (26), and specifically, as shown in the conventional example of FIG. P-type head area (
47) is formed by the junction capacitance generated between the two. However, distributed capacitance (C') also occurs between the light-shielding aluminum film (49) coated on the surface via the insulating film (48) and the n'' region 46).This undesired distributed capacitance (
As shown in FIG. 11(c), C') is connected in parallel to the original capacitor (C+) formed of a junction capacitance, increasing the output capacitance and resulting in a decrease in photosensitivity. Moreover, the light shielding aluminum film (49) and n
The distribution volume ff1 (C”) occurring between
is undesirable because it has a lot of variation and causes variation in photosensitivity from product to product. Therefore, as shown in FIG. 11(b), the aluminum film (49) located in the output stage portion is
is deleted (50). In this case, the distributed capacitance (C') is almost eliminated 1, the output capacitor (C+) is hardly affected, and the photosensitivity increases.

On the other hand, the removed portion is shielded from light by a field mask (9) shown in FIG. That is, the junction capacitance portion as the capacitor (C3) is covered with a field mask (9).
) is placed away from the window. This is not limited to the capacitor (C7) provided at the output stage of the shift register (26), but also the aluminum film on the top of the capacitors (C2) to (C8) provided at each output stage. ing.

Figure 12 shows this configuration as a schematic shape of the photoelectric conversion section (15) seen from the field mask side, and (51) is connected to the photodiode array (21) and color temperature detection photodiodes (13) and (14). (52)
reveals the projection of the window of the field mask (9). The condensers (C1) to (C8) are arranged at a position away from the projected image of the window, and therefore at a position not exposed to light. Here, the opening areas of the capacitors (C5) to (C8) are set equal to each other. With this configuration, the output voltages of the capacitors (C2) to (Cb) can be made equal for the same output from the light receiving elements of the same size. Of these capacitors (C1) to (C4), only the capacitor (C,) is located further away from the shift register segment corresponding to the light receiving part, so a segment is required to connect them. The segments are the first to fifth segments shown in FIG. Therefore, these five segments merely function as photo-charge transfer paths. Since the capacitors (C2) to (C6) directly input the output of the light receiving section, they do not require the above-mentioned extra segments. Transfer lock (φ1) (φ2) when the transistor (0,) is turned off instantaneously by the output signal (OSRST) of the shift register (26)
is applied to the capacitor (C5) by the buffer (
27).

In FIG. 7, of the pixel photodiodes (PD) and the monitor photodiodes (MPD), five on the right end and three on the left end are shielded from light by an aluminum film. These light-shielded photodiodes generate a dark charge that is used, for example, for dark correction of the output of the pixel photodiode. The photodiode array (21) is assigned one part as a reference part (M.) and the other part as a reference part (gate).

For example, there are 40 reference parts (M.) and 5 reference parts (Ml).
It includes a combination of 0 pixel photodiodes and a monitor photodiode. However, structurally speaking, the standard part (M.

) and the reference part (Ml), and they are distinguished by software processing in the system controller, which will be described later.

Regarding the unnecessary parts between the standard part (M) and the reference part (Ml), only the shift register (26) is left, and other pixel photodiodes, monitor photodiodes, barrier gates, storage parts, and storage parts are added. The clear gate and shift gate have been deleted from the drawing. This deleted part (
Shown as S). Each segment (26a) of the shift register corresponding to the deleted portion (S) has a pitch that is smaller than that of other portions in order to reduce the number of transfer locks required to transfer all pixel outputs and shorten the total charge transfer time. It is shaped to become larger.

The monitor photodiode (MPD) is in the reference section (M.)
and the reference part (M,) are connected to each other so that only those located in the reference part (M,) are used, and those located in other parts are not used. However, the unused monitor photodiode (MPD) is also connected to the power supply terminal (T) as shown in Figure 13.
, ) for stabilization. This is because if it is electrically floating, it will receive induction from other pixel photodiodes or cause induction to other pixels, eventually affecting other pixel photodiodes. The output of the monitor photodiode is connected to the capacitor (C2).
It is held here and output as a monitor signal (AGCO3) via a buffer (28). In order to remove power supply fluctuations and temperature-dependent components of this monitor signal (AGCO5), a transistor (Q,) having the same configuration as the initialization transistor (Q2) of the capacitor (Cz) is used.
The output from the capacitor (C8) initialized by (
AGCDOS) is prepared at the same time. This capacitor (
A photodiode (DI) of approximately the same size as the monitor photodiode (MPD), which is shielded from light by an aluminum film, is connected to C3) as shown. Transistors (02) and (03) are turned on simultaneously during the application period of the integral clear gate signal (ICG).

Next, a pair of color temperature detection photodiodes (13) (1
4) are respectively arranged in the standard part (M.) and the reference part (MO) as shown in the figure, and these two photodiodes (1.
3) The output of (14) is the integral clear gate signal (ICG
), the capacitors (C4) (C8) are initialized by transistors (Q6) (Q?) that are turned on by
) (mouth, ), the yellow temperature detection signal (OS
Y) is output as a red temperature detection signal (OSR). These color temperature detection photodiodes (13) (1
4) A color filter (not shown) is provided on the surface. Here, the output buffer following the shift register (26), the output buffer for the red temperature detection signal, and the output buffer for the yellow temperature detection signal are formed identically, and the pixel photodiode (PD) and the color temperature detection photodiode (1
3) By setting the magnitudes to be approximately the same as (14), the output voltages of the yellow temperature detection signal (OSY) and red temperature detection signal (OSR) can be set to the reference part (M) and the reference part (
A1) is output as the product of the average output of the pixel photodiode and the transmittance of the color filter. Therefore, the second red temperature detection signal (OSR) and yellow temperature detection signal (OSY)
has approximately the same dynamic as the output voltage of the pixel photodiode (PD), and can be used as a processing circuit for the pixel signal (O3) by time-divisionally processing in the analog processing section at the subsequent stage. Furthermore, since the size of the color temperature detection photodiodes (13) and (14) is the same as the size of the light-shielded pixel photodiode (OPD), the difference between the output voltage of the light-shielded pixel photodiode (OPD) must be taken. It is also possible to compensate for dark output. In addition, Fig. 7 shows the color temperature detection signal (OSY) (O
Output (PDDO) to remove power supply noise etc. of SR)
3) A capacitor (Ch) for generating the voltage and a switching transistor (Q, ) are also provided.

In Fig. 7, color temperature detection photodiodes (13) (1
4) output signal (OSY) (OSR) is connected to a separate transistor (port 4) (O5) and capacitor (C4) (C
5), buffers (29), (30), etc., but it is also possible to take out using the output system of the pixel output (O3) without installing a separate output system like this. It is.

FIG. 13 shows an embodiment based on this viewpoint, in which any one of the three light-shielding pixel photodiodes (OPDs) arranged on the left side of FIG.
), and the output signal of the red temperature detection photodiode (14) is sent to the shift register (26) using the barrier gate, storage section, and shift gate sequentially coupled thereto. This output signal is transferred from the shift register (26) to the capacitor (C1
) and further output via a buffer (27). FIG. 13 shows the red temperature detection photodiode (14) corresponding to the reference part (Ml) as described above, and one end of the second light-shielded pixel photodiode (OPD) from the left end that is shielded with an aluminum film is connected to the other end. The reference part (M) is formed longer than the pixel photodiode and is connected to the output end of the red temperature detection photodiode (14).
The output end of the yellow temperature detecting photodiode (13) corresponding to the yellow temperature detecting photodiode (13) is similarly formed long and connected to any one of the five light-shielding pixel photodiodes (OPD) on the right end side in FIG.

Next, FIG. 14 shows the photoelectric conversion section (15) as one block, and also shows other parts of the photoelectric conversion element (12) in detail, and also shows the system controller (
53) and its peripheral circuits.

The system controller (53) is formed by a one-chip microcomputer, and includes the photoelectric conversion element (1).
A ^/D converter (54) that converts the analog signal (Vout) from 2) into a digital signal, and a lens data output unit (6I) containing the ROM of the photographing lens (interchangeable lens), which outputs different digital signals for each lens. R inputs data such as focus amount, lens extension type conversion coefficient (KL), color temperature defocus amount (dFt), etc. in advance, and stores digital data from the A/D converter (54) one by one.
A memory part (55) formed of AM, and the memory part (55)
a focus detection section (55) that detects the focus based on the output of the
6), a correction calculation unit (57) that calculates a correction amount from the detected focus data and lens data, etc., and sends a signal for driving the lens to a lens drive circuit (63) based on the correction amount. In addition, to monitor whether the integral value at the lens drive control section (58) that receives data on the movement status of the lens from the motor encoder section (64) and the photoelectric conversion section (15) reaches a predetermined value in a predetermined time. A timer circuit (59) for measuring time and a photoelectric conversion element (12)
) and the sensor control unit (6o
). In addition, (65) is the lens drive motor, (
62) is a display circuit controlled by the system controller (53). The photoelectric conversion element (12) and the system controller (53) are formed separately with one chip each, so that the image sensing system is composed of two chips in total.

The integral time control section (17) in FIG. 6 includes a brightness determination circuit and an integral time control circuit, and in FIG. 14, this brightness control circuit (17a) and the integral time control circuit (1
7b) is shown separately. Further, the signal processing timing generation section (16B) shown in FIG. 14 is included in the data output control section (16) shown in FIG.

The I10 control section (20) in FIG. 6 is distributed into the signal processing timing generation section (16B), the integral time control circuit (17b), and the transfer lock generation section (16A) in FIG. 14. The system controller (53) first provides a basic clock (CP) to the photoelectric conversion element (12). This basic clock (CP) is used by the transfer lock generation unit (1
6A) and an integral time control circuit (17b), respectively. The system controller (53) also sends mode signals (MD+) (MJ) to the photoelectric conversion element (12).
give. The mode signal is composed of 2 bits, and there are 4 modes: initialization mode, low brightness integral mode, high brightness integral mode, and data dump mode for the photoelectric conversion element (12).
It can represent two modes and is transmitted using two lines.

In the initialization mode, the transfer lock generation section (1
6A) to the photoelectric conversion unit (15) is a transfer lock (φ1
) (φ2) is supplied at a high frequency, and the charge that was unnecessarily accumulated in the shift register (26) before the transfer lock is supplied is discharged to the capacitor (C8) on the output side of the shift register (26). The charge discharged to this capacitor (C1) is transferred to the reset signal (OSR) by the transistor (Ql) in Fig. 7.
When turned on by ST), it is discharged to the power supply (Vcc). In addition, in the initialization mode, the analog processing section (18)
is also initialized.

Next, the system controller (53) first instructs the low brightness integration mode and supplies an integration clear signal (ICS) shown in FIG. 16 to the integration time control circuit (17b). The integral time control circuit (17b) uses this integral clear signal (ICS5) manually.
), the integral clear gate signal (IcG), the barrier gate signal (BG), and the storage section clear gate signal (ST
ICG) is generated and applied to a predetermined portion of the photoelectric conversion unit (15) shown in FIG. Integral clear gate signal (
rcG) is the monitor output signal (AGCO3), monitor output compensation signal (AGCDO3), color temperature detection output signal (
O3R) (OSY), color temperature detection compensation signal (PDDO
3), respectively, and on the other hand, the barrier gate signal (B
G) and the storage section clear gate signal (STICG) initialize the pixel photodiode (PD) and the storage section (23).

When the integral clear signal (ICS) disappears, the integral clear gate signal (ICG), barrier gate signal (BG),
The storage unit clear gate signal (STrcG) also disappears.

As a result, the transistor (QZ) (Q3) is turned off, and the capacitor (C2), which was initially charged to the power supply voltage (Vcc), becomes the monitor photodiode (MPD).
The voltage begins to drop in proportion to the charge generated by the capacitor (
C3) slightly drops its voltage in response to a small amount of charge generated by the shielded photodiode (D,). Also, (PDS
) is given to the transistors (Qa) (Qs), and the capacitors (C4) (C5) also change from the initial power supply voltage (Vcc) to the color temperature detection photodiode (
13) The voltage is lowered according to the amount of charge generated in (14). On the other hand, the barrier gate (22) and the storage section clear gate (24) are turned off, and as a result, the pixel photodiode (PD) starts generating and accumulating photocharges in response to the irradiation light, and the light-shielding photodiode (MPD) starts generating and accumulating photocharges. The dark output charge starts to accumulate. Furthermore, the storage section 23
), the dark output charge generated by itself is accumulated.

As can be seen from FIG. 16(a), for the integral clear signal (IC3), the above-mentioned (BG) (STrCG)
(ICG) have the same pulse width. Therefore,(
The pulse width of the ICS) is determined by the pulse width of the pixel photodiode (PD) to transfer all charges previously accumulated (that is, before initialization) to the barrier gate (22), the accumulation section (23), and the accumulation section clear gate (24). The limit is on the time required to drain the voltage through the capacitor to the power supply (Vcc). Specifically, the pulse width is selected to be 50 μs to 100 μs or more.

The integration operation of the photoelectric conversion unit (15) does not need to be performed forever, but rather must be completed at some point. This is because once the integral value reaches a predetermined level, there is no need to continue integrating any more.Also, if it takes a long time for the integral value to reach a predetermined level, the time required for the integral value to reach the predetermined level may vary from pressing the shutter button until the release is possible. This is because, since the time required for the integration becomes extremely long, it is better to complete the integration midway through and correct the shortfall in the integrated value at the signal processing stage.

The brightness determination circuit (17a) determines the integration state from the monitor output signal (AGCO5) of the monitor photodiode (MPD) and the monitor output correction signal (AGCDOS), and when it reaches a predetermined value, it The integration time control circuit (VFLG) generates an instruction signal (VFLG) to instruct
17b), and also outputs a gain control signal (AGC) corresponding to the shortfall in the integral value. Its gain control signal (A
GC) is supplied to an AGC subtraction circuit (71).

The AGC subtraction circuit (71) receives the pixel output signal (O
3) and the gain of the color temperature detection output signal (OSR) (O3Y). The AGC subtraction circuit (71) also has a function of performing dark output compensation of the pixel output signal (O3), as will be described later. AGC data is sent to the system controller (
53). This is to enable the system controller (53) to determine whether or not it is necessary to emit auxiliary light (not shown) based on the GC data. The brightness determination circuit (
The specific structure of 17a) is shown in FIG. In FIG. 15, the block indicated by the dotted line (17a) is the brightness determination circuit, and the other dotted line blocks are the AGC subtraction circuit (71).
In the brightness determination circuit (17a), the resistance value of the monitor output compensation signal (AGCDOS) is 1 times, 2 times, 4 times,
Operational amplifier (AI) (At) (AI) (A4
) is applied to the positive input (+) of the At this time, a constant current (I) flows through each resistor due to the constant current source (B), so the voltage drop due to the resistor is 1, 2, and 4 times, respectively.
The relationship is twofold, eightfold. Operational amplifiers (A1) to (A4)
The negative input terminal (-) of the monitor output signal (8G
COS) is supplied, and the output is (8GCO5) and (AG
However, as shown in Figure 7, capacitors (C2) and (C3), transistors (O2) and (Q, ), and buffers (28) and (31
) are designed identically, so both signals (A
GCOS) and (AGCDOS) are at the same potential immediately after applying the integral clear gate signal (ICG), and of these, the monitor output signal (AGCOS) is connected to the monitor photodiode (MP
It decreases with the generation of photocharge at D), while the monitor output compensation signal (AGCDOS) remains unchanged and always maintains the initial potential of the monitor output signal. Therefore, by taking the difference between these signals, it is possible to monitor the amount of accumulated charge (integral value). Moreover, by taking the difference between the two signals, fluctuations in the power supply voltage can be canceled, and furthermore, if the dark output increases due to temperature rise, the light-shielding photodiode (Dl) will respond to it.
The monitor output compensation signal (AGCDOS) includes the temperature fluctuation of the dark output, and the voltage difference between the two signals becomes a correct monitor information signal from which the influence of temperature has been removed. When it is considered that the integral value at the pixel photodiode (PD) has reached a predetermined value, the monitor output signal (AG) from the monitor photodiode (MPD) is
COS) drops by ■×8R from the initial potential, so an instruction signal (VFLG) is generated from the operational amplifier (A4). This instruction signal (VFLG) is applied to the integral time control circuit (17
b). The integration time control circuit (17b) receives an instruction signal (VFLG) or a forced integration completion signal (S)I.
When either of M) is received, the photoelectric conversion unit (15) is made to perform an integration completion operation, and a latch signal (LCK) is sent.
This latch signal (LCK) is sent to the D flip-flops (FFI) to (FF
Since the data terminals (D) of the D flip-flops (FFI) to (FF3), which are supplied to the clock terminal (CP) of 3), are connected to the operational amplifiers (8,) to (A3) in the previous stage, respectively, It becomes a latch state depending on the value of the monitor output signal (AGCOS).

Each D flip-flop (FFI) (FF2) (FF
3) is connected to the AND gate (N+) (Ni) as shown in the figure, and as a result, the brightness determination circuit (17a
) output paths (72), (73), (74), and (75) will output gain control signals (AGC) corresponding to correction amounts of 1x, 2x, 4x, and 8x. . By the way,
Under conditions where the indication signal (VFLG) is output within a predetermined time period managed by the system controller (53), (AGC) occurs on the output path (72).

However, within the predetermined time, the instruction signal (VFLG
) does not occur, the integration is forcibly completed as described later, so the output path (72) (73
) (74) A GC signal will be generated in one of (75).

An explanation of the low luminance integration mode will be added using the time chart of FIG. 16(a). The integration operation starts in the photoelectric conversion unit (15) from the time when the integration clear signal (IC3) disappears, and after a while, when the monitor output signal (AGCOS) drops to a level corresponding to a predetermined integral value, the instruction signal (
VFLG) is generated from the brightness determination circuit (17a).

In response to this, the integration time control circuit (17b) generates a storage section clear gate signal (STICG) to open the storage section clear gate (24) and remove the small amount of dark charge that was unnecessarily accumulated in the storage section (23). is discharged to the power supply (Vcc) side. Subsequently, the accumulation section clear gate (24) is closed by the disappearance of this accumulation section clear gate signal. After this, the integral time control circuit (17b) immediately switches on the barrier gate signal (B
G) is generated to open the pariah gate (22) and transfer the accumulated charge of the pixel photodiode (PD) to the accumulation section (23). It takes about 50~50 seconds from the generation of the instruction signal (VFLG) until the transfer operation to the storage section (23) is completed.
A time (1) of 100 as is required. After the charges accumulated in each pixel photodiode (PD) are transferred to the accumulation section (23) in this way, the integration time control circuit (1
7b) provides an integration completion signal (TINT) to the system controller (53). In this example, (TINT
) indicates the completion of the integration.

This integration completion signal (TINT) is accepted as an interrupt signal in the system controller (53), and even while the system controller (53) is performing other processing, the processing is not important and therefore interrupts are disabled. Unless processing is required, recognition processing of the integration completion signal (TINT) is immediately performed. Further, if the other processing is an interrupt prohibition processing, the integration completion signal (TINT) is processed at the time when that processing is completed. Based on this integration completion signal (74NT), the system controller (53) sets the address etc. for storing image information data in the memory section (55), and then sets the address etc. for the photoelectric conversion element (12).
A shift pulse generation signal (SIIM) is supplied to the transfer lock generation section (16A) inside. As a result, the transfer lock generation section (16A) generates a shift pulse (SH), and applies this shift pulse (SH) to the shift gate (25) of the photoelectric conversion section (15) to transfer the shift pulse (SH) to the storage section (23). Transferring the charges accumulated to the appropriate integration level to the shift register (26) is carried out. Thereafter, the system controller (53) immediately sends the mode signal (MD
I) Give a data dump mode signal as (MIh) to the photoelectric conversion element (12) to set the photoelectric conversion element (12) to the data dump mode. In addition, in the above, the system controller (53) receives the integration completion signal (TINT
) after reception of the photoelectric conversion unit (
15), the pixel photodiode (PD) and storage section (23
) is cut off due to the non-conductivity of the barrier gate (22) due to the disappearance of the barrier gate signal (BG), the charge accumulated in the pixel photodiode (PD) during the above 101113 period is accumulated in the accumulation section (23). has no effect on the desired charge, and the 10m5
In the meantime, a signal (
Since ST) is set to a low level (details will be described later), the dark charge generated in the storage section (23) itself and added to the desired charge is extremely small and does not pose a problem. In FIG. 16(a), the shift pulse generation signal (SH
M) and the shift pulse (S) which is approximately synchronized with the (S)IM)
The slight delay in the generation of SH) indicates that the processing of the integration completion signal (TINT) in the system controller (53) is delayed.

The integration time control circuit (17b) receives a barrier gate signal (
The color temperature detection gate signal (P
DS) also occurs. This color temperature detection gate signal (PD
S) indicates that during the period corresponding to the integral clear gate signal (ICG), the color temperature detection photodiode (13)
(14) The unnecessary accumulated charge is removed by a capacitor (c
a) Color temperature detection photodiodes (13) (14) and capacitors (C4) (C%) to discharge to (Cs)
), the switching transistor (C4) (Qs) is turned on, and even after the integral clear gate signal (ICG) disappears, it remains high level and the transistor (+14) (C
5) is turned on, and charges generated in the color temperature detection photodiodes (13) and (14) are accumulated in the respective capacitors (C4) and (C2). Then, the instruction signal (
From the generation of VFLG), the storage section clear gate signal (STI
After the generation of the barrier gate signal (CG), the color temperature detection gate signal (PDS) falls at the fall of the barrier gate signal (BG), turning off the transistor (IIJ) (11%). As a result, each color temperature detection photodiode (13)
(14) Said capacitor (C4) of the charge generated in
The integration operation at (Cs) is completed, and the potential at the time of completion is the color temperature detection output signal (OSR) until the start of the next integration.
(O3Y).

The above explanation is about the low-luminance integration mode when the subject is relatively bright, but the integration completion operation etc. are slightly different in the low-luminance integration mode when the subject is extremely dark. A time chart of each signal at this time is shown in FIG. 16(b). After starting the above-mentioned integration, the system controller (53)
While waiting for reception of the integration completion signal (TINT), the timer circuit (59) is used to measure the integration time. Then, the integration continues even after 100m5 has passed after the start of the integration,
If the integration completion signal (TINT) is not received, the system controller (53) sends a shift pulse generation signal (SH) to force the photoelectric conversion element (12) to complete the integration.
M) is given. This shift pulse generation signal (St(M)
The integral time control circuit (
17b) provides the above-mentioned storage section clear gate signal (STICG) to the photoelectric conversion section (15) to clear the storage section (23).
) After discharging unnecessary charges, the barrier gate signal (BG)
is given to transfer the accumulated charge of the pixel photodiode (PD) to the accumulation section (23). This completes the integration. still,
At this time, the potential level of the storage section should be raised (
The reason why the signal (ST) is not set to low level is because this storage section has almost no storage time. The charges in each accumulation section (23) are subsequently transferred to the shift register (
26) and are sequentially transferred to the capacitor (C1) by the subsequently sent transfer locks (φI) (φ2). In this way, when the integration is forced to complete based on a command from the system controller, the charge is not accumulated to the appropriate integration level, so the output level is small, which may cause a decrease in the S/N ratio or cause the system The dynamic range of the A/D converter (54) of the controller (53) may become inappropriate. Therefore, in such a case, it is desirable to perform gain correction in the analog processing section (18).

The brightness determination circuit (17a) described earlier in FIG. 15 determines the amount of gain correction, and the output path (72 ) (7
3) Either (74) or (75) is selected (set to high level). The selected state is held until the next integration is completed and the monitor output signal is processed.

This concludes the explanation of the integration operation in the low-brightness integration mode. However, if integration is started in the low-brightness integration mode and the integration completion signal (TINT) is detected before 1ms, there will be many excessive integral components in the low-brightness integration mode. As a result, the analog processing and A/D conversion processing of the pixel output signal become saturated, so the system controller (53) switches the mode signal (MD, ) (ADz) to the high-luminance integration mode.

Next, the integration operation in this high brightness integration mode is shown in Figure 17 (
This will be explained with reference to the time chart of a).

First, the system controller (53) generates an integral clear signal (ICS) as in the low brightness integral mode.

This pulse width is chosen to be the same as in the low brightness integration mode.

Upon receiving this integral clear signal (IC3), the integral time control circuit (17b) sends an integral clear gate signal (ICG), an accumulation section clear gate signal (STrCG), and a barrier gate signal ( BG) is generated. Next, as the integration clear signal (ICS) disappears, integration starts as in the low-luminance integration mode.
Since this time is a high-intensity integration, the barrier gate signal (BG) is output from the integration time-based in circuit (17b) as a high-level signal from the start to the end of the integration, as shown in FIG. 17(a). This means that the pixel photodiode (PD
) and the accumulation section (23) is kept in the ON state while integration is performed, and the charge generated in the pixel photodiode is accumulated in the accumulation section (23) from the beginning. Furthermore, during this integration, the storage section clear gate (24)
is off. Integration starts in this way, and the monitor output signal (AGCOS) is changed to the monitor output compensation signal (8GCDOS) corresponding to its initial potential as in the low-luminance integration mode.
) Predetermined from the level! 1Vth (”=I X8R)
At the point when the brightness has decreased by
supplied to The integral time control circuit (17b) receives this instruction signal (VFLG) and outputs a barrier gate signal (BG
) is set to low level, and the barrier gate (22), which had been on until that point, is turned off. This stops the charge flow from the pixel photodiode (PD) to the storage section (23), and also stops the system controller (
53) and sends an integration completion signal (TINT) to the terminal. In this way, in the high-brightness integration mode, it is not necessary to transfer charge from the pixel photodiode (PD) to the storage section (23), which was seen in the low-brightness integration mode, but simply to transfer the charge from the barrier gate (22).
) from the on state to the off state can complete the integration completion operation, so the instruction signal (VFLJ
) can be completed without delay as shown in FIG. 17(a). On the other hand, in the low luminance integration mode, a time delay (t) of 50 to 100 μs (see FIG. 16(a)) occurs as described above. Then, when the terminal (22) turns off, the signal (ST)
is set to low level to raise the potential of the storage section and reduce the generation of dark charges. The charge integrated to the appropriate integration level accumulated in the accumulation section (23) with a high potential in this way is inputted to the shift pulse generation signal (S)IM) from the system controller (53) as in the low-luminance integration mode. and shift pulse (Sl+) and transfer lock (φI)
(φ2) is shifted to the shift register (26) under the control of the transfer lock generating unit (16A) and sequentially transferred to the output capacitor (C3) of the shift register (26). The signal (ST) becomes high level in synchronization with the disappearance of the shift pulse (SR), thereby returning the charge in the storage section to its original state. The color temperature detection gate signal (PDS) that controls the integration of the output of the color temperature detection photodiodes (13) and (14) is output as a signal having the same value as the barrier gate signal (BG). ) falls at the falling edge of the pixel photodiode (P
D) Color temperature detection output signal (OSR) at the time of completion of integration
Hold the output of (O3Y).

Incidentally, a case where the brightness of the subject is extremely low in the high brightness integration mode is shown in the time chart of FIG. 17(b). In this case, since the integration completion signal is not generated within the predetermined time measured by the timer circuit of the system controller (53), the system controller side (TIN
(S11M) occurs before the reception of T), and the integration operation is completed. The operation for completing the integral operation is shown in Fig. 17(a).
is the same as

In the above, the integration operation of the photoelectric conversion unit (15) has been explained in the low-intensity integration mode and the high-intensity integration mode, respectively. Gate (22), storage section (23), shift gate (25), shift register (
26) schematically shows the physical operation.

Also, in these figures, the pixel photodiode (PD)
Other parts are indicated by symbols of applied signals. Furthermore, (OG
) shows an outgate attached to the end of the pixel photodiode (PD), and if necessary, for example, as shown in FIGS. If this is the case, this aratogame) (
Unnecessary charges can be discharged through OG). 1st
FIG. 9 shows the low-brightness integration mode, and FIG. 20 shows the high-brightness integration mode.

In FIG. 19, (a) is during integration. (b) shows an operation in which the charge in the storage section (23) is discharged to the power supply (Vcc) through the storage section clear gate (24) before transferring the charge in the pixel photodiode (PD) as the integration completion operation (i). There is. (c) shows the operation of transferring the charge of the pixel photodiode to the storage section (23) as the integration completion operation (ii). (d) shows the state at the time of completion of the integration, where the potential control signal (ST) of the storage section is changed from high level to low level to raise the potential level of the storage section.
This is due to the following reason. In a state where the charge from the pixel photodiode (PD) is held, the storage section (23) has a deep potential, but dark charge is likely to occur in the storage section itself (this changes the amount of stored charge, so the potential should be made shallow). This is to suppress the generation of dark charge in the storage section itself.This point is the same in the high-brightness integration mode shown in Fig. 20. Fig. 19(e) shows the initialization, that is, the integration Indicates clearing operation.

In high-intensity integration mode, Fig. 20(a) shows that during integration, (
b) shows the time when the integration is completed, and (c) shows the charge transfer to the shift register. Even in this case, the integral clearing operation is performed as shown in FIG. 19(e).

Next, regarding the analog processing section (18) shown in FIG.
This will be explained with reference to the time charts of FIGS. 16 to 18. As shown in FIG. 7, the first to fifth segments from the right of the shift register (26) do not have corresponding pixel photodiodes. Therefore, the buffer (27)
The first five of the pixel output signals (O8) outputted through are the outputs of the register segment without photodiodes, followed by the outputs of the occluded pixel photodiodes (OPD) from the 6th to 1oth, and then , the output of the pixel photodiode in the reference part (M.), the unnecessary part <
Output of register segment corresponding to S>, reference part (
The output from the photodiode (M1), and finally the output from the light-shielded pixel photodiode (OPD) on the left side. The output waveform is shown in Figure 18 (
OS).

The pixel output signal (O8) is initialized by resetting the capacitor (C+) in FIG.

At that time, a reset pulse (QSR3T) is applied to the gate of the transistor (Ql) to make the transistor (Q, ) conductive and charge the capacitor (C3) to the power supply voltage (Vcc), but the reset pulse (O5R5T) When applied, a signal induced by the clock field through effect of the MOS transistor (Ql) is generated, and this (7
) When the IJ set pulse (OSR3T) ends, the capacitor (C+) is charged to approximately the power supply voltage, indicating the original reference level. However, this reference level fluctuates due to fluctuations in the power supply voltage when the reset pulse (O3R5T) is applied.The shift register (26) transfers one phase at the falling edge of the transfer lock (φl), and the capacitor (C1
) is injected with the accumulated charge of the next pixel photodiode and output. The amount of voltage drop at this time is the pixel output signal Vos (
n). Next, reset pulse (O3RST)
is applied to the transistor (Ql) and the capacitor (C+
) is reset, and at the next transfer lock (φ, ), the pixel output signal V os (n +
1) is obtained, pixel output signals are sequentially outputted in this manner, and the series of pixel output signals outputted in this way is sent to the first sample and hold circuit (66) as shown in FIG. By taking the differential with (VR3) sampled and held at the timing of (RSS/H) in the subtraction circuit (67), the differential output (OSd
ir) is set to a constant value, and the voltage drop from that level becomes the value of the pixel output signal. This power supply noise removal method is generally called a double sampling method.

Next, using the differential output (OSdir) obtained in this way, a second sample and hold circuit (not shown) provided in the same subtraction circuit 67) performs sample and hold. This is to ensure time for keeping the input analog amount constant for the A/D converter (54) in (53). The subtraction circuit (67)
The pixel output signal sampled and held at is shown in Figure 18 (
Vos(n) and Vo
s(n+1), resulting in a signal with a value lowered by Vos(n+2).

Among the pixel output signals (Vos) processed in this way, the seventh to ninth dark pixel output signals are sampled and held in the next third sample and hold circuit (70). The sampling pulse (OBS/H) at this time is the first
As shown in FIG. 6, the pulse is such that the output signal of the light-shielded pixel photodiode (OPD) that is shielded by the seventh to ninth aluminum films of the pixel output signal (Vos) is extracted. Note that the sixth signal is not sampled and therefore is not used for the following reason. That is, as shown in FIG. 7, the sixth pixel output signal is located at the end of the light-shielded pixel photodiode (OPD), so it is easily affected by external noise, and therefore its output is This is because the dark pixel output is not necessarily accurate. Said (OBS/
The 7th to 9th dark pixel outputs sampled and ringed by H) are processed at least until the output of a series of pixel photodiodes ends (1 in the shift register segment).
(until the 28th output is processed).

In this way, the sampled and held dark pixel output (V
os) and the pixel output signal (V os) output from the 11th pixel onwards, the next stage AGC subtraction circuit (71
), it is possible to obtain a pixel output signal (Vosn) based only on the photocharge output with the dark output removed.This subtraction is performed using the AGC subtraction circuit (7) shown in FIG.
1). In Fig. 15, (A,) is the dark pixel output (■.
This is an operational amplifier that takes a differential with the pixel output signal (V os) input from 76). Furthermore, this operational amplifier (A,
) (r,) (r,) (r-) <r-) connected between the output terminal of the The resistor (rs) (r-) (r=) (r-) is connected to the analog switch (S+
) to (S, ) to compensate for the lack of gain in the image output signal (based on the forced stop of integration at low brightness times. The signal that has passed through this AGC subtraction circuit (71) is converted into a photoelectric converter. It is output from the element (12) to the system controller (53). Therefore, the output level is adjusted to the dynamic range (1/3 V ref≦DR≦Vref) of the A/D converter (54) in the system controller (53). However, the AGC subtraction circuit (71) is configured so that the pixel output in the dark is set to (Vref), and when the pixel output (Vos) increases, the output format is set to Vref-Vos. , when a pixel output voltage (V os) equal to the dark output voltage (■.,) input to the terminal (77) is input to the terminal (76), the output of the operational amplifier (A,) is Vref, and the input (
V.

When S) becomes lower than (■.,), the operational amplifier (8,
) output becomes Vref-Vos.

On the other hand, the color temperature detection output signal (OSR) (OSY) is differentiated from the color temperature detection compensation signal (PDDO5) which acts as a reference voltage output in the second and third subtraction circuits (68) and (69).

Furthermore, the above-mentioned AGC is used to compensate the differential output in the dark, to make it an appropriate gain, and to adjust it to the reference voltage.
The subtraction circuit (71) is supplied with the subtraction circuit (71). At this time, the supply timing to the AGC @ calculation circuit (71) is the subtraction circuit (67) (6
8) Analog switch (AND) following (69)
(AND) For (8NS), the control signal (ANS+) (ANSz) (ANS
s).

As a result, in this embodiment, as shown in the pixel output signal (Vos) in FIGS. 16 and 17, during the output of the 10th pixel output signal immediately after the sampling of the dark output, the The yellow temperature detection signal (OSY) is
During the output of the 11th pixel output signal, the red temperature detection signal (OSR) is sent to the AGC subtraction circuit (7
1). In addition, the color temperature detection signal (OSR) (
OSY) is output using a separate output buffer in the photoelectric converter (15), but instead of outputting the same signal as the normal pixel output signal by using a light-shielded pixel photodiode (OPD) as shown in Fig. 13. If output is made through the route, the signals are output from the buffer (27) as the 10th and 12727th elementary output signals. Therefore, these outputs are supplied to the AGCi calculating circuit (71) after noise components are removed by the aforementioned double sampling and dark output is compensated by taking the difference from the dark output sampling value. In this case, the second and third subtraction circuits (68) (69
) and analog switches (AND) (ANz) (AN
3) becomes unnecessary.

This concludes the explanation of the analog processing section (18), and next the temperature detection section (19) will be explained. Among the autofocus detection mechanisms shown in Fig. 2, for example, the lens holder (9)
acrylic material part and re-imaging lens (4a) (4b)
The substrate (5) etc. that hold the holder expand depending on the temperature, causing slight changes in the dimensions of a predetermined portion.

This causes autofocus errors due to temperature.

From this point of view, a temperature detection section (19) is provided to electrically perform temperature compensation;
) is a resistance (
p+) (Rg) are connected in series, and the midpoint of the connection is connected to the plus input terminal (+) of the operational amplifier (A6).

Connect the negative input terminal (-) and output terminal directly. Here, the resistance (R1) has a temperature coefficient βRt"5000ppm
ion implanted resistance, (R2) is the temperature coefficient βR2=50
It is a 0 pp- polysilicon resistor, and the resistance value at 25°C is 10 KΩ for both (R,) (R1). In FIG. 21, the power supply voltage vcc=13v, the reference voltage Vr
The output characteristics of the temperature detection section when ef is −5ν are expressed as
Shown in Figure 2. The detection output is expressed by the voltage across the resistor (R+).

In the time charts of FIGS. 16 and 17, AG
The pixel output signal (V
os), up to the 9th output is the photoelectric conversion element (1
2) There is no need to give it to the system controller (53) as an output signal.
The signal to be supplied to is the yellow temperature detection signal (OSY) located at the 10th position. Therefore, up to the ninth pixel output signal, the temperature detection signal (vy□) is sent to the system controller (53) through the same output line.
give to For this reason, analog switches (8N4) (AN,) are provided in front of the connection point (A) between the AGC subtraction circuit (71) and the temperature detection circuit (19), and these analog switches (AN4) (ANS ) from the signal processing timing generator (20a), respectively.
Gate signal (ANS4) shown in Figure (and Figure 17)
(ANSs) is provided.

Next, the specific configuration of the transfer lock generating section (16A) is shown in FIGS. 26(a) and 26(b). Of these, the second
Figure 6 (a) shows the part that forms the shift pulse (SH),
Figure 26(b) shows transfer locks (φ1) (φ2), (OSRST) (RSS/)I) (O5S/H
) (ADS) etc. are generated. Figure 26 (a
>, (16a) is the system controller (53
) is the first frequency divider that divides the basic clock (CP) from CP, and its divided output is (SHM) (ICS) (TIN
(QDO) (QD
I) (QD2) is generated. These outputs are shown in Figure 26 (
Decoded by the decoder section (16d) of b) and passed through the circuit following the decoder section (16d) (φ, ) (φ2)
(OSRST) etc. are created.

FIG. 27 shows a specific example of the signal processing timing generation section (20a), in which (φ+) (s++) (rcS) is input, (ANS+) to (^N5s) and (OBS/H) are input.
(ADT) is generated. (ADT) is a control signal that triggers A/D conversion of the system controller (53).

Next, the system controller (53) will be explained.

A/D converter (5,) in the system controller (53,)
4) is formed as shown in FIG.
8), the pixel output signal (Vout) from the photoelectric conversion element (12) described above is input, and the reference voltage (Vout) is input to the terminal 79).
ref), and (ADT) is input to the terminal (80). And from terminal (0+) (0□)...(On) to A/
A D-converted output is derived.

The system controller (53) detects the color temperature of the subject by calculating the ratio R of the digital values (■.sa) (Vosv) of the color temperature detection signal (OSR) (OSY) thus A/D converted, Correction is performed according to the color temperature, and the flowchart is shown in the 24th section.
As shown in the figure. Figure 24 shows the overall flow of focus detection operation.
25(a), (b), (c), and (d) particularly show the flow of color temperature correction.

First, an outline of the focus detection operation will be explained using FIG. 24. When the focus detection operation is started by pressing the shutter button on the camera, the system controller (53) resets the flag and inputs lens data including color temperature correction data from the lens data output section (61). The system controller (53) sets an integration mode (ST) in which the storage unit performs storage (signal MDI - low level, MD2 = high level), and sets the maximum integration time to 20 m5ec. Then, an integration clear signal (ICS) is generated to start integration. At this time, the integration of the color temperature detection photodiodes (13) and (14) is also performed at the same time. Then, it waits for the integration end signal (TINT) indicating the end of integration to become low level, and when it becomes low level, it is determined that the integration has ended, and the time required for this is determined. If the time is within 1m5ec, the next integration mode is a mode that performs integration to the storage section (ST mode)
Set the high brightness flag (HLF) to
If m5ec~20m5ec, the next integration mode is
Assuming the same as this time, the integration end signal (T
If INT) does not become low level, a low luminance flag (LLF) is set so that the next integration mode will be a mode for integrating into the light receiving section (PD mode). In either case, a signal (SHM) is sent to indicate the completion of the integration operation.
is output and waits for the integration end signal (TINT) to become low level. This allows 20m5 in low brightness integration mode.
Only when the integration is not completed within ec, the system waits for the integration signal to become low level; otherwise, it is already low level. Note that pixel data is sent to the shift register by a shift pulse in terms of hardware. Then, when the integration end signal (TINT) is at a low level, the system controller (53) sets the data input mode and inputs the AGC data of the digital signal. Next, temperature data is input, AID conversion for this analog data is started by the pulse of the signal (ADT), and the A/D converter waits for this A/D conversion to complete.
When the conversion is completed, input the temperature data (SBT),
Store in a predetermined register. As described above, this temperature data input is at the timing of the ninth data input of the shift register (26) (see the time chart) (no data is input to the shift register).

Next, the system controller (53) sets the number of pixels of the captured data, including the number of color temperature detection photodiodes and the number of pixel output signals, and sets the input analog signal (V
os) is performed, data is stored in the internal memory each time an interrupt signal is generated due to the termination, and this is repeated for the set number of times. Thus, the reference part (M.) as well as the reference part (
The digital signals corresponding to the respective images of M,) are used to calculate the image interval of both parts (M.)CM+) using a correlation calculation as disclosed by the applicant in JP-A No. 60-247211. Calculate the defocus df. After calculating df by the distance measurement calculation, temperature correction is also performed based on the output from the temperature detection unit (19), where β is the temperature correction coefficient of the camera itself, SBT is the temperature information, and SBT is 2
This is basic temperature information at 5°C. This temperature-corrected defocus dro is set to take the true value when the light source of the subject is sunlight.

This defocus amount dfO is set to a predetermined value Tdf (=2 to 3
If the color temperature correction value is larger than the body (body), the color temperature correction value is not that large (approximately 100 to 200μ or less), so the correction value itself does not have a large effect, and the lens is driven and remeasured. When defocus is detected below a predetermined value Tdf, the color temperature correction value Δdf
will be added. In this way, the color temperature correction value Δdf
is added, a focus judgment is performed, and if it is within the focus range, an in-focus display is performed, and if it is determined that it is out of focus, a detection diagonal is added by adding the color temperature correction value Δdf to the defocus amount df. Lens driving is started in accordance with the focus 1ldf, and after setting the integration mode, the routine from the step of starting integration upon generation of ICS is repeated.

Here, we will add an explanation of the internal operation of color temperature correction.

As mentioned earlier, the lens color temperature correction data dFL is input at the top of the flowchart.

This value is, for example, the amount of chromatic aberration of each lens with respect to 550nn+ (daylight) when an 800 nm monochromatic light source is stored in the memory within the lens. On the other hand, the output signal (OSR) of the color temperature detection photodiode is integrally controlled simultaneously with each pixel photodiode and subjected to analog processing.
(O5Y) is digitized by the A/D converter (54) of the system controller (53) and (Vos++) (Vo
sy) in the memory (55).

As shown in FIG. 25(a), the system controller (53) calculates the ratio R of (■.s* > (Vosv)
Calculate. When this ratio R is a predetermined value, for example 1.8 or more, it is determined that the incident light from the subject has many long wavelength components and has a low color temperature, and a predetermined coefficient k (0≦) is added to dFL of the color temperature correction data. , ≦1), and the color temperature correction amount Δd
Let it be f. Conversely, when the ratio R is 1.2 or less, it is determined that the incident light from the subject has many short wavelength components and the color temperature is low, and a predetermined coefficient -kt (0≦
is multiplied by 2≦1), and the color temperature correction amount is set to Δdf. When the ratio R is between 1.2 and 1.8, the incident light from the subject is integrated by the light component close to daylight,
Color temperature correction is not necessary, and the color temperature correction amount Δdf is
Let f=O. In this way, depending on the light from the subject,
The determined color temperature correction amount Δdf is added to the defocus amount df obtained by distance measurement calculation to calculate the true detected defocus amount df.

Color temperature correction is performed in this way, but another method is to include the necessity of color temperature correction as lens data depending on the type of lens, and perform color temperature correction as shown in the flowchart in FIG. 25(b). By first determining whether or not to perform color temperature correction, if color temperature correction is not necessary, speed can be increased without going through an extra flow. Also, since each correction value is determined discretely as shown in (a) and (b),
The second flow of determining the correction value continuously for the value of R is
This is shown in Figure 5(c). Here, R may show infinity for an object having a single wavelength component of a short wavelength, whereas the chromatic aberration of an optical system naturally has a finite value as long as it is visible light. To add restrictions for that, R
In the case of ≧2.5, the value of R is limited to 2.5, and the correction amount is adjusted to the above-mentioned lens color temperature defocus correction amount and a predetermined coefficient, and from the ratio R to 1 at the reference daylight color. .5
Determined by multiplying by the value obtained by subtracting .

Next, when performing discretely as shown in FIG. 25(a),
If it is possible to set the value of the correction amount Δdf for each lens, the correction amount Δdf will be R≧1 as shown in FIG. 25(d).
．． When R≦1.2, df, and when R≦1.2, dft, and so on, the values given to each lens are df+ and dfz.

In any case, in the embodiments described above, the color temperature of long wavelength components and short wavelength components within visible light is detected and corrected, so that the accuracy of focus detection is improved.

Furthermore, according to the present invention, the first gate means provided between the photoelectric conversion light receiving means and the storage means and the second gate means provided between the storage means and the shift register means are controlled in two different ways. A first and a second control means are provided and the first and second control means are provided so as to be able to perform the first and second control operations in the same manner. Since the second control means can be selectively switched and activated, image signals can be extracted at appropriate levels over a wide range from low to high brightness and almost unaffected by dark output. It is extremely effective.

[Brief explanation of the drawing]

All figures relate to the present invention, and FIG. 1 is a principle diagram of an optical system when the image sensing system of the present invention is used for focus detection of a camera. FIG. 2 is an exploded perspective view of the sensor module, and FIG. 3 is a schematic configuration diagram of the photoelectric conversion element. FIGS. 4 and 5 are characteristic diagrams for explaining the spectral sensitivity of the color temperature detection photodiode. The sixth figure is a block circuit diagram of the photoelectric conversion element, and FIG. 7 is a diagram showing the circuit configuration of the photoelectric conversion section. FIG. 8 is an enlarged view of a part of FIG. 7, and FIG. 9 is a sectional view taken along the line AA' in FIG. FIG. 10 is a structural diagram showing the physical structure of a pixel photodiode. FIG. 11 is a diagram showing the structure of the output section of the shift register in FIG. 7 in comparison with a conventional example. 12th
The figure is a diagram showing a schematic shape of a photoelectric conversion unit viewed from the light incident direction. FIG. 13 is a diagram of another embodiment corresponding to FIG. 8. FIG. 14 is a block circuit diagram showing the overall configuration of the image sensing system, and FIG. 15 is a specific circuit diagram of a portion thereof. 16 and 17 are time charts of each partial signal of FIG. 14 in the low-luminance integration mode and the high-luminance integration mode, respectively. Figure 18 is the first
5 is a diagram of various signal waveforms for explaining the operation of the analog processing section in FIG. 4. FIG. FIGS. 19 and 20 are diagrams showing the physical operation of the photoelectric conversion section in the low-brightness integration mode and the high-brightness integration mode, respectively. FIG. 21 is a specific circuit diagram of the temperature detection section, and FIG. 22 is its output characteristic diagram. FIG. 23 is a circuit diagram of the A/D conversion section of the system controller. FIG. 24 is a flowchart showing the operation of the system controller, and FIG. 25 is a flowchart showing a portion thereof in detail. FIG. 26 is a specific circuit diagram of the transfer lock generation section, and FIG. 27 is a specific circuit diagram of the signal processing timing generation section. (16)--data output control section, (17)--integration time control section, (21)--photodiode array section (light receiving means for photoelectric conversion), (22)--barrier gate first gate means) + (23)・-accumulation section, (
24) - Accumulation section clear gate (discharge means), (25)
, -・Shift gate (second gate means) + (2
6)---Shift register.

Claims (4)

[Claims] (1) Light receiving means for photoelectric conversion consisting of a plurality of light receiving element arrays that output electrical signals according to the intensity of incident light; Storage means having a plurality of storage sections that respectively accumulate electrical signals from the light receiving means for photoelectric conversion; A first gate means consisting of a plurality of gates connected between the light receiving means for photoelectric conversion and the storage means; receiving electrical signals accumulated in the storage means and sequentially outputting them at timings according to a predetermined clock signal; shift register means; second gate means comprising a plurality of gates connected between the accumulation means and the shift register means; disabling the first gate means and the second gate means in response to a predetermined accumulation start signal; As an operation, an electric signal is held by the light receiving means for photoelectric conversion, and in response to a predetermined accumulation end signal, the first gate means is first actuated in a pulse manner to remove the electric signal held in the light receiving means for photoelectric conversion. a first control means for accumulating the electric signal in the accumulating means, and then operating the second gate means in a pulse manner to transfer the electric signal accumulated in the accumulating means to the shift register means; in response to a predetermined accumulation start signal; the first gate means is activated, the second gate means is deactivated, the electric signal outputted by the photoelectric conversion light receiving means is stored in the storage means, and the first gate is activated in response to a predetermined accumulation end signal. the first gate means and the second gate means such that the second gate means is momentarily activated in a pulsed manner to transfer the electric signal stored in the storage means to the shift register means; An image sensing system comprising: a second control means for controlling the first control means; a switching means for selectively operating the first control means and the second control means; (2) The switching means includes means for measuring the brightness of light incident on the light receiving means for photoelectric conversion, and actuating either the first control means or the second control means according to the measured brightness. The image sensing system according to claim 1, further comprising a selection means for selecting the image sensing system. (3) The selection means includes a determining means for determining whether the measured brightness is above or below a predetermined brightness, and when the brightness is above the predetermined brightness, operates the second control means and reduces the predetermined brightness. 3. The image sensing system according to claim 2, further comprising an operation determining means for activating the first control means when the temperature is lower than 0. (4) The selection means includes a first determination means for determining whether the measured brightness is above or below a predetermined first brightness; 2
a second discrimination means for discriminating whether the brightness is above or below the first brightness; and when the brightness measured while the second control means is operating becomes below the first brightness, the second control means replaces the first brightness. actuating the first control means, and actuating the second control means in place of the first control means when the brightness measured while the first control means is in operation exceeds a second brightness; The image sensing system according to claim 2, further comprising a switching means.