JP3312660B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device.

[0002]

2. Description of the Related Art A photoelectric conversion device is used for various purposes in various devices. In this specification, a photoelectric conversion device for focus detection used in a single-lens reflex autofocus camera or the like is taken as an example. I will explain it. Such a photoelectric conversion device is disclosed in, for example, JP-A-2-1696.

[0003]

However, the autofocus (AF) system using the photoelectric conversion device has a problem that it is difficult to autofocus a low-contrast subject. In order to solve such a problem it may be to obtain a high contrast as possible amplifies the photoelectric conversion output, when amplifying, the conventional photoelectric conversion device amplifies the basis of the output voltage when dark However, although it is effective for low-brightness, low-contrast output, efficient amplification cannot be performed, for example, for high-brightness, low-contrast output.

The present invention has been made in view of the above points, and an object of the present invention is to provide a photoelectric conversion device capable of efficiently increasing contrast regardless of whether the luminance is low or high. Aim.

[0005]

In order to achieve the above object, a photoelectric conversion device having a first configuration has a mode in which an output from a photoelectric conversion unit including a plurality of pixels is amplified with reference to a dark output voltage. A mode in which amplification is performed based on an average voltage of the effective pixel output, and an output from the photoelectric conversion unit.
At low contrast,
In this case, increase based on the average voltage of the effective pixel output.
If you select a mode to increase the contrast and the contrast is high,
Includes a control <br/> control means for selecting a mode for amplifying the reference output voltage when dark, the.

Further, the photoelectric conversion device of the second configuration has a plurality of
A first mode for amplifying the output from the photoelectric conversion means with reference to a dark output voltage, and a second mode for amplifying the output from the average pixel value of the effective pixel output. An amplifier, an integrating means for integrating the output charge of the photoelectric conversion means, and when the integrated value of the integrating means or the integrated value of the monitoring integrating means reaches a predetermined level, the integration of the integrating means is terminated and within a predetermined time. First control means for forcibly terminating the integration by the integrator when the predetermined level is not reached; and the amplifier in the second mode when the integration is terminated by the integral value reaching the predetermined level. And the second control means for operating the amplifier in the first mode when the integration is forcibly terminated. The photoelectric conversion device according to the third configuration includes a mode in which an output from a photoelectric conversion unit including a plurality of pixels is amplified based on a dark output voltage, and a mode in which the output is amplified based on an average voltage of effective pixel outputs. Detecting a maximum value and a minimum value of the accumulated charge amount of each pixel in the photoelectric conversion means, and amplifying the output based on a dark output voltage when a difference between the maximum value and the minimum value is larger than a predetermined level. Control means for selecting an amplification mode based on an average voltage of the effective pixel output when the difference between the maximum value and the minimum value is equal to or less than a predetermined level.

[0007]

According to the first and third configurations, in the mode in which amplification is performed based on the dark output voltage, the amplification is performed so that the level of the entire photoelectric conversion output is higher than the dark output voltage. Further, in the mode for amplifying average specific voltage (average voltage or a voltage corresponding thereto) to a reference, is amplified so that the amplitude of the photoelectric conversion output waveform increases. The above two modes are switched based on the output from the photoelectric conversion means.

[0008] According to the second configuration, the first mode for amplifying the output voltage when the dark output from the photoelectric conversion unit as a reference is selected when the luminance of the photoelectric conversion output is low, the effective
The second mode for amplifying based on the average voltage of the pixel output is selected when the luminance is relatively high.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a photoelectric conversion device embodying the present invention will be described with reference to the drawings. First, FIG.
A configuration in which a set of photoelectric conversion element arrays and their outputs are selected by a selection unit 5 under the control of a control unit 6 is shown. Next, FIGS. 2 and 3 showing a focus detection optical system in a single-lens reflex camera with an automatic focus detection function using a photoelectric conversion device will be described. In the camera body of the single-lens reflex camera, a photographic lens 11 is provided on an optical axis 10, a main mirror 12 is provided at an angle of 45 degrees upward behind the photographic lens 11, and a film exposure surface 13 is provided behind the main mirror 12. The luminous flux for photography that has passed through the photographic lens 11 is reflected upward by the main mirror 12, is imaged by the reticle, and is guided to the finder optical system via the pentaprism.

[0010] At least a part of the main mirror 12 is formed as a half mirror. The main mirror 12 is located between the half mirror portion of the main mirror 12 and the film exposure surface 13.
The sub-mirror 14 having a rotating shaft pivotally mounted on the back of the
The focus detection light flux provided at 5 degrees and transmitted through the half mirror portion of the main mirror 12 is reflected downward by the sub mirror 14,
The light is guided to the focus detection device 15 arranged below the mirror box of the camera body.

At the time of photographing, the main mirror 12 and the sub mirror 1
Reference numeral 4 denotes a photographic light beam that has been rotated upward and retracted from the optical axis 10 and passed through the photographic lens 11,
To give an imagewise exposure to the film exposure surface 13.

The focus detecting device 15 is provided with an AF sensor 17 having three photoelectric conversion element rows 16a, 16b, 16c. Photoelectric conversion element rows 16a to 16c
Among them, one photoelectric conversion element row 16a is arranged at a horizontal position including the optical axis 10, and two photoelectric conversion element rows 16b,
16c is disposed at a vertical position not including the optical axis 10 on both sides of the photoelectric conversion element row 16a. Photoelectric conversion element row 1
6b and 16c are approximately 90 to the photoelectric conversion element row 16a.
It is oriented in degrees.

A separator lens plate 18 is provided in front of the AF sensor 17.
Separator lenses 18a to 18c corresponding to the photoelectric conversion element rows 16a to 16c are integrally formed. An aperture mask 19 is provided immediately before the separator lens plate 18, and the aperture mask 19 has the separator lenses 18a to 18a-1.
Openings 19a to 19c corresponding to 8c are formed.

A reflection mirror 20 is provided opposite to the aperture mask 19 and the sub-mirror 14. This reflection mirror 2
Numeral 0 denotes the focus detection light flux reflected downward by the sub mirror 14 through the aperture mask openings 19a to 19c and the separator lenses 18a to 18c.
Is to lead to. Reflection mirror 20 and secondary mirror 1
4, condenser lenses 21a to 21c facing the aperture mask openings 19a to 19c are provided. On the upper surfaces of the condenser lenses 21a to 21c, a focus detection light beam is provided by a photoelectric conversion element array having different positions and directions. 16a-16c
22a to 22c for separating so as to correspond to
Is provided.

The principle of focus detection is a TTL phase difference detection method, and a reference portion light beam a (shown by a broken line in FIG. 3) passing through mutually different areas 11a and 11b and 11c and 11d on the exit pupil plane of the photographing lens 11. And the reference portion light beam b (shown by a solid line in FIG. 3) are received by the reference portion A and the reference portion B in each of the photoelectric conversion element rows 16a to 16c, and the light distribution pattern of the image is converted into an electric signal. These correlations are obtained by a correlator (not shown) to perform automatic focus detection, and the drive mechanism moves the photographing lens 11 back and forth based on a shift signal from the correlator, thereby performing automatic focus adjustment. is there.

In the focus detection optical system shown in FIG. 2, since the photoelectric conversion element rows 16b and 16c at the vertical position are provided in addition to the photoelectric conversion element row 16a at the horizontal position, focus detection in the horizontal direction and the vertical direction is performed. Simultaneous detection enabled detection of the focus of a horizontal line or the like.

FIG. 4 shows a focus detection area and a display in a viewfinder with respect to a photographing screen of a camera using the AF sensor 17. In this example, three areas IS1, IS2,
IS3 (hereinafter, the first island, the second island,
Focus detection can be performed on the subject of the third island. Rectangular frame A indicated by a broken line in the figure
F is displayed to indicate to the photographer the area where focus detection is being performed. The display Lb shown outside the photographing screen S indicates the focus detection state, and is turned on when focusing.

FIG. 5 shows a CCD used in this focus detection device.
(Hereinafter referred to as a CCD including the light receiving unit, the storage unit, and the transfer unit). Each island IS in FIG.
A reference part and a reference part are provided for each of IS1, IS2, and IS3.
The IS3 is provided with monitoring light receiving elements MPD1, MPD2, and MPD3 for controlling the integration time to the accumulation section of the CCD, respectively. Each island IS1, IS2, IS3
Are (34, 44) in the first island IS1 and the number of pixels (X, Y) in the reference
(44, 52), and in the third island IS3, (3
4, 44). These are all formed on a one-chip semiconductor substrate.

In the focus detecting device according to the present embodiment, the reference portion of the CCD of the above-mentioned three islands IS1 to IS3 is divided into a plurality of blocks, and the reference portion of the divided block is compared with all of the reference portions. Perform focus detection. In each island, among the focus detection results obtained in the divided blocks, the data of the last pin is used as the focus detection data of each island, and the focus detection data of the camera is calculated based on the focus detection data of each island.

The range to be divided and the defocus range of the divided block will be described with reference to FIGS. FIG. 6 is an enlarged view of the focus detection area on the photographing screen S shown in FIG. Each of the focus detection islands IS1, IS2, and IS3 is a region of the reference portion shown in FIG. In FIG. 6, the numerical value shown for each island indicates the number of difference data obtained by taking the difference of every third pixel of the CCD shown in FIG. Good, but the above values are different at this time.) Therefore, the number (X, Y) of difference data between the reference portion and the reference portion in each island is equal to the first island IS1
Then, (30, 40), in the second island IS2, (4
0,48), in the third island IS3 (30,40)
Becomes

Each island is divided into two parts. The first island IS1 divides the data into two parts, and sets (1 to 20) and (11 to 30) based on the difference data at the upper end. And Second Island I
In S2, the data is divided into three, and (1-2)
0), (11 to 30), and (21 to 40), and the third block BL3, the fourth block BL4, and the fifth block BL5, respectively. Further, the sum (1 to 35) of adjacent data of data obtained by taking a difference every seven pixels for all pixels is defined as a sixth block BL6, the front part (1 to 25) of this data string is a seventh block BL7, and the rear part ( 11 to 35) as an eighth block BL8. In the third island IS3, (1-20) and (11-30) are obtained from the difference data at the upper end,
A ninth block BL9 and a tenth block BL10, respectively.

In the focus detection by the phase difference detection method, when the image interval when the images of the reference portion and the reference portion match each other is larger than a predetermined interval, the rear focus is set.
Focusing is performed at predetermined intervals. Therefore, the defocus range of the divided block is such that a block farther from the optical center of each island covers the rear focus side. A specific description will be given based on FIG. 7 showing the state after the difference data has been obtained.

FIG. 7 shows a reference portion and a reference portion of the second island IS2.
Consider a defocus range of 4. At this time, the images to be focused are the 15th to 34th images (15 ′ to 34 ′) from the left end and the image (1) of the fourth block BL4 in the reference portion.
1 to 30). From this, when the image coincidence is on the left side of the reference portion, the front pin is determined. At this time, the maximum number of shift data of the front pin (hereinafter referred to as shift pitch) is one.
4. When the coincidence of the images is on the right side of the reference portion, the rear focus is set. At this time, the maximum pitch of the rear focus shift is 14.

The same applies to the defocus range divided into blocks in each of the other islands. FIG. 8 shows that, in the third block BL3, the front-pin-side shift pitch is 4, the rear-pin-side shift pitch is 24, In the fifth block BL5, the front pin side shift pitch is 24, and the rear pin side shift pitch is 4. Regarding the first island IS1 and the third island IS3, in the blocks BL1 and BL9, the front pin side shift pitch is 5, the rear pin side shift pitch is 15, the block BL2,
In BL10, the front-pin-side shift pitch is 15, and the rear-pin-side shift pitch is 5. In the sixth block BL6, the rear pin and the front pin have four pitches on both sides, and in the seventh block BL7, the rear pin side has four to fourteen pitches. In the eighth block BL8, the pitch is 4 to 14 on the front pin side.

FIG. 9 discloses an AF sensor 17, an AF controller 30, and peripheral circuits as an example in which the photoelectric conversion device is used in a focus detection device of a camera. The AF controller 30 is formed of a one-chip microcomputer, in which an A / D converter 31 for converting an analog signal obtained from the analog signal output line Vout of the AF sensor 17 into a digital signal, a photographing lens (interchangeable lens) ) From the lens data output unit 40 including the ROM, the defocus amount-lens extension amount conversion coefficient KL and the color temperature defocus amount dFL differ for each lens.
And the like, and a memory unit 32 formed of a RAM for storing digital data from the A / D conversion unit 31 one by one, and a focus detection unit for detecting a focus based on an output of the memory unit 32 33 and a correction operation unit 34 for calculating a correction amount from the detected focus data, lens data, and the like.
And a lens drive control unit 35 which receives a signal for driving the lens based on the correction amount to the lens drive circuit 42 and receives data on the state of movement of the lens from the encoder 44, and an integrated value of the AF sensor 17. An AF for transmitting / receiving signals to / from the AF sensor 17 and a timer circuit 36 for monitoring whether or not (“charge accumulation” is also referred to as “integration” below) reaches a predetermined value within a predetermined time. A sensor control unit 37.

Reference numeral 43 denotes a lens driving motor, and reference numeral 41 denotes a display circuit controlled by the AF controller 30. The AF sensor 17 and the AF controller 30
Each one chip is formed separately, so that the AF system is composed of a total of two chips. Vref is the A / D of the AF controller 30
Analog reference voltage of conversion unit 31 and AF sensor 17, V
ccL is a power supply line, and GND is an earth line.

AF sensor 17 and AF controller 30
During the period, MD1, MD2, MD3, ICG, SHM, C
They are connected by eight signal lines of P, ADT, and Vout. Of the eight signal lines described above, MD1, MD2,
MD3 is a signal line for outputting a logic signal from the AF controller 30 to the AF sensor 17, and sets an operation mode of the AF sensor 17. The operation modes of the AF sensor 17 include an initialization mode, a low brightness integration mode, a high brightness integration mode, a data dump mode, a dark output clamp mode, and an average value clamp mode. The logic levels of the signal lines MD1, MD2, and MD3 are provided. The operation mode is set by the combination of. The signal lines ICG and SHM are bidirectional, and serve as output logic lines from the AF sensor 17 to the AF controller 30 in the above-described data dump mode, and output information on the brightness of the subject in each island and the integration completion order.

In other modes, the signal line ICG provides an ICG signal for instructing the AF sensor 17 to start a new integration, and the signal line SHM provides the AF sensor 17 with an SHM signal for supporting a data request and a mode designation. A logic line for supplying a latch signal to the AF sensor 17 from the AF controller 30 is provided. The signal line CP is a line for supplying a basic clock from the AF controller 30 to the AF sensor 17.

The basic clock supplied from the signal line CP is turned on / off inside the AF controller 30.
When the basic clock is turned off, the operation of the AF sensor 17 is temporarily frozen so that the AF controller 30 can control other circuit parts, for example, the lens driving circuit 42 and the like. It is possible. The signal line ADT indicates the completion of the output of one pixel data of the AF sensor 17 in the data dump mode,
An ADT signal for instructing start of A / D conversion is supplied to an A / D converter 31 in the AF controller 30. In another mode, when charge accumulation is performed to an appropriate level in each island of the AF sensor 17, the AF sensor 17 outputs an interrupt signal to the AF controller 30 to indicate the completion of integration.

Finally, the signal line Vout is an analog signal line. After the outputs of the photoelectric conversion element arrays 16a to 16c in the AF sensor 17 are subjected to analog signal processing,
A / D in AF controller 30 from AF sensor 17
It is supplied to the converter 31. This Vout signal corresponds to the aforementioned AD
The data is output for each pixel in synchronization with the T signal, is subjected to A / D conversion, and is taken into the AF controller 30 as subject image information obtained from the AF sensor 17.

Next, a specific configuration of the AF sensor 17 will be described with reference to FIG. In the figure, the photoelectric conversion element row 1 is on the left side.
6a to 16c are connected to the I / O
O part is shown. First, as shown in the above-mentioned display in the finder of FIG.
It is divided into three islands IS1 to IS3 arranged in a character shape, and in principle, each is controlled separately. The detailed configuration of the photoelectric conversion element rows 16a to 16c is shown in FIGS.

Among them, a portion including main components such as the photodiode PD and the shift register SR will be described. As shown in FIG. 11, the photodiode array unit 50
Has a form in which a plurality of pixel photodiodes PD and monitoring photodiodes MPD arranged therebetween are alternately provided. One end of each pixel photodiode PD in the longitudinal direction is coupled to a source of a first MOS transistor TR1 forming a barrier gate. The drain of the MOS transistor TR1 is coupled to the storage section ST of the next stage, and the gate is coupled to a supply line of a BG signal (barrier gate signal).

The storage section ST is shielded from light by an aluminum film and is not irradiated with light, but generates a so-called dark charge. The output terminal of the storage unit ST is connected to the source of the second MOS transistor TR2 forming the integration clear gate ICG and the third MOS transistor T forming the shift gate SH.
R3 is coupled to the source. The drain of second MOS transistor TR2 is coupled to power supply line Vcc,
The gate is coupled to a supply line for an ICG signal (integral clear gate signal). On the other hand, the drain of the third MOS transistor TR3 is coupled to a segment forming the shift register SR, and the gate is coupled to a supply line for an SH signal (shift gate signal).

The monitoring photodiodes MPD are connected to each other on the upper end side in the figure, and thus the monitor output is the total output of the plurality of connected monitoring photodiodes MPD. By combining a plurality of monitoring photodiodes MPD in this manner, a subject luminance monitoring photodiode having a wide field of view can be realized.

The physical structure of the photodiode array unit 50 is schematically shown in FIG. 12 showing a cross section taken along the line CC 'in FIG. 11, and a P-type region 52 formed in a silicon substrate 51 by a diffusion method and an implantation method. A channel stopper 54 made of P ⁺ (a P-type high-concentration impurity diffusion region) provided on the upper N-type region 53 to separate the pixel photodiode PD and the monitoring photodiode MPD from each other; An N.sup. ⁺ Film 55 is provided on the surface to suppress the dark output of each photodiode PD and suppresses the surface depletion layer. A positive potential is externally applied to the silicon substrate 51, and a ground potential is applied to the intermediate P-type region 52. The N-type region 5
3 is formed by phosphorus implantation, and the P-type region 52 is formed by boron diffusion.

The pixel photodiode PD, the monitoring photodiode MPD, the first MOS transistor TR1 for the barrier gate BG, the storage unit ST, the second MOS transistor TR2 for the integration clear gate ICG, and the shift gate SH in FIG. A large number of continuous third MOS transistors TR3 and shift registers SR are arranged in the horizontal direction. For example, there are 128 shift registers SR.

However, as seen at the right end of the array shown in FIG. 13, the pixel photodiode PD, the monitor photodiode MPD, the MOS transistor TR1 for the barrier gate, the storage unit ST, the MOS transistor TR2 for the integration clear gate, and the shift The number of segments of the gate MOS transistor TR3 is smaller than that of the shift register SR by five on the right end side. Conversely, only the number of segments of the shift register SR is increased at the right end. These five segments merely function as a photocharge transfer path.

In FIG. 13, a photodiode P for a pixel is used.
D, the rightmost 5 of the monitoring photodiodes MPD
Each of the light-emitting elements and the leftmost three are shaded by an aluminum film as shown by oblique lines. These light-shielded photodiodes OPD generate, for example, dark charge used for dark correction of the output of the pixel photodiode PD. One portion of the photodiode array portion is assigned as a reference portion A, and the other portion is assigned as a reference portion B. For example, the reference portion A includes 44 pixels and the reference portion B includes 52 pixel photodiodes PD and monitor photodiodes MPD for 52 pixels. However, structurally, there is no distinction between the reference part A and the reference part B, and they are distinguished by software processing in the AF controller 30 described later.

With respect to portions considered unnecessary between the reference portion A and the reference portion B, only the shift register SR is left, and other pixel photodiodes PD, monitor photodiodes MPD, MOS transistors TR1 for barrier gates, Some or all of the accumulation unit ST, the integration clear gate MOS transistor TR2, and the shift gate MOS transistor TR3 are deleted. The pitch of each segment of the shift register SR corresponding to the deleted portion is formed so as to be larger than the pitch of the other portions, and the number of transfer clocks required for transferring all pixel outputs is reduced to reduce the total charge transfer time. I can shorten it.

The monitoring photodiodes MPD are connected to each other so that only those located at the reference portion A (and, if necessary, the reference portion B) are used, and those existing at other portions are not used. However, it is desirable that the unused monitoring photodiode MPD is also connected to the power supply line Vcc and stabilized. If this is electrically floating, it receives guidance from the photodiodes PD for other pixels or causes guidance to the photodiodes PD for other pixels, and eventually affects the photodiodes PD for other pixels. Because.

The output of the monitoring photodiode MPD is applied once to the capacitor C2 via the MOS transistor Q5, and is held there and is retained by the source follower SF2.
Automatic gain control output signal AGC through a buffer comprising
Output as OS. The MOS transistor Q2 is for initializing the capacitor C2. In order to remove the power supply fluctuation and the temperature-dependent component of the automatic gain control output signal AGCOS, the drift output signal DO from the capacitor C1 is initialized by the MOS transistor Q1 having the same configuration as the MOS transistor Q2 for initializing the capacitor C2.
S is generated simultaneously. A photodiode MD for detecting a drift component having substantially the same area as the total area of the monitoring photodiode MPD is connected to the capacitor C1 via the MOS transistor Q4. Photodiode MD
Is shielded from light by an aluminum film. MO for initialization
The S transistors Q1 and Q2 are turned on simultaneously during the application period of the ICG signal (integral clear gate signal).

Here, the charge integration mode of the photoelectric conversion element rows 16a to 16c of the AF sensor 17 will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 14 is a potential distribution diagram of a conventional general one-dimensional photoelectric conversion element array. The photoelectric conversion element for one pixel is an overflow gate O
It has a photodiode PD with G, a barrier gate BG set to a constant potential, and a storage unit ST. First, by applying a voltage to the integration clear gate STICG, the storage unit ST and the photodiode PD for photoelectric conversion are applied.
Discharges the charge accumulated before that to the overflow drain OD, as shown in FIG.

The overflow drain OD is designed in common with the power supply line Vcc. Due to the discharge of the unnecessary charges, the charges remaining in the photodiode PD and the storage section ST are eliminated, and each pixel is initialized. Next, by removing the voltage to the integration clear gate STICG, the potential level of the integration clear gate ICG rises, the outflow of charges from the accumulation unit ST to the overflow drain OD is stopped, and the light intensity incident on the photodiode PD The photocharge generated in response to
As shown in FIG. 4 (b), it flows into the storage section ST via the barrier gate BG and is stored here. This is the charge accumulation operation (integration operation). Here, the storage unit ST
Whether the average value of the charge stored in each pixel reaches an appropriate level for the subsequent processing circuit and the processed operation,
Alternatively, when there is a data request from the AF controller 30, an integration completion operation is performed.

In this integration completion operation, as shown in FIG. 14C, a voltage is applied to the shift gate SH, and the potential level of this gate is lowered, so that light is incident on the photodiode PD and accumulation occurs. The charge accumulated so far in the section ST is injected into the corresponding shift register SR.

Here, the reason why the storage section ST is provided is mainly due to the following reasons. In the AF sensor 17, in order to be usable even in a low luminance range,
A high-sensitivity photodiode PD having a large pixel area is used, and its length LPH generally reaches several 100 μm. On the other hand, the length LST of the storage section ST is generally about 50 μm in accordance with required conditions such as a saturation voltage. here,
Considering the time required to transfer charges to the shift register SR in the integration completion operation, it takes about 3 to 5 μsec to transfer charges from the storage unit ST. This is a value that depends on the moving speed of the charge, and is 2 times the moving distance.
It is known to increase in direct proportion to the power.

Therefore, if charges are stored in the photodiode PD without providing the storage portion ST, the charge transfer time τSH is LPH = 200 μm, LS
Assuming that T = 50 μm, τSH = 5 × (LPH / LST) ² = 80 μsec, and 80 μs even when a voltage is applied to the shift gate SH to start the integration completion operation immediately after the integration starts.
It is necessary to continue that state during ec, and there is a limitation on the minimum integration time. As a result, the dynamic range at the time of high luminance is reduced. From this perspective,
The storage section ST is provided to shorten the charge transfer length at the end of integration, thereby improving the responsiveness of the integration end operation.

When the above-described integration completion operation is completed and the voltage applied to the shift gate SH is removed, the photodiode PD and the photodiode PD are connected between the end of the previous integration completion operation and the end of the current integration completion operation. This means that the charges generated in the storage unit ST have been transferred in parallel to the corresponding shift registers SR.

Thereafter, the charges as the image information are sequentially transferred in the shift register SR in synchronization with the transfer clocks φ1 and φ2 supplied to the shift register SR.
Capacitor C3 serving as voltage conversion means, source follower S
The signal is read out as an analog voltage from the output signal line OS in FIG. 13 via the buffer composed of F3. The MOS transistor Q3 is for initializing the capacitor C3. However, in this integration operation,
The following problems arise.

First, there is a problem of dark output. In this case, even in a state where no light is incident, electric charges corresponding to the potential level are generated in each part by thermal excitation or the like. Therefore, normally, the potential level of the photodiode PD is set high, and the accumulation unit ST
It is necessary to set the potential level of the accumulating unit ST in spite of extremely small dark output.
Generally, the dark output of only the photodiode is several times to several tens of times that of the photodiode PD. For this reason, most of the dark output, which is a noise component, is actually generated in the storage unit ST which is not related to the photoelectric conversion, and the S / N ratio is reduced as compared with the general photodiode PD.

Further, as described above, with the demand for higher sensitivity of photoelectric conversion, a shorter integration time control is required. As described above, the minimum integration time is the shift pulse S
In addition to being limited by the pulse width of H, the generation of the shift pulse SH also limits the transfer relationship of the transfer clocks φ1 and φ2 supplied to the shift register SR.

Therefore, in the present embodiment, in order to reduce the dark output and achieve a higher degree of integration completion,
This is achieved by switching between the two integration modes according to the respective use conditions.

ST Integration Mode (High-Brightness Integration Mode) First, when inputting image information of a high-brightness subject requiring high-speed integration completion, the above-described signal line MD is used.
The ST integration mode shown in FIG. 15 is selected by a combination of the logics of 1, MD2. The integration clear operation and the integration operation shown in FIG.
The operation is performed by the operation as shown and described in (a). ST
In the integration mode, only the integration completion operation is different. In the photoelectric conversion element rows 16a to 16c of this embodiment, the potential of the barrier gate BG disposed between the photodiode PD and the storage section ST is designed to be controllable.

During the integration clear operation and the integration operation shown in FIG. 15A, a predetermined voltage is applied to the barrier gate BG to reduce the potential so as to enable the charge transfer between the photodiode PD and the storage section ST. Set to level. If the average level of the accumulated charge of each pixel has reached an appropriate level in the processing circuit in the subsequent stage, or if a data request has been made from the AF controller 30, the signal applied to the barrier gate that has been applied up to that time By removing the voltage of BG, as shown in FIG. 15B, the potential of the barrier gate BG is raised to a high level to stop the charge transfer between the photodiode PD and the storage unit ST. The integration operation is completed by inhibiting the charge generated by light incident on the PD from flowing into the storage unit ST.

Thereafter, as shown in FIG. 15 (b), the potential of the storage section ST is raised to a high level, so that the charge from the photodiode PD is held in the storage section ST, and the storage section ST is implied. The generation of charges is suppressed so that image information is not damaged by dark charges generated in the storage unit ST. After this state, the AF controller 3
With the generation of the data request signal SHM from 0, FIG.
As shown in (c), a voltage is applied to the shift gate SH, and the potential level of this gate is lowered to transfer charges between the storage unit ST and the shift register SR.

As described above, the data read operation and the integration completion operation are performed separately, and the integration completion operation is realized only by changing the potential of the barrier gate BG from a low level to a high level. Responsiveness is realized.

PD Integration Mode (Low-Brightness Integration Mode) Next, the integration mode of the photodiode PD for a low-brightness subject requiring a reduction in dark output will be described with reference to FIG. In the integration mode of the photodiode PD, charge accumulation (integration) is performed by the photodiode PD having a low dark output, and unnecessary dark output generated in the accumulation unit ST during this integration is discharged through the integration clear gate STICG. In this mode, after sufficient time, the generated charges of only the photodiode PD are transferred from the photodiode PD to the storage unit ST, and then transferred to the shift register SR and sequentially read. In this mode, since the charge transfer speed is limited as described above, it takes about 100 μsec for the integration completion operation, but it is possible to read out image information with an extremely low dark output.

The integration clear operation is performed in exactly the same manner as shown in FIG. Next, at the time of the start of integration, as shown in FIG. 16A, unlike the integration mode shown in FIG. 14 and the ST integration mode shown in FIG. 15, it is located between the photodiode PD and the storage unit ST. The potential of the barrier gate BG is set to a sufficiently high level, and charge is stored not by the storage unit ST but by the photodiode PD.

The charge accumulated in the photodiode PD reaches an appropriate level or the AF controller 30
When the integration completion operation is performed in response to the data request signal SHM from the memory, unnecessary dark output charges generated in the storage unit ST and stored in the storage unit ST are first discharged. This is because the potential of the integration gate STICG is manipulated as shown in FIG. 16B while the potential of the barrier gate BG is maintained at the “High” level, so that unnecessary charges remaining in the accumulation unit ST are reduced. It discharges.

After the unnecessary charges in the storage section ST have been discharged in this way, as shown in FIG.
The potential of the ICG is returned to the original high level, and thereafter, the potential of the barrier gate BG is set to the low level, and charge transfer between the photodiode PD and the storage unit ST is performed (see FIG. 16C). As described above, this charge transfer requires a time of about 100 μsec, and is measured and operated in the AF sensor 17. After the transfer of the charges integrated by the photodiode PD is completed, the potential of the barrier gate BG is returned to a high level again, thereby completing the integration completion operation.

After the completion of the integration completion operation, FIG.
As shown in FIG. 6D, the potential of the accumulation unit ST is set to a high level to suppress the generation of the dark charge, as in the case after the end of the above-described ST integration mode. After waiting in this state, the shift gate SH is operated by the data request signal SHM from the AF controller 30, and the accumulation unit ST is operated.
Are transferred in parallel to the shift register SR, and thereafter, the operation of sequentially reading out as image information is also as described above.

The description of each of the photoelectric conversion element arrays 16a to 16c shown in the block diagram of FIG. 10 has been completed. Next, how these photoelectric conversion element arrays 16a to 16c are controlled in this embodiment will be described. Will be described. As shown in FIG. 10, the monitoring photodiode MP in each of the three photoelectric conversion element rows 16a to 16c.
CCD integration time controllers 171 to 173 are provided for the outputs AGCOS1 to AGCOS3 of D1 to MPD3, respectively. Controlled. Also,
CCD clock generator 174 sets 1 for all islands.
And controls the common transfer clocks φ1 and φ2 of the shift registers SR of all islands and the shift gates SH1 to SH3 of each island.

Hereinafter, the ST integration mode for a high-luminance subject will be described with reference to the time chart of FIG. First, the AF controller 30 sets the signal line MD1 to the “Low” level and sets the signal line MD2 to the “High” level in order to set the high brightness integration mode.
Next, in order for the AF sensor 17 to start integration, the IC
The G signal (integral clear gate signal) is supplied. This ICG signal is sent through the I / O control unit 175 in FIG.
The signals are supplied to the CCD integration time controllers 171 to 173.
The CCD integration time controllers 171 to 173 supply the photoelectric conversion element rows 16a to 16c as STICG signals (ST integration clear gate signals) for a time (about 100 μsec) sufficient for discharging the charges.

During this period, the photoelectric conversion element array 1 of each island
"Hi" is also applied to the barrier gates BG1 to BG3 of 6a to 16c.
gh "level voltage is supplied, and the charges generated in the photodiode PD are all discharged to the overflow drain OD via the barrier gate BG, the storage section ST, and the integration clear gate STICG. During this time (about 100 μs)
After the clocking of c), only the STICG signal goes to the "Low" level, the potential of the ST integration clear gate STICG goes to the high level, and the charge generated in the photodiode PD starts to be stored in the storage section ST. on the other hand,
The outputs AGCOS1 to AGCOS of the monitoring photodiodes MPD1 to MPD3 are generated by the STICG signal.
3 is also started to be integrated. The details will be described below.

FIG. 19 shows a monitoring photodiode MP.
The details of the AGC signal processing circuit 60 for integrating the respective outputs AGCOS1 to AGCOS3 of D1 to MPD3 to obtain the voltage flag signals VFLG1 to VFLG3 are shown, and FIG. 20 is a time chart thereof. The AGC signal processing circuit 60 is provided in each of the CCD integration time controllers 171 to 173. When the ICG signal is input, first, the initialization signal DOSRS of the capacitor C1 for obtaining the drift output signal DOS and the automatic gain control output signal AGCO
Signal AGCRS for initializing capacitor C2 to obtain S
At this time, a signal of "High" level is supplied, and the voltages .DELTA.VDOS and .DELTA.VAGC of the capacitors C1 and C2 are initialized. At the same time, the operating point of the inverting amplification unit 64 is set by the operating point setting pulse φF, the capacitance C6 of the reference output holding unit 65 is initialized by the initialization pulse φS, and the capacitance of the comparison circuit unit 66 is reset by the initialization pulse φFLGRS. Initialization of C7 is performed.

The voltage ΔVDOS of the capacitors C1 and C2
And ΔVAGC are differentially amplified in a differential amplifier 61 formed by combining source followers, and an automatic gain control voltage VAGC = 0.8 × (Δ
VAGC-.DELTA.VDOS) + V0 is obtained. Where V
0 is an offset value. The automatic gain control voltage VAGC obtained from the differential amplifying section 61 and the reference voltage Vr obtained from the reference voltage generating section 62 have the same capacitance C
4, and synthesized by the voltage synthesizing circuit 63 including C5.

A variation component of 0.8 × {(ΔVAGC−ΔVDOS) −Vr} / 2 is obtained in the output voltage VX of the voltage synthesizing circuit 63. AGC for automatic gain control output signal
Assuming OS, ΔVAGC = ΔVDOS + V1-AGC
OS. Here, V1 is an offset value. Thus, VAGC = 0.8 × (−AGCOS) + V2. Here, V2 (= V0 + 0.8 × V1) is also an offset value. Further, a fluctuation component of {0.8 × (−AGCOS) −Vr} / 2 is obtained in the output voltage VX of the voltage synthesis circuit unit 63.

In the initial state, the reference voltage switching pulse φa is "
Since the “High” level and φb to φe are “Low” levels, the reference voltage Vr is the minimum reference voltage Va (= 0.3
75V). The voltage VY = (− 10) × VX obtained by inverting and amplifying the output voltage VX of the voltage synthesizing unit 62 at this time by the inverting amplifier 64 is a voltage flag signal VFLG.
It becomes the inversion threshold level, and this voltage VY
Is held in the capacitor C6 of the reference output holding unit 65 at the rising timing of the initialization pulse φS, and is continuously supplied as the level VYM.

Next, the initialization pulse φF rises, and the charges at this time are held in the capacitors C4 and C5 of the voltage synthesizing circuit section 63 in total. After that, the voltage synthesis circuit unit 6
The level fluctuation of half of each voltage fluctuation in each of the input voltages VAGC and Vr of No. 3 is the level fluctuation of the output voltage VX.

Next, the AF controller 30 sets the pulse φa for obtaining the reference voltage Va (= 0.375 V) and the initialization pulse DOSRS to the “Low” level, and then sets the reference voltage Ve (= 3.375 V). Pulse φe to obtain
Is set to the “High” level, and the fluctuation of the voltage VAGC is (V
In order to start monitoring whether or not only e-Va) has occurred, the initialization pulse φFLGRS is set to the “Low” level, the initialization pulse AGCRS is set to the “Low” level, and the integration of the monitor output is started. The light incident on the monitoring photodiode MPD is photoelectrically converted, and the generated electrons gradually lower the voltage ΔVAGC charged in the capacitor C2 from the initial value Vcc.

The output voltage V of the voltage synthesizing circuit 63 is
The variation of X from the initial value is as follows: {−Va + 0.8 × AGCOS + Ve} / 2, and when the value of this expression becomes 0, the inverting amplifier 64
Becomes the same potential as the initial value VYM, and when VY> VSB ≒ 0.8 × VYM, the comparison circuit 6
The charge stored in the capacitor C7 of the MOS transistor Q
6, the voltage flag signal VFLG is inverted and output as a signal indicating a proper level of integration.

The AGC signal processing circuit 60 is constituted by such a circuit.
In No. 7, by sharing the area of the pixel photodiode PD in each island and sharing the sensitivity of each CCD pixel, and also sharing the total area of the monitoring photodiode MPD in each island,
The sensitivity ratio between the pixel photodiode PD and the monitoring photodiode MPD in each island is made common, whereby the reference voltage generator 62 in the AGC signal processing circuit 60 shown in FIG. In this case, the power consumption can be reduced, and the chip area of the AF sensor 17 can be reduced.

The AGC signal processing circuit 60 not only controls the integration time of the CCD pixel array in each island, but also controls the maximum allowable integration time of the system when the integration is insufficient. Appropriate gains are given according to the monitor signals from the island. The determination of the gain is also a role of the AGC signal processing circuit 60.

When the SHM signal for starting the data reading is supplied from the AF controller 30, the CCD integration time controllers 171 to 173 start forcibly completing the integration operation, and the barrier gates BG1 to BG3 and the storage unit ST1
To ST3, ST integration clear gate STICG1 to STI
The operation of CG3 is started. In the ST integration mode, only the operation of the barrier gates BG1 to BG3 is instantaneous.
In the PD integration mode, after the SHM signal is applied, the ST integration clear gates STICG1 to STICG are used.
3, about 100 by operation of barrier gates BG1 to BG3
After elapse of μsec, the integration completion operation ends. Subsequently, first, a shift pulse SH2 is generated to transfer charges from the storage unit ST of the second island to the shift register SR. At this point, it is necessary to store the gain of each island.

Therefore, following the generation of the shift pulse SH2, the monitoring reference voltage Vr of each island is sequentially switched using the reference voltage switching pulses φe, φd, φc, and φb, thereby inverting the voltage flag signal VFLG. A check is made, and the gain at the time of reading the photoelectric conversion signal of each island is determined and stored according to when the voltage flag signal VFLG is inverted.

When the inversion of the voltage flag signal VFLG has already occurred when Vr = Ve (3.375 V) or when the inversion of the voltage flag signal VFLG has occurred when switching to Vr = Vd (1.875 V), × 1 gain is stored, and Vr = V
If the inversion of the voltage flag signal VFLG occurs at the time of switching from d to Vr = Vc (1.125V), a gain of × 2 is stored and Vr = Vc
If the inversion of the voltage flag signal VFLG occurs at the time of switching from Vr to Vb (0.75 V), a gain of × 4 is stored and Vr = V
If the inversion of the voltage flag signal VFLG does not occur even at the time of switching to b, a gain of × 8 is stored.

In this way, after the gain is determined by the AGC signal processing circuit 60 of each of the first, second, and third islands at the same time and is stored, when the pixel data of each island is read out, the stored gain is set to FIG.
1 is supplied to the amplifier 75 or 76 shown in FIG. As a result, the output of each island is amplified with the most appropriate gain. The gain information of each of these islands is obtained from the ICG and SHM signal lines by the AF
ADT immediately after start of data dump to controller 30
It is output as digital data in synchronization with the signal. still,
FIG. 21 does not show the supply of the gain to the amplifier 75 or 76.

The AGC signal processing circuit 60 as described above
The monitor outputs AGCOS1 to AGCOS are provided in the CCD integration time controllers 171 to 173, respectively.
3 is constantly monitored by the AGC signal processing circuit 60 as to whether or not it has reached the appropriate level, a predetermined level fluctuation has occurred, and the arrival at the appropriate level is detected by any of the CCD integration time controllers 171 to 173. Then, every time,
The voltage flag signals VFL of the islands IS1 to IS3
G1 to VFLG3 are inverted.

In the operation example of FIG. 17, first, the voltage flag signal VFLG2 is inverted in the second island. At this time, the CCD integration time control unit 172 inverts the barrier gate signal BG2, which has output the "High" level signal from the integration clear operation, to "Low" level, and charges inflow between the photodiode PD and the storage unit ST. Is interrupted, and the integration completion operation is performed.
By supplying a pulse signal of "Low" level to the ADT signal which has maintained "gh" level, the completion of integration of one island is notified to the AF controller 30. The AF controller 30 uses the rising edge of the ADT signal as an interrupt signal. By inputting and performing ADT interrupt processing, the completion of integration of one island can be recognized.

In the other islands, that is, in the case of FIG. 17, the first and third islands IS1 and IS3 are independent of the operation of the second island IS2.
The barrier gate signals BG1, BG3 keep the state of "High" level and continue the integration (this operation is limited to the ST integration mode. In the PD integration mode described later, the integration of all islands is stopped simultaneously. I do.)

In the operation example of FIG. 17, the voltage flag signal VFLG1 of the first island is inverted after the second island. In this case as well, as in the case of the second island, a "Low" level pulse is output to the ADT signal, the barrier gate signal BG1 is inverted, the path between the photodiode PD and the storage unit ST is cut off, and integration is completed. Perform the operation. The AF controller 30 recognizes the completion of the integration of the second island at the rise of the ADT signal.

Finally, the voltage flag signal V of the third island
FLG3 is the maximum allowable integration time (20 in the ST integration mode).
msec), the ADT signal is held at the “Low” level and the barrier gate signal BG3
Is set to the “Low” level, the connection between the photodiode PD and the storage unit ST is cut off, and the integration is completed. The AF controller 30 repeatedly detects the ADT signal at a period slightly longer than the pulse width indicating the completion of the first and second integrations, thereby detecting that the “Low” level signal is continuously output. , It can be recognized that the integration of all islands has been completed. At this time, in the storage units of the photoelectric conversion element arrays 16a to 16c of all islands, a charge amount of a level suitable for the subsequent analog signal processing unit 176 is prepared.
The state is held.

Next, the AF controller 30 supplies an SHM signal serving as a data request signal to the AF sensor 17.
The SHM signal is sent to each of the CCD integration time controllers 171 to 173 and the CCD via the I / O controller 175 of FIG.
The clock is supplied to the clock generator 174. As shown in the time charts of FIGS. 17 and 18, when the integration operation is automatically completed by the CCD integration time controllers 171 to 173 in all the islands before the supply of the SHM signal, the CCD
The integration time controllers 171 to 173 do not operate on the SHM signal.

On the other hand, the CCD clock generator 174 initializes the internal counter by the SHM signal, starts counting the input pulse CP from this point, sets the transfer clock φ1 to the “High” level, sets the transfer clock φ
2 is set to the “Low” level, and the shift gate pulse SH2 is supplied first. This shift gate pulse SH2
Is applied, the electric charge held in each storage section ST2 of the second island is transferred to the shift register SR2 of the second island. After the completion of the application of the shift gate pulse SH2, the transfer clocks φ1 and φ2 are restarted.
1, in synchronization with φ2, the CCD shift register SR2
Transfers the photocharge generated in the photoelectric conversion unit of the second island as the output signal OS2.

The CCD clock generation section 174
The number of transfer clocks of D is counted and sent to the analog signal processing unit 176. Further, when an analog signal is output from the CCD dark output pixel which is the 7th to 9th pixels shown in FIG.
In order to clamp this dark output level to the A / D conversion reference voltage Vref, a control signal for level clamping is supplied to the analog signal processing unit 176. The analog signal processing unit 176 will be described later in detail.

The CCD clock generator 174 outputs an ADT signal via the I / O controller 175. The ADT signal is output as a signal indicating switching of one pixel of the CCD data, and the A / D converter 31 of the AF controller 30 starts A / D conversion at the falling edge of the ADT signal.

FIGS. 23 and 24 are time charts showing the operation of the CCD transfer clocks φ1 and φ2 and the signals synchronized therewith. The ADT signal is shown in FIG.
As shown in FIG. 7, the signal is output as a signal synchronized with the CCD transfer clock only when outputting a falling pulse indicating the completion of integration of each island, when outputting digital data using the ICG and SHM signal lines, and when outputting an effective pixel. When an invalid pixel is output, the pixel is masked by the value of the counter in the CCD clock generator 174 and is not output. Therefore, the AF controller 30 can take in the A / D conversion data without determining whether the pixel is an effective pixel or an invalid pixel.

Thus, the pixel signal photoelectrically converted by the second island IS2 is output as the output signal VOS in the order of the reference section and the reference section. This image signal is obtained by an analog signal processing unit 176 to be described later in which the dark output level generated during the integration time of the second island IS2 is clamped to the reference voltage Vref or the output amplified based on the average value. Becomes Next, it is necessary to read the image signal photoelectrically converted by the first island IS1.

Therefore, as shown in FIGS. 23 and 24, the clock .phi.1 at the time of outputting the forty-eighth pixel data of the reference section output in the second island generates the SHI signal at the "High" level phase. This timing is also derived from the value of the counter in the CCD clock generator 174. The reason why the SHI signal is generated at this time is because the idle feed pixel having no pixel exists at the head of the CCD output as shown in FIG. 13, and therefore, the output time of the idle feed pixel is shortened.

When the output of the 52nd pixel data of the reference section in the second island is completed after the generation of the SHI signal, the CCD clock generation section 174 causes the analog signal processing section 176 to control the opening and closing of the analog switch AS2 by the AS2 signal. From the “High” level to the “Low” level, and the AS1 signal from the “Low” level to the “High” level.
The level is switched to the level, and the data of the first island is supplied to the analog signal processing unit 176. After that, similarly to the data output of the second island, the dark output sample-hold is performed, and then the photoelectric conversion output generated during the integration time of the first island from the analog signal Vout has the dark output level of A / A. The output is output in the order of the reference section and the reference section as an output clamped to the D conversion reference voltage Vref or an output amplified based on the average value.

Next, by performing exactly the same processing as when the output is switched from the second island to the first island, the first island is obtained.
The output is switched from the island to the third island.
Performs data output for the island. Thus, the output of the data is completed, and the process proceeds to the next integration.

In the analog signal processing section 176 shown in FIGS. 21 and 22, the output signal VOS is indefinite during the integration time and during the amplification based on the dark output, so that the analog signal processing section 176 is not suitable as an externally supplied signal. Absent. Therefore, during these phases, the CCD clock generator 174 controls the temperature data VTEMP obtained by dividing the A / D conversion reference voltage Vref with resistors having different temperature counts as the output signal Vout. The temperature data VTEMP is supplied from the temperature detector 177 shown in FIG. 10 to the analog signal processor 176.

Next, in the PD integration mode for a low-luminance object, since the integration time is low and the integration time is long, priority is given to the speed of the entire system, and after the maximum integration time (100 msec) has elapsed as shown in FIG. When the first ADT signal is input from the AF sensor 17 to the AF controller 30, the SHM signal is supplied from the AF controller 30 to the AF sensor 17, and all the islands IS1 to IS1
The integration operation in S3 is completed at the same time. Except for this point, substantially the same operation as in the above-described ST integration mode is performed, and therefore, duplicate description will be omitted.

Now, the details of the analog signal processing unit 176 will be described with reference to FIGS. 21 and 22. First, FIG.
In FIG. 10, the output signals OS1, OS2, O of the photoelectric conversion element rows 16a, 16b, 16c shown in FIG.
S3 is stored in the buffer circuit 200 through the terminals 201, 202, and 203, and is selectively supplied to the positive input terminal of the differential amplifier 75 by sequentially turning on analog switches SW1, SW2, and SW3.

Here, the buffer circuit 200 is connected to the capacitors C17, C18, C19 connected between the input terminals 201, 202, 203 and the ground, and the terminals 204, 205, 206 to which the power supply voltage VCC is applied. Terminal 20
Switching transistors 207, 208, and 209 connected between the first, second, and first buffers 202, 211, and 212, respectively. The analog switches SW1, SW2, and SW3 connected to the outputs of the buffers 210, 211, and 212 and the switch transistors 207, 208, and 209 are formed of MOS transistors, though not necessarily limited thereto.

The analog switches SW1, SW2, S
The photoelectric conversion outputs OS1, OS2, and OS which are sequentially and repeatedly output from W3 and given to the differential amplifier 75.
3, the differential amplifier 75 removes the fluctuation of the power supply voltage Vcc. That is, the photoelectric conversion output OS is output as a voltage between both ends of the capacitor C3 as shown in FIG. 13. One end of this capacitor is connected to the power supply voltage VCC via the switching transistor Q3, and the transistor Q3 is turned on at the time of reset. Thus, once the power supply voltage VCC has been reached, the voltage dropped from the power supply voltage VCC in accordance with the amount of charge from the photoelectric conversion element array given via the shift register SR together with the turning off of the transistor Q3 as the photoelectric conversion output OS When the power supply voltage VCC changes as an initial value, the photoelectric conversion output signal OS includes a fluctuation of the power supply voltage VCC.

The differential amplifier 75 is provided mainly for removing the fluctuation of the power supply voltage. In FIG. 21, the transistor Q19 is turned on at the time of reset, and the power supply voltage VCC is stored in the capacitor C16. The voltage is also applied to the negative input terminal of the differential amplifier 75 through the buffer 214 and the resistor 215 at the time of reset. I have. In the differential amplifier 75, the difference between the photoelectric conversion output given to the positive input terminal and the power supply voltage VCC given to the negative input terminal is taken, whereby the power supply voltage VCC component is canceled from the photoelectric conversion output. Therefore, the fluctuation component is also removed.

As described above, the power supply voltage VC
The photoelectric conversion output from which the variation of C has been removed is subjected to dark-time output compensation by the differential amplifier 76 at the next stage. In the dark output compensation, the output of the light-shielded pixel photodiode OPD of FIG. 13 is sampled by the transistor Q18 and the voltage held by the capacitor C15 is applied to the positive input terminal of the amplifier 76, and the photoelectric conversion output is applied to the negative input terminal. This is achieved by:

In this way, the photoelectric conversion output subjected to the dark output compensation is applied from the terminal 216 to the terminal 216 in FIG. 22, and is sampled and held by the sample and hold circuit 217. The sample hold circuit 217 includes a transistor Q17, a capacitor C14, and a buffer 218.

The output of the sample hold circuit 217 is subjected to contrast control by the next contrast control circuit 220. The contrast control circuit 220 increases the contrast by amplifying the photoelectric conversion output with reference to an average level of the photoelectric conversion output when the contrast is low, for example, when the contrast is low. It can be amplified with reference to a predetermined dark reference voltage Vref corresponding to the hour output.

Therefore, a reference voltage serving as a reference level for amplification is applied to the negative input terminal of the amplifier 77. The reference voltage supply circuit 230 for applying the reference voltage includes an average value holding circuit 221 and a dark output reference voltage applying circuit 222. The average value holding circuit 221 further includes first, second, and third islands IS1, First, second, and third average value holding circuits 223, 224, and 22 provided corresponding to IS2 and IS3.
It consists of five. The first average holding circuit 223 includes a switch transistor Q11, a buffer 226, a capacitor C11, and a switch transistor Q12. The second average holding circuit 224 also includes a switch transistor Q13, a buffer 227, and a capacitor C12.
And a switch transistor Q14.
Similarly, the average value holding circuit 225 includes a switch transistor Q15, a buffer 228, a capacitor C13, and a switch transistor Q16.

On the other hand, the dark output reference voltage providing circuit 222 outputs a dark output reference voltage Vre which is equivalent to the dark output voltage.
It comprises a terminal 229 to which f is applied and a transistor Q10. The transistors Q10, Q12, Q14,
Only one of the transistors Q16 is turned on to output the voltage on the input side of the switch transistor. The output voltage of this switch transistor is supplied to the amplifier 7 via the buffer 231.
7 is added.

In this embodiment, the average value holding circuit 221
Is taken from the output of the amplifier 77. Therefore, the output terminal of the amplifier 77 is connected to the first,
The second and third average value holding circuits 223, 224, and 225 are provided. It should be noted that the output for the original use is
4 to an output terminal 235.

The average value holding circuit 221 has two states. One is a state where the average value is held (see FIG. 23), and the other is a state where the average value is output (see FIG. 24). FIG. 23 shows one embodiment in a state where the switch transistor Q10 is turned on and the amplifier 77 amplifies the photoelectric conversion output based on the dark output reference voltage Vref. The average value holding circuit 221 is a second average value holding circuit 224.
Switch transistor Q13 is turned on and capacitor C
12 stores the photoelectric conversion output of the second island IS2. At this time, the switch transistors Q11, Q15 and Q12, Q14, Q16 are all OFF.

FIG. 24 shows that the average voltage of the second average holding circuit 224 is output from the switch transistor Q14, and the amplifier 77 outputs the photoelectric conversion output OS2 of the second island IS2.
Of the second island IS2
5 is a time chart when the photoelectric conversion output OS2 of FIG.
N, Q11, Q12, Q13, Q15, Q16 are OF
F.

FIG. 24 shows the case where the average voltage of the second average holding circuit 224 is used as the reference voltage of the amplifier 77. This is the case where the photoelectric conversion output input to the contrast control circuit 230 is OS2. Next, when OS3 is input to the contrast control circuit 220 instead of OS2, the third average value holding circuit 224 operates. , The average of which can be used as the reference voltage for amplifier 77. Of course, even in this case, the dark output reference voltage Vref of the dark output reference voltage applying circuit 222 may be selected. The same applies to a case where OS1 is input to the contrast control circuit 230 after OS3.

25A shows a case where the voltage Vref of the dark output reference voltage applying circuit 222 is amplified by the amplifier 77 as a reference voltage (dark output voltage reference mode), and FIG. The case where the voltage from the circuit 221 is used as a reference voltage and amplified by the amplifier 77 (average value reference mode) is shown. Here, L1 is an amplifier 77
Is a signal (photoelectric conversion output) waveform input to the input terminal L1, and L2 is a signal waveform after amplification. In the case of (a), the level of L2 is increased with respect to Vref by amplifying with reference to Vref . At this time, the gain of the amplifier 77 is greater than 1.
If it is large, the amplitude of the signal waveform of L2 also becomes large. However
However, if the gain is set to about 1, the amplitude of the signal waveform hardly changes. On the other hand, in the case of (b), the level VOS with respect to Vref does not change, and the amplitude of the signal waveform is amplified.

Now, which voltage is selected as the reference voltage of the amplifier 77 is determined by φAV1, φAV2, φAV3,
It depends on φB, of which φAV1, φAV2,
There is no problem because φAV3 is determined according to the photoelectric conversion outputs OS1, OS2, and OS3 input to the contrast control circuit 220. However, when to select the average value holding circuit 221 and the fixed value providing circuit 222 is determined. It becomes a problem.

The switching between the implicit output voltage reference mode and the average value reference mode is performed by discriminating the state of the MD3 signal at the second falling of the SHM signal shown in the timing charts of FIGS. Is determined outside the AF sensor based on the evaluation function
It can be performed by switching on / off of V1, φAV2, φAV3 and φB. MD3 signal is
If the level is “High”, the average value reference mode, and “Lo”
If the level is w "level, the dark output voltage reference mode is selected. Alternatively, the switching is performed by the AF sensor 1 shown in FIG.
7 can be automatically performed by an analog signal processing circuit 176 in the inside.

Furthermore, automatic switching and external switching can be selected for switching between the dark output voltage reference mode and the average value reference mode. FIG. 17, FIG.
As shown in the timing chart of FIG. 8, the selection can be made according to the state of MD3 at the first fall of the SHM signal. For example, when the MD3 is set to the "High" level, the mode is externally switched. When the MD3 is set to the "Low" level, the mode can be automatically switched.

An example of the automatic switching between the dark output reference mode and the average value reference mode will be described below. When the average level of the accumulated charge of each pixel reaches an appropriate level and integration is completed, the average value reference mode is used. This is a method of selecting a dark output voltage reference mode when a mode is selected and integration is compulsorily terminated due to a data request from the AF controller 30. Here, the state in which the average level of the accumulated voltage reaches the appropriate level and ends, as described above,
This is the case where the brightness of the subject is high, and the AF controller 30
As described above, the data is requested by the user to terminate the integration when the brightness of the subject is very low.
In this embodiment, the output of the monitor photodiode MPD is used to detect whether or not the average level of the accumulated charge of each pixel reaches an appropriate level. However, the output of the photodiode PD is different from such an embodiment. You may make it detect using an output.

As another example, there is a method of detecting the maximum value and the minimum value of the accumulated charge amount of each pixel and performing switching depending on whether the difference is larger than a predetermined level. In this case, if it is higher than the predetermined level, the dark output voltage reference mode is set, and if it is lower than the predetermined level, the average value reference mode is set.

Various variations of the above-described contrast control circuit 220 are conceivable. Among them, those shown in FIGS. 26 to 30 will be described. First, in FIG. 26, the output of the amplifier 77 is input to the average value calculation unit 240, and the average value obtained by the calculation processing is input to the average value holding circuit 2
21. Then, the average value and the output of the dark output reference voltage applying circuit 222
The signal is switched at 36 and supplied to the amplifier 77. Switch 236
Can be substituted by Q10, Q12, Q14, and Q16 in FIG.

Next, in FIG. 27, the monitoring photodiodes MPD of each of the islands IS1 to IS3 are averaged.
(See FIG. 13) uses a monitor output AGCOS output by photoelectric conversion. The monitor output output from the monitor output unit 81 is input to the average value holding circuit 221 and held. In this case, the average value holding circuit 221 is different only in that the input signal is a monitor signal.
The circuit configuration may be substantially the same as that of FIG.

In FIG. 28, the maximum value detection unit 242 and the minimum value detection unit 243 detect the maximum value and the minimum value, respectively, from the photoelectric conversion output, and the maximum value and the minimum value are added by the next arithmetic circuit 244 and are calculated by 2 The average value is calculated by dividing.
The average value thus calculated is input to the next average value holding circuit 221. The maximum value detection in the maximum value detection unit 242 and the minimum value detection in the minimum value detection unit 243 may be configured to sequentially calculate and calculate inputs at predetermined intervals.

In FIG. 29, a fixed voltage predetermined by the fixed voltage generation circuit 245 is used as the average voltage.

FIG. 30 shows an example in which the voltage supplied from the external input source 246 is taken into the average value holding circuit 221 through the D / A converter 247.

In the above embodiments, the photoelectric conversion device is a so-called destruction-type photoelectric conversion device in which the photoelectric conversion output is sequentially processed and then destroyed. An example of a contrast control circuit in the case where reading from an element array is performed using a non-destructive reading device will be described.

In FIG. 31, the photoelectric conversion output OS of each of the photoelectric conversion element rows 16a, 16b, 16c in FIG.
1, OS2, OS3 can be stored without destruction even after processing,
A rewritable storage device 91 is used. The storage device 91 includes the photoelectric conversion element arrays 16a, 16b, and 16c.
A portion 91a for storing the photoelectric conversion output of the reference portion and a portion 91b for storing the photoelectric conversion output of the reference portion of the photoelectric conversion element rows 16a, 16b, 16c. To the first and second analog operation units 92 and 93.

The first analog operation section 92 performs an average value calculation for calculating the reference voltage for amplification in the average value reference mode, and outputs the calculated voltage to the average value holding circuit 221 to hold it. The second analog operation section 93 performs an operation for mode switching, and supplies the mode switching signal to the changeover switch 236. This switch 236 includes switching transistors Q10, Q12,
Since it corresponds to Q14 and Q15, the mode switching signal is φ
AV1, φAV2, φAV3, and φB, whereby the switching transistors Q10, Q12,
Switching between the dark output voltage reference mode and the average value reference mode is performed by controlling ON / OFF of Q14 and Q15.

There are various application examples of a method for obtaining an appropriate contrast by switching between the average value reference mode and the dark output voltage reference mode shown in the text. One example is shown in FIG. In this example, a correlation calculation function is added to the analog processing unit 176 that performs analog processing on the above-described photoelectric conversion output. In the figure, as for the output from the photoelectric conversion element array, the reference section output and the reference section output are read from the memory 91 in a non-destructive type. Each output is switched between the average value reference mode and the dark output reference mode automatically or manually or in accordance with various selections according to various conditions, and the amplifiers 77A and 77B perform appropriate amplification according to the respective outputs. The result is input to the analog correlation operation circuit 250, and the correlation result in each island is output.

Next, in the example shown in FIG. 33, a circuit for correcting variation in sensitivity peculiar to each pixel of the CCD is added. The output from each photoelectric conversion element row is E ² PRO
After the variation is corrected by the pixel correction circuit 301 based on the correction value for each element stored in the storage unit 300 such as M, the amplified value is amplified based on the average value or the dark output voltage. Good output can be obtained.

[0122]

As described above, the photoelectric conversion device of the present invention has a mode in which the photoelectric conversion output from the photoelectric conversion means comprising a plurality of pixels is amplified with reference to the dark output voltage .
A mode in which amplification is performed based on an average voltage of the effective pixel output (average voltage or a voltage corresponding thereto) , and
Contrast in photoelectric conversion output or photoelectric conversion
The difference between the maximum and minimum values of the accumulated charge of each pixel in the stage
Control means for selecting each mode based on the
Therefore, the contrast in the photoelectric conversion output or the photoelectric conversion
The maximum and minimum values of the accumulated charge of each pixel in the conversion means
Therefore, it is possible to select an appropriate mode in accordance with the difference between the two , and it is possible to efficiently increase the contrast.

Further, the photoelectric conversion device of the present invention has a plurality of pixels.
A well comprising a photoelectric conversion unit, a first mode for amplifying the basis of the dark output voltage output from the photoelectric conversion means,
An amplifier having a second mode for amplifying based on an average voltage of the effective pixel output, integrating means for integrating the output charge of the photoelectric conversion means, and integration value of the integration means or integration value of the monitoring integration means A first control means for terminating the integration by the integrating means when the pressure reaches a predetermined level, and forcibly terminating the integration by the integrating means when the predetermined value is not reached within a predetermined time; and A second control means for operating the amplifier in the second mode when the integration is completed by reaching the level, and operating the amplifier in the first mode when the integration is forcibly ended. Therefore, the first mode is selected when the luminance of the photoelectric conversion output is low, the contrast of the photoelectric conversion output having a low contrast is improved, and the second mode is relatively selected. Since the selection is made when the degree is high, the effect of improving the contrast of the photoelectric conversion output having high luminance but low contrast is obtained, and the output of the integrating means provided for luminance detection for another purpose is also used. Therefore, it is not necessary to provide the first and second mode switching control signals exclusively.

[Brief description of the drawings]

FIG. 1 is a diagram showing three sets of CCDs and a selection control system of their outputs in a photoelectric conversion device embodying the present invention.

FIG. 2 is a diagram showing a focus detection optical system in a single-lens reflex camera with an automatic focus detection function using a photoelectric conversion device.

FIG. 3 is a diagram showing a focus detection optical system in a single-lens reflex camera with an automatic focus detection function using a photoelectric conversion device.

FIG. 4 is a view showing a focus detection area and a display in a viewfinder with respect to a shooting screen of a camera.

FIG. 5 is a diagram showing an array of CCD light receiving units used in the focus detection device.

FIG. 6 is an enlarged view of a focus detection area on a shooting screen.

FIG. 7 is a diagram showing a reference portion and a reference portion of a second island IS2.

FIG. 8 is a diagram showing a defocus range divided into blocks in each island.

FIG. 9 is a circuit diagram of an AF sensor, an AF controller, and peripheral portions thereof.

FIG. 10 is a configuration diagram of an AF sensor.

FIG. 11 is a diagram showing a portion including main components of a photoelectric conversion element array.

FIG. 12 is a sectional view schematically showing the physical structure of a photodiode array unit.

FIG. 13 is a configuration diagram of a photoelectric conversion element row.

FIG. 14 is a potential distribution diagram of a one-dimensional photoelectric conversion element row.

FIG. 15 is a potential distribution diagram of a one-dimensional photoelectric conversion element row when a high-brightness integration mode is selected.

FIG. 16 is a potential distribution diagram of a one-dimensional photoelectric conversion element row when a low luminance integration mode is selected.

FIG. 17 is a time chart of each signal in the high brightness integration mode.

FIG. 18 is a time chart of each signal in the low luminance integration mode.

FIG. 19 is a circuit diagram of an AGC signal processing circuit.

FIG. 20 is a time chart of each signal in the AGC signal processing circuit.

FIG. 21 is a detailed view of the first half of the analog signal processing unit.

FIG. 22 is a detailed view of the latter half of the analog signal processing unit.

FIG. 23 is a time chart when the amplifier amplifies the photoelectric conversion output based on the dark output reference voltage.

FIG. 24 is a time chart when the amplifier amplifies the photoelectric conversion output of the second island using the average value of the photoelectric conversion output of the second island as a reference voltage.

FIG. 25 is a diagram showing signal waveforms in each case where a voltage output from a dark time output reference voltage applying circuit or an average value holding circuit is amplified by an amplifier using the voltage as a reference voltage.

FIG. 26 is a block diagram showing the latter half of the analog signal processing unit when the average value of the photoelectric conversion output is used as the average value during amplification.

FIG. 27 is a block diagram showing a second half of an analog signal processing unit when a monitor output is used as an average value during amplification.

FIG. 28 is a block diagram showing the latter half of the analog signal processing unit when an intermediate value between the maximum value and the minimum value of the photoelectric conversion output is used as the average value during amplification.

FIG. 29 is a block diagram showing the latter half of the analog signal processing unit when a predetermined fixed voltage is used as an average value during amplification.

FIG. 30 is a block diagram showing the second half of the analog signal processing unit when a voltage of a value input from the outside is used as an average value during amplification.

FIG. 31 is a block diagram showing a second half of an analog signal processing unit in which a photoelectric conversion output is temporarily stored in a rewritable non-destructive storage device so that an average value and a switching mode during amplification can be arithmetically processed; .

FIG. 32 is a block diagram showing an application example for obtaining an appropriate contrast by switching between an average value reference mode and a dark output voltage reference mode.

FIG. 33 is a block diagram showing the latter half of the analog signal processing unit when a circuit for correcting a variation in sensitivity peculiar to each pixel of the CCD is added.

[Explanation of symbols]

 16a, 16b, 16c Photoelectric conversion element array 77 Amplifier 220 Contrast control circuit 221 Average value holding circuit 222 Dark output reference voltage applying circuit 230 Reference voltage supply circuit IS1, IS2, IS3 First, second, third island

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masataka Hamada 2-3-113 Azuchicho, Chuo-ku, Osaka-shi Osaka International Building Minolta Camera Co., Ltd. (56) References JP-A-62-163009 (JP, A (58) Fields investigated (Int. Cl. ⁷ , DB name) G02B 7/34

Claims (3)

(57) [Claims] A mode for amplifying an output from a photoelectric conversion means comprising a plurality of pixels on the basis of a dark output voltage; a mode for amplifying the output based on an average voltage of effective pixel outputs; If the contrast is low, select the mode that amplifies based on the average voltage of the effective pixel output when the contrast is low, and amplify based on the dark output voltage when the contrast is high. And a control unit for selecting a mode to be performed. 2. A photoelectric conversion means comprising a plurality of pixels, a first mode for amplifying an output from said photoelectric conversion means with reference to a dark output voltage, and an average power of effective pixel outputs. An amplifier having a second mode for amplifying on the basis of pressure, an integrating means for integrating the output charge of the photoelectric conversion means, and an integrating means when the integrated value of the integrating means or the integrating value of the monitoring integrating means reaches a predetermined level. First control means for terminating the integration of the means and forcibly terminating the integration by the integrator when the predetermined level is not reached within a predetermined time; and A second control means for operating the amplifier in the second mode when the operation is completed, and operating the amplifier in the first mode when the integration is forcibly ended. 3. A mode for amplifying an output from a photoelectric conversion means comprising a plurality of pixels on the basis of a dark output voltage; a mode for amplifying on the basis of an average voltage of effective pixel outputs; Detecting the maximum value and the minimum value of the accumulated charge amount of each pixel at a time, and when the difference between the maximum value and the minimum value is larger than a predetermined level, selects an amplification mode based on a dark output voltage; Control means for selecting a mode in which amplification is performed based on an average voltage of the effective pixel output when the difference between the value and the minimum value is equal to or smaller than a predetermined level.