JP2707644B2 - Charge storage type photoelectric conversion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage type photoelectric conversion device, and is particularly suitable as a focus detection element of an automatic focus camera having a plurality of focus detection areas. .

[Related Art] Conventionally, it has been proposed to use a charge storage type photoelectric conversion element such as a CCD line sensor as a focus detection element of a camera. The CCD line sensor has a light receiving element row,
A charge storage element array for accumulating charges obtained from the light receiving element array, and a charge transfer element array for transferring the accumulated charges of the charge storage element array in parallel and reading out serially in accordance with a transfer clock; Since the luminance distribution on the line can be detected and the luminance distribution data can be read out in a self-scanning type, it is extremely suitable as a focus detection element. However, the CCD line sensor does not detect the absolute amount of the received light, but by looking at the relative value of the charge stored in the charge storage element row,
The brightness distribution of the light applied to the light receiving element array is known. If the received light is too strong, the output from the charge storage element array is saturated and the output signal is distorted, and the received light is too weak. And the output from the charge storage element row decreases,
There is a problem that the ratio becomes worse. Therefore, a light receiving element for luminance monitoring is arranged near the light receiving element row, more preferably between each light receiving element, and the charge accumulation time in the charge storage element row is controlled according to the luminance monitor output. It has been proposed that the charge accumulation time is shortened when the luminance is high, and the charge accumulation time is lengthened when the luminance is low, so that the charge accumulation amount is controlled to an appropriate value.

Japanese Patent Application Laid-Open No. Sho 60-256279 discloses a one-line CCD.
For the line sensor, it has been proposed to divide the light receiving element array into a plurality of blocks, arrange a light quantity monitor for each block, and control the charge accumulation time for the brightest block, but each block is arranged discretely However, the light amount difference between the blocks is not so large. Further, the charge accumulation time is not controlled for each block.

[Problems to be Solved by the Invention] By the way, in an autofocus camera having a plurality of focus detection areas, it is necessary to discretely arrange a plurality of CCD line sensors. In this case, since different focus detection areas capture different subjects, the subject images formed on the respective CCD line sensors also differ, and the brightness thereof also differs. Therefore, if the charge accumulation time of each CCD line sensor is controlled according to the average brightness of the entire screen, the output is saturated because the charge accumulation time is too long than the appropriate value, or the S / N ratio is too short and the charge accumulation time is too short. Or lower. Then, when the output of the CCD line sensor is saturated or the S / N ratio is lowered, there is a problem that accurate automatic focus detection cannot be performed, which sometimes results in false focus detection.

The present invention has been made in view of such a point,
An object of the present invention is to provide a charge storage type photoelectric conversion device capable of appropriately controlling the charge storage time of a plurality of photoelectric conversion element arrays.

[Means for Solving the Problems] In the charge storage type photoelectric conversion device according to the present invention,
In order to solve the above problem, as shown in FIG. 1, a plurality of light receiving element rows 1a to 1c and a plurality of charge storage element rows 2a to 2c provided corresponding to the respective light receiving element rows 1a to 1c. And a plurality of gate element rows 3a to 3c capable of blocking the flow of charges from the respective light receiving element rows 1a to 1c to the corresponding charge storage element rows 2a to 2c, and the accumulated charges of the respective charge storage element rows 2a to 2c in series. Scanning means 4a to 4c for sequential reading, and by controlling the corresponding gate element rows 3a to 3c in a blocking state in accordance with the amount of light incident on each of the light receiving element rows 1a to 1c, each of the light receiving element rows 1a to 1c is controlled. And storage time control means 5a to 5c for individually controlling the charge storage time.

The scanning means 4a to 4c include the charge storage element rows 2a to 2c.
It is preferable to use a charge transfer register in which the accumulated charges of 2c are transferred in parallel and read out serially in accordance with a transfer clock, but a sequential readout circuit using a switching circuit may be used.

[Operation] Hereinafter, the operation of the present invention will be described with reference to FIG. Each of the light receiving element arrays 1a to 1c generates a photocurrent according to the amount of incident light. This photocurrent is supplied to the charge storage element array through the gate element arrays 3a to 3c.
It flows into 2a-2c and is accumulated as charge information. The charge accumulation speed in each charge storage element row 2a to 2c is
It increases according to the amount of light incident on .about.1c. Therefore, in the present invention, by the accumulation time control means 5a to 5c, the corresponding gate element rows 3a to 3c are controlled to be in a cutoff state according to the amount of light incident on each of the light receiving element rows 1a to 1c, and each light receiving element is controlled. The charge accumulation time is individually controlled for each of the columns 1a to 1c. The charge storage time is set to be long within a range where the output is not saturated. Since the photoelectric conversion device of the present invention relatively detects the luminance distribution of the portion where the light receiving element rows 1a to 1c are provided, by setting the charge accumulation time to be long as long as the output is not saturated, The S / N ratio is improved, and the data of the luminance distribution can be detected accurately. After the charge storage operation is completed, the charge storage element rows 2a to 2c are
Until the accumulated charge is read in series by ~ 4c,
While waiting while holding the accumulated charge, at this time, since the charge storage element rows 2a to 2c are cut off from the light receiving element rows 1a to 1c, the potential of the charge storage element rows 2a to 2c is increased. By setting, the generation of dark charge can be reduced, and the S / N ratio is less likely to be degraded by the dark charge accumulated during standby.

As a comparative example with respect to the present invention, charge information obtained by photoelectric conversion is stored in the scanning units 4a to 4c, the scanning signals are held in a stopped state, and the scanning signals are sequentially supplied to the scanning units 4a to 4c. (See Japanese Patent Application No. 62-19838), the scanning means 4a to 4c as shown in FIG.
Has a larger area per pixel than the charge storage unit ST. The dark current due to the thermal excitation and the light excitation due to the pinhole generated in the light-shielding film increase in proportion to this area, and the generation of the noise charge is caused by the scanning means 4a to 4c.
There are many. Therefore, as in the present invention, the charge storage element rows 2a to 2c in which the generation of dark charge is small are provided, and after the charge storage operation is completed, the charge storage element rows 2a to 2c are provided until the stored charge is read out. Is preferably shielded from other element rows.

Embodiment A focus detection optical system in a single-lens reflex camera with an automatic focus detection function using the photoelectric conversion device of the present invention will be described with reference to FIGS. 2 and 3. FIG. In the camera body of the single-lens reflex camera, a photographic lens 11 is provided on an optical axis 10, a main mirror 12 is provided at an angle of 45 degrees upward behind the photographic lens 11, and a film exposure surface 13 is provided behind the main mirror 12. The light beam for photographing that has been provided and passed through the photographing lens 11 is
Is reflected upward, is focused on the focusing screen, and is guided to a finder optical system via a pentaprism.

At least a part of the main mirror 12 is formed as a half mirror, and between the half mirror portion of the main mirror 12 and the film exposure surface 13, a rotation axis is pivotally mounted on a back portion of the main mirror 12. The secondary mirror 14 is provided at 45 degrees downward and the primary mirror 12
The focus detection light beam transmitted through the half mirror section
The light is reflected downward at 14 and guided to a focus detection device 15 arranged below the mirror box of the camera body.

At the time of photographing, the main mirror 12 and the sub-mirror 14 are pivoted forward and upward to retreat from the optical axis 10, and the photographing light flux passing through the photographing lens 11 forms an image on the film exposure surface 13, and 13 to give an imagewise exposure.

The focus detection device 15 includes three photoelectric conversion element rows 16a,
An AF sensor 17 including 16b and 16c is provided. One photoelectric conversion element row 16a among the photoelectric conversion element rows 16a to 16c
Is arranged at a horizontal position including the optical axis 10, and the two photoelectric conversion element rows 16b and 16c are disposed on both sides of the photoelectric conversion element row 16a.
Are arranged in vertical positions not including The photocharge conversion element rows 16b and 16c are oriented at substantially 90 degrees with respect to the photoelectric conversion element row 16a.

A separator lens plate 18 is provided in front of the AF sensor 17, and the separator lens plate 18 has a photoelectric conversion element row 16a.
The separator lenses 18a to 18c corresponding to 〜 to 16c are integrally formed. An aperture mask 19 is provided immediately before the separator lens plate 18, and the aperture mask 19 has openings 19a to 19c corresponding to the separator lenses 18a to 18c. Reflection mirror facing aperture mask 19 and sub mirror 14
20 is provided, and the reflection mirror 20 converts the focus detection light flux reflected downward by the sub-mirror 14 to the photoelectric conversion element rows 16a to 1a through the aperture mask openings 19a to 19c and the separator lenses 18a to 18c.
It leads to 6c. Reflecting mirror 20 and secondary mirror 14
Are provided between the condenser lenses 21a to 21c facing the aperture mask openings 19a to 19c, respectively.
A field mask 22 having openings 22a to 22c for separating the focus detection light flux so as to correspond to the photoelectric conversion element rows 16a to 16c having different positions and directions is provided on the upper surfaces of the light-receiving elements 21a to 21c.

The principle of focus detection is a TTL phase difference detection method, and different areas 11a, 11b, 11c on the exit pupil plane of the taking lens 11.
And reference beam a passing through 11d (shown by a broken line in FIG. 3)
And a reference portion light beam b (shown by a solid line in FIG. 3) are received by the reference portion A and the reference portion B in each of the photoelectric conversion element rows 16a to 16c, and the light distribution pattern of the image is converted into an electric signal. A correlation device (not shown) for determining the correlation between them, performs automatic focus detection, and performs automatic focus adjustment by moving the photographing lens 11 back and forth by a driving mechanism based on a shift signal from the correlator. It is.

In the focus detection optical system of FIG. 2, in addition to the photocharge conversion element rows 16a at the horizontal position, the photoelectric conversion element rows 16b and 16c at the vertical position
Is provided, the focus detection in the horizontal direction and the vertical direction can be performed simultaneously, so that the focus detection of a horizontal line and the like can be performed.

FIG. 4 shows the focus detection area and the display in the viewfinder with respect to the photographing screen of the camera using the AF sensor 17 of this embodiment. In this example, focus detection is performed on subjects in three areas IS1, IS2, and IS3 (hereinafter, referred to as a first island, a second island, and a third island, respectively) indicated by solid lines in the center of the screen with respect to the shooting screen S. It can be carried out.
A rectangular frame AF indicated by a broken line in the drawing is displayed so as to show a photographer of an area where focus detection is being performed.
The display Lb shown outside the shooting screen S indicates the focus detection state, and is turned on when focusing.

FIG. 5 shows a light receiving section of a CCD used in the focus detection device (the CCD including the light receiving section, the storage section, and the transfer section). Each island IS1, IS2, IS in Fig. 5
3 is provided with a reference section and a reference section, respectively, and the light receiving elements MPD1 for monitoring for controlling the integration time of the CCD into the storage sections in the respective islands IS1, IS2, IS3,
MPD2 and MPD3 are provided respectively. Each island IS1, IS2,
The number of pixels (X, Y) of the reference part and the reference part of IS3 is (34, 44) for the eyelined IS1, (44, 52) for the island IS2, and (34, 44) for the island IS3. These are all formed on one chip.

In the focus detection device according to the present embodiment, the reference portion in the CCD of the above three islands IS1 to IS3 is divided into a plurality of blocks, and the focus detection is performed by comparing the reference portion of the divided block with all of the reference portions. Do. In each island, among the focus detection results obtained in the divided blocks, the data of the last pin is used as focus detection data of each island,
Further, the focus detection data of the camera is calculated based on the focus detection data of each island.

The range to be divided and the defocus range of the divided block will be described with reference to FIGS. 6 to 8. FIG. FIG. 6 is an enlarged view of the focus detection area on the photographing screen S shown in FIG. Each island for focus detection
IS1, IS2 and IS3 are areas of the reference part shown in FIG. In FIG. 6, the numerical value shown in each island indicates the number of difference data obtained by taking the difference of every third pixel of the CCD shown in FIG. 5 (the difference data is two or one. However, at this time, the above numerical values are different.) Therefore, the number (X, Y) of difference data between the reference portion and the reference portion in each island is (3
0,40), Island IS2 (40,48), Island IS3
Then it is (30,40). Each island is divided into two parts. In the island IS1, the two parts are divided into (1-20) and (11-30) based on the difference data at the upper end.
1, the second block BL2. In Island IS2, it is divided into three, and from the difference data on the left end (1-20), (11-30),
(21-40), 3rd block BL3, 4th block B, respectively
L4, the fifth block BL5. In addition, 7
Sum of adjacent data of every other data (1 to 35)
Is the sixth block BL6, and the front part of this data string (1-2
5) is the seventh block BL7, and the rear part (11 to 35) is the eighth block
BL8. In the island IS3, from the difference data at the upper end, (1-20) and (11-30)
BL9 and the tenth block BL10.

In the focus detection of the phase difference detection method, when the image interval when the images of the reference portion and the reference portion coincide with each other is larger than a predetermined interval, the focus is on the rear focus, and when smaller, the focus is on the front focus and at the predetermined interval. Therefore, the defocus range of the divided blocks is assigned to the rear focus side as the blocks are farther from the optical center of each island. A specific description will be given based on FIG. 7 showing the state after the difference data has been obtained. FIG. 7 shows a reference portion and a reference portion of the island IS2, and now consider a defocus range of the fourth block BL4 divided into blocks. At this time, the focus is on the 15th to 34th images (15 'to 34') from the left end in the reference section.
And when the images (11 to 30) of the fourth block BL4 match. From this, when the image coincidence is on the left side of the reference portion, the front pin is set. At this time, the maximum number of shift data of the front pin (hereinafter referred to as shift pitch) is 14, and when the image coincidence is on the right side of the reference portion, the rear pin is set. At that time, the maximum rear pin shift pitch is 14. The same applies to the defocus range divided into blocks in each of the other islands.
In the third block BL3, the front pin side shift pitch is 4, the rear pin side shift pitch is 24, and in the fifth block BL5, the front pin side shift pitch is 24, and the rear pin side shift pitch is 4. For the islands IS1 and IS3, the front-pin-side deviation pitch is 5, the rear-pin-side deviation pitch is 15 in the blocks BL1 and BL9, and the front-pin-side deviation pitch is 15 and the rear-pin-side deviation pitch is 5 in the blocks BL2 and BL10. . In the sixth block BL6, the rear and front pins have a pitch of 4 pitches, and in the seventh block BL7, the rear pin has a pitch of 4 to 14 pitches. The eighth block BL8
Then, the pitch is 4 to 14 pitches on the front pin side.

FIG. 9 shows an AF sensor 17 and an AF controller as an example in which the photoelectric conversion device of the present invention is used for a focus detection device of a camera.
30 and its peripheral circuits are disclosed. AF controller 30
Is formed by a one-chip microcomputer, in which an A / D converter 31 for converting an analog signal obtained from the analog signal output line Vout of the AF sensor 17 into a digital signal, and a ROM for a photographing lens (interchangeable lens) from the lens data output section 40 including the respective lenses at different defocus amount - lens movement amount conversion coefficients K _L, the data such as the color temperature defocus amount dF _L previously input, and the a / D converter
Digital data from 31 is stored one by one, a memory unit 32 formed of RAM, a focus detection unit 33 that detects a focus based on an output of the memory unit 32, and the detected focus data and lens data. Correction calculation unit 34 for calculating the correction amount
And a lens drive control unit that sends a signal for driving the lens based on the correction amount to the lens drive circuit 42 and receives data on the movement state of the lens from the encoder 44.
A timer circuit 36 for monitoring whether or not an integrated value (hereinafter, “charge integration” is also referred to as “integration”) at the AF sensor 17 reaches a predetermined value within a predetermined time;
It has an AF sensor 17 and an AF sensor control unit 37 for transmitting and receiving signals. Reference numeral 43 denotes a lens driving motor, and reference numeral 41 denotes a display circuit controlled by the AF controller 30. The AF sensor 17 and the AF controller 30 are separately formed one chip at a time, so that the AF system is composed of a total of two chips. Vref
Is an analog reference voltage of the A / D converter 31 and the AF sensor 17 of the AF controller 30, Vcc is a power supply line, and GND is a ground line.

MD1, MD2, IC between AF sensor 17 and AF controller 30
G, SHM, CP, ADT, and Vout are connected by seven signal lines. Of the seven signal lines described above, MD1 and MD2 are signal lines for outputting a logic signal from the AF controller 30 to the AF sensor 17, and set the operation mode of the AF sensor 17. The AF sensor 17 has four operation modes: an initialization mode, a low-luminance integration mode, a high-luminance integration mode, and a data dump mode. The operation mode is set by a combination of the logic levels of the signal lines MD1 and MD2. The signal lines ICG and SHM are bidirectional, and serve as output logic lines from the AF sensor 17 to the AF controller 30 in the data dump mode described above, and output information on the brightness of the subject in each island and the integration completion order. In other modes, signal line IC
G is an ICG signal for instructing the AF sensor 17 to start a new integration, and a signal line SHM is an SHM signal for instructing the AF sensor 17 to request data.
Logic line to be supplied to The signal line CP is a line for supplying a basic clock from the AF controller 30 to the AF sensor 17. The basic clock supplied from this signal line CP can be turned ON / OFF inside the AF controller 30. By turning this basic clock OFF, A
It is also possible that the operation of the F sensor 17 is temporarily frozen, and the AF controller 30 controls another circuit portion, for example, the lens drive circuit 42 and the like. The signal line ADT indicates the completion of the output of one pixel data of the AF sensor 17 in the data dump mode, and the A / D converter 31 in the AF controller 30
Supplies an ADT signal instructing to start A / D conversion. In another mode, when charge accumulation is performed to an appropriate level in each island of the AF sensor 17, an interrupt signal is output from the AF sensor 17 to the AF controller 30 to indicate the completion of integration. Finally, the signal line Vout is an analog signal line, and the photoelectric conversion element array 16a in the AF sensor 17
After analog output signal processing of ~ 16c, AF sensor 17
From the AF controller 30 to the A / D converter 31. This Vout signal is output for each pixel in synchronization with the above-mentioned ADT signal, and after being A / D converted, is taken into the AF controller 30 as subject image information obtained from the AF sensor 17.

Next, a specific configuration of the AF sensor 17 will be described with reference to FIG. In the figure, the photoelectric conversion element rows 16a to 16c are shown on the left side, and the I / O portion with the AF controller 30 is shown on the right side. First, the photoelectric conversion element rows 16a to 16c are divided into three islands IS1 to IS3 arranged in an H shape, as shown in the above-described display in the viewfinder of FIG. Controlled. The detailed configuration of the photoelectric conversion element rows 16a to 16c is shown in FIG. 11 to FIG. Among them, a portion including main components such as the photodiode PD and the shift register SR will be described. As shown in FIG. 11, the photodiode array section 50 includes a plurality of pixel photodiodes PD.
, And a monitor photo-automatic MPD arranged therebetween are alternately provided. One end in the longitudinal direction of the photodiode PD for each pixel is a first end forming a barrier gate.
It is coupled to the source of MOS transistor TR1. This MO
The drain of the S transistor TR1 is coupled to the storage unit ST of the next stage, and the gate is coupled to a supply line of a BG signal (barrier gate signal). The storage section ST is shielded from light by the aluminum film and is not irradiated with light, but generates a so-called dark charge. The output terminal of the storage unit ST is coupled to the source of the second MOS transistor TR2 forming the integration clear gate ICG and the source of the third MOS transistor TR3 forming the shift gate SH. The drain of the second MOS transistor TR2 is coupled to a power supply line Vcc, and the gate is coupled to a supply line for an ICG signal (integral clear gate signal). On the other hand, the drain of the third MOS transistor TR3 is coupled to a segment forming the shift register SR, and the gate is coupled to a supply line for an SH signal (shift gate signal).

The monitoring photodiodes MPD are connected to each other on the upper end side in the figure, and thus the monitor output is the total output of the plurality of connected monitoring photodiodes MPD. By combining a plurality of monitoring photodiodes MPD in this manner, a subject luminance monitoring photodiode having a wide field of view can be realized.

The outline of the physical structure of the photodiode array section 50 is shown in FIG. 12, which shows a cross section taken along line CC 'in FIG. 11, and a P-type region 52 formed in a silicon substrate 51 by a diffusion method and an implantation method. A channel stopper 54 made of P ⁺ (a P-type high-concentration impurity diffusion region) applied to the upper N-type region 53 to separate the pixel photodiode PD and the monitoring photodiode MPD from each other.
An N ⁺ film 55 is provided on the surface to suppress the dark output of each photodiode PD and suppresses the surface depletion layer. A positive potential is externally applied to the silicon substrate 51, and a ground potential is applied to the intermediate P-type region 52. The N-type region 53 is formed by phosphorus implantation, and the P-type region 52 is formed by boron diffusion.

The pixel photodiode PD, the monitor photodiode MPD, and the first one for the barrier gate BG in FIG.
MOS transistor TR1, storage unit ST, integration clear gate IC
A large number of cascaded units of the second MOS transistor TR2 for G, the third MOS transistor TR3 for the shift gate SH, and the shift register SR are arranged in the horizontal direction. For example, if the number of segments of the shift register SR is counted, There are 128.

However, as seen at the right end of the array shown in FIG. 13,
Photodiode for pixel PD, photodiode for monitor MP
D, MOS transistor TR1 for barrier gate, storage unit ST,
The number of segments of the integration clear gate MOS transistor TR2 and the shift gate MOS transistor TR3 is smaller than the shift register SR by five on the right end side. Conversely, only the number of segments of the shift transistor SR is increased on the right end side. These five segments merely function as a photocharge transfer path.

In FIG. 13, the rightmost five and the leftmost three of the pixel photodiode PD and the monitor photodiode MPD are shielded from light by an aluminum film as shown by oblique lines. These light-shielded photodiodes PD generate dark charges used for dark correction of the output of the pixel photodiode PD, for example. One portion of the photodiode array portion is assigned as a reference portion A, and the other portion is assigned as a reference portion B. For example, the reference portion A includes 44 pixels and the reference portion B includes 52 pixels of photodiodes PD and monitor photodiodes PD. However, structurally, there is no distinction between the reference portion A and the reference portion B, and they are distinguished by software processing in the AF controller 30 described later.

Regarding portions considered unnecessary between the reference portion A and the reference portion B, only the shift register SR is left, and the other photodiodes for pixels PD, the photodiodes for monitoring MPD,
Part or all of the MOS transistor TR1 for the barrier gate, the storage unit ST, the MOS transistor TR2 for the integration clear gate, and the MOS transistor TR3 for the shift gate are deleted. The pitch of each segment of the shift register SR corresponding to this deleted portion is formed so as to be larger than the pitch of the other portions, and the number of transfer clocks required for transfer of all pixel outputs is reduced to reduce the total charge transfer time. I can shorten it.

The monitoring photodiodes MPD are connected to each other so that only those located at the reference portion A (and, if necessary, the reference portion B) are used, and those existing at other portions are not used. However, it is desirable that the unused monitoring photodiode MPD be connected to the power supply line Vcc and stabilized. When this is electrically floating, it receives guidance from the photodiodes PD for other pixels or causes guidance to the photodiodes PD for other pixels, and eventually,
This is because it affects other pixel photodiodes PD. The output of the monitoring photodiode MPD is once given to the capacitor C ₂ through the MOS transistor Q _5, and output as an automatic gain control output signal AGCOS through where it is held consisting source follower SF ₂ buffer. MOS transistor Q ₂ is used for initialization of the capacitor C _2. Therefore the automatic gain control power fluctuation in the output signal AGCOS and temperature-dependent component removal, drift from capacitor C ₁ to be initialized by the MOS transistor Q ₂ and the MOS transistor to Q ₁ the same configuration for initializing the capacitor C ₂ The output signal DOS is generated at the same time. This capacitor C _1, diode MD for drift component detecting a total area substantially equal area of the monitor photodiode MPD is connected via a MOS transistor Q _4. The diode MD is shielded from light by an aluminum film. The MOS transistors Q ₁ and Q ₂ for initialization are simultaneously turned on during the application period of the ICG signal (integral clear gate signal).

Here, the photoelectric conversion element rows 16a to 16c of this AF sensor 17
The charge integration mode will be described with reference to FIGS. 14 to 16. FIG. 14 is a potential distribution diagram of a conventional general one-dimensional photoelectric conversion element array. The photoelectric conversion element for one pixel is a photodiode with an overflow gate OG
PD and barrier gate B set at a constant potential
G, and a storage unit ST. First, the integration clear gate STICG
When the voltage is applied to the storage section ST, the storage section ST and the photodiode PD for photoelectric conversion discharge the charge stored before that to the overflow drain OD, as shown in FIG. 14 (a). This overflow drain OD is connected to the power line Vcc
It is designed in common with. By discharging the unnecessary charges, the charges remaining in the photodiode PD and the storage unit ST are eliminated,
Each pixel has been initialized. Next, by removing the voltage to the integration clear gate STICG, the potential level of the integration clear gate ICG rises, and
The outflow of charges from the drain to the overflow drain OD is stopped, and the photoelectric charges generated in accordance with the light intensity incident on the photodiode PD are thereafter stored in the storage section via the barrier gate BG as shown in FIG. 14 (b). It flows into the ST and is stored here. This is the charge accumulation operation (integration operation).
Here, when the average value of each pixel of the electric charge stored in the storage unit ST reaches an appropriate level for the subsequent processing circuit and processing operation, or when there is a data request from the AF controller 30, the integration is performed. Perform completion operation. This integration completion operation is performed by applying a voltage to the shift gate SH and lowering the potential level of this gate, as shown in FIG. Is injected into the corresponding shift register SR.

Here, the storage unit ST is provided for the following reasons. In the AF sensor 17, a high-sensitivity photodiode PD having a large pixel area is used so that the AF sensor 17 can be used even in a low luminance range, and the length l _{PH of the} AF sensor 17 generally reaches several hundred μm. On the other hand, the storage unit S
The length l _{ST of} T is generally about 50 μm depending on required conditions such as the saturation voltage. Here, considering the time required to transfer the charges to the shift register SR in the integration completion operation, it takes about 3 to 5 μsec to transfer the charges from the storage unit ST. This is a value dependent on the moving speed of the charge, and is known to increase in direct proportion to the square of the moving distance. Therefore, if charges are stored in the photodiode PD without providing the storage section ST, the charge transfer time τ _SH is set to l _PH = 200 μm, l _ST = 50 μm, and τ _SH = 5 × (l _PH / l _ST ) ² = 80 μsec, and even if voltage is applied to the shift gate SH to start the integration completion operation immediately after the start of integration, the state must be maintained for 80 μsec, and the minimum integration time is limited. Will receive. As a result, the dynamic range at the time of high luminance is reduced. From such a viewpoint, the storage unit ST
Is provided to shorten the charge transfer length at the end of integration and improve the response of the integration end operation.

When the above-described integration completion operation is completed and the voltage applied to the shift gate SH is removed, the photodiode PD and the storage unit ST are stored between the end of the previous integration completion operation and the end of the current integration completion operation. Is transferred in parallel to the corresponding shift register SR.

Thereafter, the charge as the image information is stored in the shift register SR.
₁₃ are sequentially transferred in the shift register SR in synchronization with the transfer clocks φ ₁ and φ ₂ supplied to the circuit, and are transferred via a buffer composed of a capacitor C _{3 serving} as a charge-voltage conversion means and a source follower SF _{3 in} FIG. Is read out as an analog voltage from the output signal line OS. Incidentally, MOS transistor Q ₃ are is for initializing the capacitor C _3.

However, the following problem occurs in this integration operation.

First, there is a problem of dark output. In this case, even in a state where no light is incident, electric charges corresponding to the potential level are generated in each portion by thermal excitation or the like. Therefore,
Normally, the potential level of the photodiode PD is set high, and it is necessary to set the potential level of the storage unit ST low due to the charge inflow condition. The time output is generally several times to several tens of times that of the photodiode PD. For this reason, most of the dark output, which is a noise component, is stored in the storage unit ST that is not actually related to photoelectric conversion.
And the S / N ratio is reduced as compared with a general photodiode PD.

Further, as described above, with the demand for higher sensitivity of the photoelectric conversion, a shorter integration time control is required. As described above, the shortest integration time is not only limited by the pulse width of the shift pulse SH, but also the generation of the shift pulse SH depends on the phase relationship between the transfer clocks φ ₁ and φ ₂ supplied to the shift register SR. Give restrictions.

Therefore, in the present embodiment, in order to reduce the dark output and achieve faster integration, the two integration modes are switched according to the respective use conditions.

ST integration mode (high-brightness integration mode) First, when inputting image information of a high-brightness subject requiring high-speed integration completion, the above-described signal line MD1,
Depending on the combination of MD2 logic, S shown in Fig. 15
T integration mode is selected. The integration clear operation and the integration operation shown in FIG. 15 (a) are carried out by the same operations as shown in FIG. 14 (a). In the ST integration mode, only the integration completion operation is different. In the photoelectric conversion element arrays 16a to 16c of the present embodiment, the photoelectric conversion element arrays 16a to 16c are designed so that the potential of the barrier gate BG disposed between the photodiode PD and the storage section ST can be controlled. During the integration clear operation and the integration operation shown in FIG.
A predetermined voltage is applied to the barrier gate BG so that the electric charge can be transferred between the gate and the storage unit ST, and the potential is set to a low level. If the average level of the accumulated charge of each pixel has reached an appropriate level in the subsequent processing circuit, or if a data request has been made from the AF controller 30, the signal indicates that the barrier gate BG applied until that time has been applied. As shown in FIG. 15 (b), the potential of the barrier gate BG is raised to a high level to stop the charge transfer between the photodiode PD and the storage unit ST. By prohibiting the charge generated by light incident on the PD from flowing into the storage unit ST, the integration operation is completed. Then, as shown in FIG. 15 (b),
By raising the potential of the storage unit ST to a high level, the generation of dark charge in the storage unit ST while holding the charge from the photodiode PD in the storage unit ST is suppressed, and the image information is stored in the storage unit ST. It is not damaged by the generated dark charge. After this state, with the generation of the data request signal SHM from the AF controller 30, as shown in FIG. 15 (c), a voltage is applied to the shift gate SH, thereby lowering the potential level of this gate. The charge transfer between the storage unit ST and the shift register SR is performed.

In this way, the data readout and the integration completion operation are performed separately, and the integration completion operation is realized only by changing the potential of the barrier gate BG from a low level to a high level. Has been realized.

PD integration mode (low-brightness integration mode) Next, the integration mode of the photodiode PD for a low-brightness subject requiring a reduction in dark output will be described with reference to FIG. In the integration mode of the photodiode PD, charge accumulation (integration) is performed by the photodiode PD with low dark output.
After the unnecessary dark output generated in the storage unit ST during this integration is discharged through the integration clear gate STICG, sufficient time is required to generate only the photodiode PD from the photodiode PD to the storage unit ST. In this mode, charges are transferred, then transferred to the shift register SR, and sequentially read. In this mode, since the charge transfer speed is limited as described above, it takes about 100 μsec for the integration completion operation, but image information can be read with an extremely low dark output.

The integration clear operation is performed in exactly the same manner as shown in FIG. Next, at the time of the start of integration, unlike the integration mode shown in FIG. 14 and the ST integration mode shown in FIG.
The potential of the barrier gate BG between the PD and the storage unit ST is set to a sufficiently high level, and charge is stored not by the storage unit ST but by the photodiode PD. When the charge accumulated in the photodiode PD reaches an appropriate level or when the integration completion operation is performed by the data request signal SHM from the AF controller 30, unnecessary charge generated in the accumulation unit ST and accumulated in the accumulation unit ST is first used. Discharges output charge when dark. This means that the potential of the barrier gate BG is maintained at the “High” level, and as shown in FIG.
By manipulating the potential of the ICG, unnecessary charges left in the accumulation unit ST are discharged. Thus the storage unit
After discharging the unnecessary charges of ST, as shown in FIG. 16 (c), the potential of the integration clear gate STICG is returned to the original high level, and then the potential of the barrier gate BG is lowered to the low level to store the photodiode PD and the accumulation. Charge transfer between the parts ST is performed (see FIG. 16 (c)). This charge transfer is
As described above, a time of about 100 μsec is required, and the time is measured and operated in the AF sensor 17. Thus the photodiode
After the transfer of the charge integrated by the PD is completed, the potential of the barrier gate BG is returned to a high level again, thereby completing the integration completion operation.

Further, after the completion of the integration completion operation, as shown in FIG. 16 (d), the potential of the storage unit ST is set to a high level,
The suppression of the generation of the dark charge is the same as after the end of the above-described ST integration mode. After waiting in this state, the shift gate SH is operated by the data request signal SHM from the AF controller 30 to transfer charges in parallel from the storage unit ST to the shift register SR, and thereafter, the operation of sequentially reading out as image information. Is also as described above.

The photoelectric conversion element array 16 shown in the block diagram of FIG.
The description of each of a to 16c is finished, and then, how the photoelectric conversion element rows 16a to 16c are controlled in the present embodiment will be described. As shown in FIG. 10, each output AGCOS1 to AGCOS3 of the monitoring photodiodes MPD1 to MPD3 in each of the three photoelectric conversion element arrays 16a to 16c.
Are provided respectively, and the barrier gates BG1 to GB3, storage units ST1 to ST3, and integration clear gates STICG1 to STICG3 of each of the islands IS1 to IS3 are controlled. One CCD clock generator 174 is provided for all islands, and controls the common transfer clocks φ ₁ and φ ₂ of the shift registers SR of all islands and the shift gates SH _{1 to} SH 3 of each island. .

Hereinafter, regarding the ST integration mode for a high-brightness subject,
This will be described with reference to the time chart of FIG. First, the AF controller 30 sets the signal line MD1 to the “Low” level and sets the signal line M to the high brightness integration mode.
D2 is set to “High” level. Next, an ICG signal (integral clear gate signal) is sent to the AF sensor 17 to start integration.
Supply. This ICG signal is supplied to the I / O control unit 175 in FIG.
Are supplied to the respective CCD integration time controllers 171 to 173. The CCD integration time controllers 171 to 173 supply the photoelectric conversion element arrays 16a to 16c with a sufficient time (about 100 μs
c), supplied as a STICG signal (ST integration clear gate signal). During this time, the photoelectric conversion element rows 16a-1
A “High” level voltage is also supplied to the barrier gates BG1 to BG3 of 6c, and the charges generated by the photodiode PD are all discharged to the overflow drain OD via the barrier gate BG, the storage unit ST, and the integration clear gate STICG. After the measurement of this time (about 100 μsec), only the STICG signal becomes “Low” level, the potential of the ST integration clear gate STICG becomes high level, and the charge generated by the photodiode PD starts to be accumulated in the accumulation unit ST. . Meanwhile, this STIC
In response to the G signal, the outputs AGCOS1 to AGCOS3 of the monitoring photodiodes MPD1 to MPD3 also start integration. The details will be described below.

FIG. 18 shows the integration of the outputs AGCOS1 to AGCOS3 of the monitoring photodiodes MPD1 to MPD3 and the generation of the voltage flag signals V _{FLG1 to VFLG1 to VGC3.
The details} of the AGC signal processing circuit 60 for obtaining _FLG3 are shown, and FIG. 19 is a time chart thereof. The AGC signal processing circuit 60 is provided in each of the CCD integration time controllers 171 to 173. When ICG signal is input, the initialization signal of the capacitor C ₁ for obtaining a drift output signal DOS DOSRS
If, in an automatic gain control output signal AGCOS initialization signal of the capacitor C ₂ to obtain AGCRS, "High" is supplied to the level of the signal, the initialization voltage [Delta] V _DOS and [Delta] V _AGC capacitor C ₁ and C ₂ is Done. At the same time, the operating point setting pulse phi _F performs an operation point setting of the inverting amplifier 64, the initialization of the capacitor C ₆ of the reference output holding unit 65 in the initialization pulse φs is also comparing circuit initialization pulse phi _FLGRS initialization of the capacitance C ₇ of 66 is performed.
The voltages ΔV _DOS and ΔV _AGC of the capacitors C ₁ and C ₂ are differentially amplified in a differential amplifying unit 61 formed by combining source followers, and an automatic gain control voltage V _AGC = 0.8 × (ΔV _AGC − ΔV _DOS ) + V ₀ is obtained. Here, V ₀ is an offset value. The automatic gain control voltage V _AGC obtained from the differential amplifier 61 and the reference voltage Vr obtained from the reference voltage generator 62 are synthesized by a voltage synthesizer 63 including capacitors C ₄ and C ₅ having the same capacitance. You. A fluctuation component of 0.8 × {(ΔV _AGC −ΔV _DOS ) −Vr} / 2 is obtained in the output voltage Vx of the voltage synthesizing circuit 63. AGCOS automatic gain control output signal
Then, ΔV _AGC = ΔV _DOS + V ₁ −AGCOS. Here, V ₁ is an offset value. From this, V _AGC = 0.8 ×
(−AGCOS) + V ₂ . Here, V ₂ (= V ₀ + 0.8 × V ₁ is also an offset value. In addition, the output voltage Vx of the voltage synthesizing circuit unit 63 has a fluctuation component of {0.8 × (−AGCOS) −Vr} / 2. In the initial state, since the reference voltage switching pulse φa is at the “High” level and φb to φe are at the “Low” level, the reference voltage Vr is the minimum reference voltage Va (= 0.375 V).
Is supplied. Voltage obtained by inverting amplifying the output voltage Vx of the voltage composition circuit portion 62 at this time by inverting amplifying portion 64 V _Y = (- 1
0) × Vx becomes the threshold level of the inversion of the voltage flag signal V _FLG , and this voltage V _Y is held in the capacitor C ₆ of the reference output holding unit 65 at the falling timing of the initialization pulse φs and supplied as the level V _YM Continue to be. Then, falling initialization pulse phi _F, the capacitance C ₄ of the voltage composition circuit portion 63, C ₅
Holds the total charge at this time. Thereafter, a level change of half of each voltage change in each of the input voltages _VAGC and Vr of the voltage synthesizing circuit unit 63 becomes a level change of the output voltage Vx. Next, the AF controller 30 sets the reference voltage Va
(= 0.375) and the initialization pulse D
After setting OSRS to “Low” level, the reference voltage Ve (= 3.375V)
The pulse φe for obtaining the “High” level and the voltage V
_In order to start monitoring whether or not the _AGC fluctuation has occurred by (Ve−Va), the initialization pulse φ _FLGRS is _set to “Low” level, the initialization pulse AGCRS is set to “Low” level, and the integration of the monitor output is started. I do. Photodiode MP for monitor
Light incident on D is photoelectrically converted, generating electrons gradually decreased from the initial value Vcc voltage [Delta] V _AGC charged in the capacitor C _2. Then, the variation of the output voltage Vx of the voltage synthesizing circuit 63 from the initial value becomes ｛−Va + 0.8 × AGCOS + Ve｝ / 2, and when the value of this equation becomes 0, the output voltage Vx of the inverting amplifier 64 becomes _Y has the same potential as the initial value _VYM, and furthermore, _VY > _VSB
When _{に な る} 0.8 × V _YM , the charge stored in the capacitor C ₇ of the comparison circuit 66 leaks through the MOS transistor Q ₆ , the voltage flag signal V _FLG is inverted, and output as a signal indicating a proper level of integration. Is done.

The AGC signal processing circuit 60 is configured by such a circuit. In the AF sensor 17 of the present embodiment, the area of the pixel photodiode PD in each island is made common, and the sensitivity of each CCD pixel is made common. In addition, by sharing the total area of the monitoring photodiodes MPD in each island, the sensitivity ratio between the pixel photodiodes PD and the monitoring photodiodes MPD in each island is shared, whereby the AGC shown in FIG.
The reference voltage generation unit 62 in the signal processing circuit 60 is shared for each island, so that power consumption of the voltage dividing resistor group R can be reduced and the chip area of the AF sensor 17 can be reduced.

The AGC signal processing circuit 60 not only controls the integration time of the CCD pixel array in each island, but also measures the maximum permissible integration time of the system in an insufficiently integrated state. Appropriate gain is given according to the monitor signal. The determination of the gain is also a role of the AGC signal processing circuit 60.

When the SHM signal for starting data reading is supplied from the AF controller 30, the CCD integration time controllers 171 to 173 start forcibly completing the integration operation, and the barrier gates BG1 to BG
G3, storage units ST1 to ST3, ST integration clear gate STICG1 to STIC
Start G3 operation. In the ST integration mode, only the operation of the barrier gates BG1 to BG3 is instantaneous.In the PD integration mode, after the SHM signal is applied, the ST integration clear gates STICG1 to STICG3 and the barrier gates BG1 to BG3 are operated. After about 100 μsec elapses, the integration completion operation ends. Subsequently, first, the shift pulse SH is used to transfer charges from the storage unit ST of the second island to the shift register SR.
2 is generated. At this point, it is necessary to store the gain of each island. Here, this shift pulse SH2
Following the occurrence of the occurrence, the reference voltage for monitoring of each island
Vr is sequentially switched using the reference voltage switching pulses φe, φd, φc, and φb, and the inversion of the voltage flag signal V _FLG is checked. Each of them is determined according to when the inversion of the voltage flag signal V _FLG occurs. The gain at the time of reading the photoelectric conversion signal of the island is determined and stored. When Vr = Ve (3.375 V), the inversion of the voltage graph signal V _FLG has already occurred, or Vr = Vd (1.87 V).
5V), when the inversion of the voltage flag signal V _FLG occurs, the gain of × 1 is memorized, and the voltage flag signal is switched at the time of switching from Vr = Vd to Vr = Vc (1.125V).
When the inversion of V _FLG occurs, the gain of × 2 is stored, and when the inversion of the voltage flag signal V _FLG occurs at the time of switching from Vr = Vc to Vr = Vb (0.75V), the gain is × 4. If the inversion of the voltage graph signal V _FLG does not occur even when Vr = Vb, the gain of × 8 is stored. In this way, the gains are determined simultaneously by the AGC signal processing circuits 60 of the first, second, and third islands and stored. When the pixel data of each island is read out, the stored gains are respectively adjusted as shown in FIG. And the most appropriate gain is supplied to the output of each island. The gain information of each of these islands is output as digital data in synchronization with the ADT signal immediately after the start of the data dump to the AF controller 30 from the ICG and SHM signal lines.

The AGC signal processing circuit 60 as described above is provided in each of the CCD integration time controllers 171 to 173, and each of the monitor outputs AGCOS1 to AGCOS3 determines whether or not an appropriate level has been reached.
The signal is constantly monitored by the signal processing circuit 60, a predetermined level fluctuation occurs, and when it is detected that any of the CCD integration time control units 171 to 173 has reached the appropriate level, each of the islands IS1 to IS3 is Voltage flag signals V _{FLG1 to} V
_FLG3 is inverted. In the operation example shown in FIG. 17, first, the voltage flag signal V _FLG2 is inverted in the second island. At this time, the CCD integration time control unit 172 outputs the “High” level signal from the integration clear operation.
ADT that inverts G2 to “Low” level, shuts off the charge inflow between the photodiode PD and the storage unit ST, performs the integration completion operation, and maintains the “High” level from the time when the integration is cleared.
By supplying a “Low” level pulse signal to the signal,
The AF controller 30 is notified that the integration of the two islands has been completed. The AF controller 30 inputs the falling edge of the ADT signal as an interrupt signal, and performs ADT interrupt processing (described later in FIG. 25).
Is performed, the completion of integration of one island can be recognized.

In the case of the other islands, that is, in the case of FIG. 17 (a), the barrier gate signals BG1 and BG3 are kept at the "High" level regardless of the operation of the second island for the first and third islands. (This operation is limited to the ST integration mode. In the PD integration mode described later, integration of all islands is stopped at the same time.) 17th
In the operation example of FIG. 7A, the voltage flag signal V _FLG1 of the first island is inverted after the second island. Also in this case, similarly to the case of the second island, a low-level pulse is output to the ADT signal and the barrier gate signal is output.
BG1 is inverted, the connection between the photodiode PD and the storage unit ST is cut off, and the integration completion operation is performed. The AF controller 30
The completion of the integration of the second island is recognized by the fall of the ADT signal. Finally, the third island voltage flag signal V
_{If FLG3} is inverted before the maximum permissible integration time ( _{20 msec in} ST integration mode) has elapsed, the ADT signal is held at “Low” level, the barrier gate signal BG3 is set at “Low” level, and the photodiode PD and the storage Cut off between ST and complete integration. The AF controller 30 repeatedly detects the ADT signal at a period slightly longer than the pulse width indicating the completion of the first and second integrations, thereby detecting that the “Low” level signal is continuously output. , It can be recognized that the integration of all islands has been completed.

At this time, a charge amount of a level suitable for the analog signal processing unit 176 at the subsequent stage is prepared and held in the storage units of the photoelectric conversion element arrays 16a to 16c of all islands.

Next, the AF controller 30 outputs the SHM signal serving as a data request signal.
The signal is supplied to the AF sensor 17. This SHM signal is
Through the I / O control unit 175 shown in FIG.
3 and the CCD clock generator 174. As shown in the time chart of FIG. 17, when the integration operation is automatically completed by the CCD integration time controllers 171 to 173 before the supply of the SHM signal in all islands, the CCD integration time controller 1
71 to 173 do not operate on this SHM signal. Meanwhile, CCD
Clock generating unit 174, an internal counter is initialized by the SHM signal, and starts counting the input pulses CP from this point, the "High" level transfer clock phi _1, the transfer clock phi ₂ to the "Low" level First, the shift gate pulse SH2 is supplied. This shift gate pulse S
By the application of H2, the charges held in the respective storage units ST2 of the second island are transferred to the shift register SR2 of the second island. After the completion of the application of the shift gate pulse SH2, the transfer clocks φ ₁ and φ ₂ are restarted, and the transfer clocks φ ₁ and φ ₂
The CCD shift register SR2 sequentially transfers the photoelectric charge generated by the photoelectric conversion unit of the second island as the output signal OS2 in synchronization with the control signal. The CCD clock generator 174 counts the number of transfer clocks of the CCD, and sends it to the analog signal processor 176. Further, the CCD of the 7th to 9th pixels shown in FIG.
When an analog signal is output from the dark output pixel, a control signal for level clamping is supplied to the analog signal processing unit 176 in order to clamp the dark output level to the A / D conversion reference voltage Vref.

The details of the analog signal processing unit 176 are shown in FIG. 20, and the operation timing thereof is shown in FIG. Analog signal processing unit 17
6 includes buffers 71 to 73 that receive the output signals OS1 to OS3 of the respective photoelectric conversion element arrays 16a to 16c, and one of the outputs of the buffers 71 to 73 outputs one of the analog switches AS1 to AS3 according to the output timing. AGC amplifier 74
Is input to The output of the AGC amplifier 74 is sampled and held by the sample and hold circuit 75, and the level clamp circuit
At 76, the reference level is clamped to the reference voltage Vref and output as the output signal Vos. The level clamp circuit 76 has C
Control signal C for level clamp from CD clock generator 174
E1, CE2, ARS3, ARS4, CL1, CL2 are supplied.

Also, the CCD clock generator 174 outputs the ADT signal to the I / O controller 17.
Output via 5. This ADT signal is output as a signal indicating switching of one pixel of the CCD data and one pixel, and A / D
The converter 31 starts A / D conversion at the falling edge of the ADT signal. FIG. 22 is a time chart showing the operation of the CCD transfer clocks φ ₁ and φ ₂ and the signals synchronized with the clocks. As shown in FIG. 17 (a), the ADT signal is output when a falling pulse indicating the completion of integration of each island is output, when digital data is output using the ICG and SHM signal lines, and when an effective pixel is output. Only when outputting, it is output as a signal synchronized with the CCD transfer clock, and when outputting invalid pixels.
It is masked by the value of the counter in the CCD clock generator 174 and is not output. For this reason, AF controller 30
Side without determining whether it is a valid pixel or an invalid pixel.
A / D conversion data can be captured.

Thus, the image signal photoelectrically converted by the second island is output as the output signal Vos in the order of the reference section and the reference section. This image signal is an output obtained by clamping the dark output level generated during the integration time of the second island to the reference voltage Vref. Next, it is necessary to read an image signal photoelectrically converted in the first island. Therefore, as shown in FIG. 22, clock phi ₁ when the output of the 48-th pixel data of the reference unit the output of the second island generates a SH1 signal at "High" level of the phase. This timing is also derived from the value of the counter in the CCD clock generator 174. The reason why the SH1 signal is generated at this point is that a blank feed pixel having no pixel exists at the head of the CCD output as shown in FIG. 13, and this is to shorten the output time of the blank feed pixel. .
After the generation of the SH1 signal, when the output of the 52nd pixel data of the reference section in the second island is completed, the CCD clock generation section 174 sets the AS2 signal for controlling the opening and closing of the analog switch AS2 in the analog signal processing section 176 to “High”. AS1 signal changes from "Low" level to "High" level from "Low" level
The level is switched to the level, and the data of the first island is supplied to the analog signal processing unit 176. Thereafter, similarly to the data output of the second island, after performing the sample-and-hold of the dark output, the dark output level generated during the integration time of the first island is converted from the analog signal Vout to the A / D conversion reference voltage. Vre
The reference portion and the reference portion are output in this order as an output clamped to f. Next, by performing exactly the same processing as when switching the output from the second island to the first island, the output is switched from the first island to the third island, and the data output of the third island is performed. Thus, the output of the data is completed, and the process proceeds to the next integration.

In the analog signal processing unit 176 shown in FIG. 20, the output signal Vos is indefinite during the integration time and during the dark output level clamping operation, and thus is not suitable as a signal supplied to the outside. For this reason, during these phases, the temperature data V _{TEMP obtained} by dividing the A / D conversion reference voltage Vref by resistors having different temperature coefficients is used as the output signal Vout.
The CD clock generator 174 is controlling. Temperature data V _TEMP
Are supplied to the analog signal processing unit 176 from the temperature detection unit 177 shown in FIG.

Next, in the PD integration mode for a low-brightness subject, since the brightness is long and the integration time is long, priority is given to the speed of the entire system, and as shown in FIG.
0msec) or the first ADT signal is sent to the AF sensor 17
, The SHM signal is supplied from the AF controller 30 to the AF sensor 17, and the integration operation in all the islands IS1 to IS3 is completed at the same time. Except for this point, the operation is substantially the same as that of the above-described ST integration mode, and thus the overlapping description will be omitted, and the description of each operation of the ST integration mode and the PD integration mode will be completed.

By the way, the voltage flag signals V _{FLG1 to} V _FLG3 of each island in the above-mentioned AGC signal processing circuit 60 are output as the falling edge of the ADT signal, and make the AF controller 30 recognize the timing of the completion of the integration. But AF controller 30
Can only recognize that the integration completion operation has been performed in any of the islands by the ADT signal, and it is not possible to recognize only the island where the integration completion operation was performed from the ADT signal. Can not.
Then, using the digital data at the time of the subsequent data dump, the AF controller 30 determines the order of completion of integration for each island.
To be recognized. Thereby, the AF controller 30 can know the timing of the completion of integration in each island and the order of completion of integration, and based on these information, corrects the lens movement amount during the integration time and during the focus detection calculation. It can be performed. In other words, when the lens is moved for automatic focus adjustment, the integration time by the AF sensor 17 and the result of the focus detection calculation based on the effective pixel output of the AF sensor 17,
There is a time difference between the time when the further lens driving amount is calculated, and it is necessary to correct the lens moving amount during this time. In the ST integration mode in which the integration completion time differs for each island, the correction amount of the lens movement amount differs for each island.

Hereinafter, the focus detection operation during lens driving will be described with reference to the time chart of FIG. Now, in a state in which the lens is driven at a constant speed, the image projected on the AF sensor 17 is also an image that transitions at any time according to the lens driving, and the image interval is also calculated. However, as long as there is no change in subject brightness, the AF
This corresponds to the image interval obtained at the midpoint of the integration interval of the sensor 17. Now begins the integration from the time t _0, the first island at time t _1, the third island at time t _2, the at time t ₃ when the integral of the second island is to complete each of which is calculated at time t ₄ result of focus detection calculation is calculated as the defocus amount df ₁ ~df ₃ shown based on image distance at different time points in each island. That is, at the first island, the time I1 =
(T ₀ + t ₁ ) / 2, at the second island, time I 2 = (t ₀ + t ₃ )
/ 2, in the third island, the defocus amount for each island based on the image interval at the time I3 = (t ₀ + t ₂ ) / 2
df ₁ ~df ₃ is calculated. In terms of the number of drive pulses based on this value df ₁ ~df _3, respectively N1~N3 are calculated.
However, the number of drive pulses N1 to N3 calculated here is the number of drive pulses required at the integration center (time I1 to I3 at the middle point of the integration section) for each island described above. remaining driving pulses the number R1 of the arithmetic completion t ₄
It is necessary to convert to ~ R3. Therefore, at times t ₀ , t ₁ , t ₂ ,
There pulse count value showing the lens driving amount necessary to memory the counter register CT (1) ~CT (4) the in each t _3. The pulse count values indicating the lens drive amount at each point are represented by P (t ₀ ), P (t ₁ ), P (t ₂ ), P
(T ₃ ), assuming that the pulse count value indicating the current lens drive amount is P (t ₄ ), the remaining drive pulse numbers R 1 to R 3 in each of the islands IS 1 to IS 3 are focus-detected from each of the integration centers I 1 to I 3. each drive pulse count up operation completion t _4, the number of drive pulses calculated by the focus detection computing N1~
It becomes the value which subtracted from N3, and it becomes each following formula.

_{R1 = N1 + P (t 4} ) - {P (t 0) + P (t 1)} / 2 R2 = N2 + P (t 4) - {P (t 0) + P (t 3)} / 2 R3 = N3 + P (t 4 ) − {P (t ₀ ) + P (t ₂ )} / 2 Each island IS first seen from the same point
The defocus amount of 1 to IS3 (converted to the pulse count number R1 to R3 at this time) is calculated, and each island is defocused.
At this point, it is determined which of the islands IS1 to IS3 should be driven according to the defocus amount of the island.

In the time chart of FIG. 23, the signal is transmitted between the AF sensor 17 and the AF controller 30 as described above.
ICG signal, SHM signal and voltage flag signal in AF sensor 17
Changes in V _{FLG1 to} V _FLG3 are shown.

Here, the integration completion signal of each island is recognized by the AF controller 30 as the falling point of the ADT signal, and the ADT signal is changed three times to “Low” level. The AF controller 30 recognizes that the integration of all the islands has been completed by detecting that the signal is held at the “Low” level. At this time, all of the voltage flag signals V _{FLG1 to} V _FLG3 are inverted, and the six D flip-flops FF12 and FF1 provided in the I / O control unit 175 are inverted.
The order of integration completion is stored in 3, FF21, FF23, FF31, FF32. In the operation example shown in FIG. 23, inverted at time t ₁ from the voltage flag signal V _FLG1 is "High" level to the "Low" level, this time, D flip-flop FF 21, FF 31 clock input
CK rises from “Low” level to “High” level,
Voltage flag signals V _FLG2 , V applied to the data input D
The “High” level signal of _FLG3 is latched at each output Q. As a result, the D flip-flops FF21 and FF31 memorize that the integration completion time of the first island is earlier than the integration completion time of the second and third islands. Then, the voltage flag signal V _FLG3 from "High" level at time t ₂ "Lo
w "level, and at this time, the D flip-flop FF1
3, FF 23 clock input CK is risen to "High" level from "Low" level, the data input voltage flag signal V _FLG1 is applied to D "Low" and the level of the signal, the voltage flag signal V _FLG2 " A High level signal is latched at each output Q. As a result, the D flip-flops FF13, FF23
Stores that the integration completion time of the third island is later than the integration completion time of the first island and earlier than the integration completion time of the second island. Further, inverted at time t ₃ the voltage flag signal V _FLG2 from "High" level to the "Low" level, this time, the D flip-flop FF12, FF 32 clock input CK is "Low" level to "High" level After rising, the "Low" level signals of the voltage flag signals V _FLG1 and V _FLG3 applied to the data input D are latched at the output Q. As a result, the D flip-flops FF12, FF32
Stores that the integration completion time of the second island is later than the integration completion time of the first and third islands.

The outputs Q of these six D flip-flops are transmitted as digital data together with the gain information of each island from the AF sensor 17 to the AF controller 30 via the signal lines ICG and SHM immediately after the start of the data dump.

A flowchart for performing the above-described lens movement amount correction will be described with reference to FIG. First, when the first focus detection is started, the lens is not driven and the memory values of the counter registers CT (I) are the same, so that the lens movement amount correction is not performed and the defocus amounts df _{1 to} df _{According to 3} ,
The drive pulse numbers N1 to N3 are calculated, set as they are in the lens drive pulse counter, and the lens drive is started. After that, the second integration of the AF sensor 17 is started. FIG. 25 shows the processing after the start of AF during the second and subsequent lens driving. Each time the pulse corresponding to the lens drive amount is obtained from the encoder 44, the pulse counter for the lens drive decrements the pulse count value by one. The AF controller 30 first stores the pulse count value P (t ₀ ) in the first counter register CT (1) at the integration start time t ₀ of the AF sensor 17, and then uses the ADT signal for recognizing the completion of integration. Interrupts are permitted, and it is continuously checked whether the maximum integration time of 20 msec in the ST integration mode and 100 msec in the PD integration mode has elapsed (# 1, # 2). When the subject is in the bright ST integration mode, each island automatically completes the integration one after another, and the electric charge is held in the storage unit ST. Each time, the ADT signal becomes “Low” level, and the division by the ADT signal is performed. Is called. In the ADT interrupt routine, first, it is determined whether the mode is the ST integration mode or the PD integration mode (♯1
Five). As described above, this is because, in the ST integration mode, the monitor output AGCO of each of the photoelectric conversion element rows 16a to 16c is set.
According to S1 to AGCOS3, charge is accumulated at different integration times, and AD
The T signal falls at the timing when the three islands IS1 to IS3 complete integration, respectively, and the interrupt routine of the ADT signal is called. In the PD integration mode, the same signal follows the falling point of the ADT signal from the brightest island ISn. This is because the charge is accumulated during the integration time, so that the interrupt routine of the ADT signal is called only once.

The switching of the integration mode is described in FIG.
These are shown in # 20 to # 25. In the figure, TINT means integration time. First, when AF is started, the photoelectric conversion element array is initialized, and then the PD integration mode with a maximum integration time of 20 msec is set. Then, when the integration is completed within 1 msec, since the amount of excessive integration due to the integration completion operation after inverting the voltage flag signal V _FLG of the PD integration is large, re-integration is performed with the integration mode set to the ST integration mode (♯ 20, 21).
Next, when the integration time is 10 msec or less, the subsequent integration mode is set to the ST integration mode, and the flow proceeds to the focus detection calculation (検 出 2
2, 23). If the gain information of all islands is twice or more, the maximum integration time is changed to 100 msec while the integration mode remains in the PD integration mode, and the focus detection calculation is started (# 24, # 25). Finally, when none of these conditions is satisfied, the integration mode proceeds to the focus detection calculation as it is.

The switching of these integration modes is performed every time the integration of the photoelectric conversion element array is completed, and once the mode is the ST integration mode, that is, when the integration time becomes 10 msec or less,
The ST integration mode is continued until the integration time of all islands becomes 20 msec and the gain becomes twice or more, and once the PD integration mode is set, that is, the gain becomes twice or more with the integration time of all islands being 20 msec. In this case, the PD integration mode is continued until the integration time of one island falls below 10 msec.

As described above, when the integration mode is entered once, by providing hysteresis in the switching condition so that the integration mode is continued, stable data can be obtained in the same integration mode.

First, in the case of the ST integration mode, at the time of the first ADT interrupt and at the time of the second ADT interrupt, the remaining driving pulse numbers P (t ₁ ), P (t) at the time of occurrence of the interrupts t ₁ and t _2. t ₂ ) is stored in the second counter register CT (2) and the third counter register CT (3), respectively (# 16), and after the counter register number I is incremented by one, the maximum integration time of $ 2 Return to progress check (# 17, # 18). When the third ADT interrupt occurs and the integration of all the islands is completed, the fourth counter register CT (4) stores the remaining drive pulse number P at that time.
After storing (t ₃ ), SHM to start data dump
Proceed to signal supply (# 3).

On the other hand, in the PD integration mode, the integration complete operation of all islands is performed when the first ADT interrupt occurs. Therefore, when an ADT signal interrupt occurs, the second, third, and fourth counter registers CT (2) After the pulse count value P (t) at the ADT interrupt occurrence time t is stored in .about.CT (4) (# 19), the process proceeds to supply of the SHM signal for data dump (# 3).
On the other hand, if the integration of all islands is not completed even after the maximum integration time has elapsed in # 2, the SHM signal for data dump is supplied in # 3, and the ADT signal is set to "Low" level in # 4. Check that the pulse count value at that time is stored in the second to fourth counter registers CT (2) to CT (4) that have not been stored yet in steps # 5 to # 7. Then, it proceeds to the data dump (# 8).

Next, the AF sensor 17 synchronizes with the ADT signal to the signal line I.
It outputs AGC data from CG and SHM and digital data indicating the order of completion of integration of each island.
Inputs the digital data. Then the AF sensor
From 17 the analog signal output of each photoelectric conversion element 16a ~ 16c,
Since the signal is output from the analog signal line Vout, the AF controller 30 A / D converts the analog signal output in synchronization with the ADT signal and sequentially inputs the analog signal output (# 8). A / D conversion is performed on all outputs from the AF sensor 17, and when data input is completed, focus detection calculation is performed for each island according to the outputs of the photoelectric conversion element rows 16a to 16c, and the defocus amounts df1 to df3 is calculated (# 9). Next, the order of completion of integration of each island is determined based on digital data from the AF sensor 17 in order to correct the movement amount during lens driving for the calculated defocus amounts df1 to df3 of each island ( ♯10). Then converted to the drive pulse number N1~N3 using the defocus amount df1~df3 lens data calculated for each island (conversion coefficient K _L) (♯11). next,
The number of drive pulses from the integration centers I1 to I3 of each island to the completion of the focus detection calculation is calculated. These are the second to fourth counters CT (2) to CT from the integration completion order of each island.
One of CT (I) is selected from (4), and lens movement correction amount ΔN (I) = CT (5) − ｛CT (1) + CT
(I)｝ / 2 is calculated respectively. The sign of ΔN (I) is negative. In the operation example of FIG. 23, the lens movement correction amounts ΔN (I) for the drive pulse numbers N1, N2, N3 of the first, second, and third islands are ΔN (2), ΔN (4), ΔN
(3). This lens movement correction amount ΔN (I) is added to the number N1 to N3 of drive pulses of each island, and the remaining drive pulses R1 to R3 of each island are calculated (# 12). And
From the remaining drive pulse numbers R1 to R3, the drive pulse number R0 for the next lens drive is selected (# 13). The lens driving (# 14) is performed according to the driving pulse number R0, and the next CCD integration (# 1) is started.

[Effects of the Invention] As described above, in the present invention, in a charge storage type photoelectric conversion device including a plurality of light receiving element rows, the charge storage time is individually controlled for each light receiving element row according to the amount of incident light. Therefore, the output of the charge storage element array corresponding to each light receiving element does not saturate or the output becomes low and the S / N ratio does not deteriorate, and the appropriate control of the charge storage time becomes possible. This has the effect. In particular, in the present invention, since the charge storage element row where charge accumulation has been completed is cut off from the light receiving element row by the gate element row, the charge accumulation in the charge storage element row is read out by the scanning means. In addition, the area and potential of the charge storage element row can be designed so that the generation of dark charge is minimized, and the S / N ratio can be improved.

A light receiving element for generating a dark output is provided for each light receiving element row, and a difference output between a dark output from the light receiving element for generating a dark output and an output from another light receiving element is obtained. For example, the signal charge can be read out without being affected by the dark charge, and the S / N ratio can be further improved.

In addition, a charge transfer register for reading the stored charge from each charge storage element row is provided, and after all the charge storage element rows have completed the charge storage operation, the charge storage element row is connected in parallel to each transfer stage of the charge transfer register. If charge is transferred from the charge transfer register to which charge has been transferred in a serial manner and stored charge is read out in series, a signal is sent to the charge storage element row in a state where little dark charge is generated until immediately before reading the stored charge. Since the charge can be held, it is possible to prevent a decrease in the S / N ratio of the charge storage element array that has already finished the charge storage operation and is on standby.

[Brief description of the drawings]

1 is a schematic configuration diagram of the present invention, FIG. 2 is a perspective view of a focus detection optical system in a camera using a photoelectric conversion device according to an embodiment of the present invention, and FIG. FIG. 4 is a view showing a display in a finder of the camera of the above, and FIG. 5 is a view showing a CC used in the photoelectric conversion device of the above.
FIG. 6 is an explanatory view showing details of a D chip, FIG. 6 is an explanatory view showing a divided area of a reference portion in the above-described CCD chip, FIG.
FIG. 9 is an explanatory diagram showing a shift amount for each divided region in the CCD chip of the above, FIG. 9 is a block circuit diagram of an AF sensor and an AF controller for realizing the photoelectric conversion device of the above,
FIG. 10 is a block circuit diagram of the AF sensor of the above embodiment, FIG. 11 is a diagram showing a main part configuration of a photoelectric conversion element array used in the above embodiment, and FIG.
FIG. 13 is a cross-sectional view taken along the line CC ′ of the above, FIG. 13 is a view showing the entire configuration of the photoelectric conversion element row of the above, and FIGS.
FIG. 17 is an explanatory view showing different integration modes of the above photoelectric conversion device, FIG. 17 (a) is an operation waveform diagram of the same photoelectric conversion device in the ST integration mode and the data dump mode, and FIG. Operation waveform chart of PD integration mode and data dump mode of photoelectric conversion device, Fig. 18 shows AGC used for AF sensor same as above
FIG. 19 is a circuit diagram of the signal processing circuit, and FIG.
FIG. 20 is a circuit diagram of an analog signal processing unit used for the AF sensor of the above, FIGS. 21 and 22 are operation waveform diagrams of the above, and FIG. 23 is for explaining signal transmission between the AF sensor and the AF controller of the above. FIG. 24 is a circuit diagram of an integration completion order storage circuit used for the AF sensor of the above, and FIG. 25 is a circuit diagram of the same.
5 is a flowchart showing the operation of the main part of the AF controller. 1a to 1c are light receiving element rows, 2a to 2c are charge storage element rows, 3a to 3c
Denotes a gate element row, 4a to 4c denote scanning means, and 5a to 5c denote accumulation time control means.

Continuation of the front page (56) References JP-A-60-121409 (JP, A) JP-A-60-125817 (JP, A) JP-A-60-241007 (JP, A) JP-A-60-256279 (JP, A) JP-A-59-60303 (JP, A) JP-A-56-108903 (JP, A) JP-A-48-38920 (JP, A) JP-A-60-176370 (JP, A)

Claims (6)

(57) [Claims] 1. A plurality of light receiving element rows, a plurality of charge storage element rows provided corresponding to each light receiving element row, and a charge inflow from each light receiving element row to a corresponding charge storage element row can be cut off. A plurality of gate element arrays, scanning means for serially reading the accumulated charges of each charge storage element array, and controlling the corresponding gate element array in a cut-off state in accordance with the amount of light incident on each light receiving element array A charge storage type photoelectric conversion device comprising: storage time control means for individually controlling a charge storage time for each light receiving element row. A plurality of charge transfer registers provided corresponding to each charge storage element column; a plurality of output means provided at a transfer end stage of each charge transfer register; Selecting means for selecting one of them, a charge transfer element row for transferring stored charge from each charge storage element row to each transfer stage of the corresponding charge transfer register in parallel, and a charge storage operation of all charge storage element rows. After the completion of the above, the charge transfer signal is sequentially supplied to each charge transfer element column, and the output means provided at the transfer end stage of the charge transfer register corresponding to the charge transfer element column supplied with the charge transfer signal is selected. 2. The charge storage type photoelectric conversion device according to claim 1, further comprising control means for controlling the selection means. 3. The charge storage type photoelectric conversion device according to claim 1, wherein each light receiving element row includes a light receiving element for generating a dark output. 4. A charge storage type storage device according to claim 3, further comprising a difference means for obtaining a difference output between a dark output from the light receiving element for generating a dark output and an output from another light receiving element. Photoelectric conversion device. 5. The storage time control means controls all the gate element rows to charge inflow state simultaneously, and individually cuts off the corresponding gate element rows after a lapse of charge storage time corresponding to the amount of light incident on each light receiving element row. 2. The charge storage type photoelectric conversion device according to claim 1, wherein the charge storage type photoelectric conversion device is a means for controlling a state. 6. The charge storage type photoelectric conversion device according to claim 1, wherein said storage time control means includes a monitor circuit for detecting the amount of light incident on each light receiving element row for each light receiving element row.