JP4086339B2 - camera - Google Patents

Description

但し、ｘ，ｙ，ｚは３軸座標であり、数１式は２次曲線を表す式であり、ｋ＝０で球面を、ｋ＝−１で放物面を、ｋ＞−１で回転楕円面となる。また、ｈ²＝ｙ²＋ｚ²であり、ｒは軸上の曲率を表す。通常のカメラと対物レンズ（撮影レンズ）を想定した場合、ｒとｋの範囲は、
−２０≦ ｒ ≦２０ −１＜ ｋ ≦−０.２
程度が好ましい。
【００２５】
また本実施形態においては、２次結像系９の第一面を凹面形状とすることで、２次結像系９に入射する光が無理に屈折されることがないような構成とし、光電変換素子１１の二次元領域の広い範囲にわたって良好で一様な結像性能を確保している。
【００２６】
このようにして得られた２つの光量分布に対して、分離方向、即ち図３に示す２つのエリアセンサ１１−１，１１−２の図上、上下方向の相対的位置関係をエリアセンサ１１−１，１１−２の各位置で算出することで、対物レンズの焦点状態を二次元的に検出することができる。尚、第１の反射鏡４は、撮影に際し、主ミラー３と同様に撮影光路外に退避されるものである。
【００２７】
次に光電変換素子１１及びその駆動制御回路について説明する。図４は光電変換素子１１とその駆動制御回路を１チップにした集積回路（ＩＣＣ）４０のブロック構成図である。
【００２８】
図において、４１は光電変換素子部であり、図３の光電変換素子１１に示したような対のエリアセンサ部１１ー１，１１ー２となっている。このエリアセンサ部１１ー１，１１ー２は、図２１に示した様に例えばジグザグに分割した各領域でそれぞれ独立に最適な蓄積終了レベルとなるように制御されている。
【００２９】
また、４２は光電変換素子部４１のエリアセンサ部の蓄積、出力制御を行うアナログ回路部で、主に蓄積終了判断のレベル設定、比較動作と蓄積電荷のノイズキャンセルやアナログ出力への適正なゲインを検出・制御・伝送している。
【００３０】
また、４３はアナログ回路部４２に対してエリアセンサ部の蓄積、出力制御のロジック制御部で、先述したように各分割領域が最適レベルで蓄積終了となるような順次走査での蓄積制御や、計時された蓄積時間情報の保存動作を行っている。即ち、個々の領域に関しての図１２，図１３，図１４に示した様な、
Ｖ_R ＝Ｖ_P −Ｖ_D
となる蓄積制御部による判断を短時間に順次行い、蓄積終了時点で計時された蓄積時間の保存を行っている。
【００３１】
図５は、図４に示すアナログ回路部４２とロジック制御部４３による蓄積制御動作を説明するための概要図である。図２０とは異なり、各分割領域（対）毎に最大値検出回路部１〜ｎと差動アンプＡＰ１〜ＡＰｎを有し、各差動アンプＡＰ１〜ＡＰｎの出力が共通の所定レベルＶRに達するまで蓄積を行い、到達を判断された時点で、蓄積動作を終了し、読出し信号ΦRが各分割領域毎に送られ、読出し信号ΦR1〜nとなる。ｎは領域分割数で、図２１に示した分割形態であるならば、ｎ＝２７となる。
【００３２】
ここで、各分割領域毎の独立蓄積制御を可能にしながら、回路規模の縮小を図るため、図５中の制御回路Ａ１が各分割領域毎に設けられたアナログスイッチ対ＡＳ１ａ，ＡＳ１ｂ〜ＡＳｎａ，ＡＳｎｂを基準クロック信号ＩＣＬＫに基づいた領域選択タイミング信号ｓ１〜ｓｎにより順次走査し、共通のコンパレータＣＯＭで全領域の蓄積終了判断を行っている。さらに、コンパレータＣＯＭの出力を共通のマスク信号ＣＯＭＫとＡＮＤゲートによりマスクし、各領域毎の判断が正しく行われるようにしている。なお、図３及び図４における２つのエリアセンサ部１１−１，１１−２は同時に、そして各分割領域対においては共通信号（各分割領域対毎の最大出力値）に基づいて制御されている。
【００３３】
図６は、図５における各信号のタイミングチャートである。図において、ＩＣＬＫは後述する蓄積時間制御部の発振クロックを蓄積制御用基準クロックとして用いたものである。ＣＯＭＫは前述したように共通コンパレータＣＯＭの出力をマスクするためのマスク信号で、図６ではＩＣＬＫを４分周して生成している。このＣＯＭＫ信号がHigh（高レベル）のとき、図６のコンパレータＣＯＭの出力が有効になる。
【００３４】
次に、領域選択タイミング信号ｓ１〜ｓｎは、マスク信号ＣＯＭＫに対し、さらにｎ分周された領域選択信号で、各領域（１〜ｎ）の蓄積終了判断動作のタイミング信号となる。この信号がHighのとき、各選択領域に対応した最大値検出回路部と差動アンプ（ＡＰ１〜ｎ）、及びアナログスイッチ対（ＡＳ１ａ，ＡＳ１ｂ〜ＡＳｎａ，ＡＳｎｂ）が有効となり、選択された領域のみの蓄積終了判断が行われ、蓄積終了ならば読出し信号ΦRが各分割領域毎に送られ、読出し信号ΦR1〜nとなる。
【００３５】
この蓄積終了、読出し信号ΦRは、図４のＳＲＡＭ４４にも送られ、領域選択タイミング信号ｓ１〜ｓｎと合わせて、各分割領域の蓄積終了信号tr1〜trnとして保持される。これは、分割領域選択タイミング信号ｓ１〜ｓｎがいったん蓄積終了した領域に対して出力されないようにするためである。図６では、領域１は２回目、領域２は１回目の走査で蓄積終了しているが、領域３は２回の走査では蓄積終了していない。
【００３６】
一方、４４はＳＲＡＭ（Static Randum Access Memory）部で、前記各分割領域毎の蓄積時間情報を記憶している。
【００３７】
また、４５は通信制御部で、ＩＣＣ４０とカメラ全体の制御を司るマイクロコンピュータ等へ先述の各分割領域毎の蓄積時間など各種情報を送信したり、焦点検出の指示等の制御通信を受けている。
【００３８】
また、４６は蓄積時間制御部で、前述の各分割領域毎の蓄積時間を計時しており、その結果はＳＲＡＭ４４に保存されている。
【００３９】
また、４７はＩＣＣ４０の電源回路部で、各部への適切な電圧と電流による動作電力の供給や蓄積終了レベルの設定、出力も行っている。
【００４０】
次に、図７は図４での蓄積時間制御部４６の発振回路部付近の簡単な構成説明図で、水晶や圧電素子の振動子５１、負荷容量５２，５３及び発振用抵抗５４は通常外付け部品で、発振用インバータ５５とともに発振回路を構成している。バッファ５６を経て、必要に応じて分周回路５７を通してクロックカウンタ５８で蓄積開始からの経過時間を計測する。なお、発振クロックは前述したようにそのまま蓄積制御用基準クロックや駆動用クロックとしても用いている。
【００４１】
上記したカウンタ５８の出力はセンサの各分割領域毎に、蓄積終了とともに図４のＳＲＡＭ４４に設定されている各分割領域の対応領域に書き込まれる。これにより、全分割領域個々の蓄積時間がディジタル情報として素子内に記憶される。また、必要に応じて、図４の通信制御部４５を介してディジタル情報の形で、カメラ内部の不図示のマイクロコンピュータに通信される。そして各種像信号の補正、例えばセンサの暗電流が蓄積時間と共に変化する場合は蓄積時間に応じた補正値を求めるためにカウンタ５８の出力が用いられる。
【００４２】
なお、図７の分周回路５７の分周比はＳＲＡＭ４４の記憶容量と蓄積時間情報としての必要な分解能により、発振子５１による発振周波数とともに最適に設定されている。
【００４３】
［第２の実施形態］
図８は上記のごとき各実施形態に示した各焦点検出装置を備えたカメラの具体的な構成の一例を示す回路図であり、先ず各部の構成について説明する。
【００４４】
図８において、ＰＲＳはカメラの制御装置で、例えば、内部にＣＰＵ（中央処理装置）、ＲＯＭ、ＲＡＭ、Ａ／Ｄ、Ｄ／Ａ変換機能を有する１チップのマイクロコンピュータである。マイクロコンピュータＰＲＳはＲＯＭに格納されたカメラのシーケンス・プログラムに従って、自動露出制御機能、自動焦点調節機能、フィルムの巻き上げ・巻き戻し等のカメラの一連の動作を行っている。そのために、マイクロコンピュータＰＲＳは通信用信号ＳＯ、ＳＩ、ＳＣＬＫ、通信選択信号ＣＬＣＭ、ＣＤＤＲ、ＣＩＣＣを用いて、カメラ本体内の周辺回路およびレンズ内制御装置と通信を行って、各々の回路やレンズの動作を制御する。
【００４５】
ＳＯはマイクロコンピュータＰＲＳから出力されるデータ信号、ＳＩはマイクロコンピュータＰＲＳに入力されるデータ信号、ＳＣＬＫは信号ＳＯ、ＳＩの同期クロックである。
【００４６】
ＬＣＭはレンズ通信バッファ回路であり、カメラが動作中のときにはレンズ用電源端子ＶＬに電力を供給するとともに、マイクロコンピュータＰＲＳからの選択信号ＣＬＣＭが高電位レベル（以下、‘Ｈ’と略記し、低電位レベルは‘Ｌ’と略記する）のときには、カメラとレンズ間の通信バッファとなる。
【００４７】
マイクロコンピュータＰＲＳが選択信号ＣＬＣＭを‘Ｈ’にして、同期クロックＳＣＬＫに同期して所定のデータをデータ信号ＳＯから送出すると、レンズ通信バッファ回路ＬＣＭはカメラ・レンズ間通信接点を介して、同期クロックＳＣＬＫ、データ信号ＳＯの各々のバッファ信号ＬＣＫ、ＤＣＬをレンズへ出力する。それと同時に、レンズＬＮＳからの信号ＤＬＣのバッファ信号をデータ信号ＳＩに出力し、マイクロコンピュータＰＲＳは同期クロックＳＣＬＫに同期してデータ信号ＳＩからレンズのデータを入力する。
【００４８】
ＤＤＲは各種のスイッチＳＷＳの検知および表示用回路であり、信号ＣＤＤＲが‘Ｈ’のとき選択され、データ信号ＳＯ、ＳＩ、同期クロックＳＣＬＫを用いてマイクロコンピュータＰＲＳから制御される。即ち、マイクロコンピュータＰＲＳから送られてくるデータに基づいてカメラの表示部材ＤＳＰの表示を切り替えたり、カメラの各種操作部材のオン・オフ状態を通信によってマイクロコンピュータＰＲＳに報知する。ＯＬＣはカメラ上部に位置する外部液晶表示装置であり、ＩＬＣはファインダ内部液晶表示装置である。本実施形態では、焦点検出の動作領域の設定等は、この検知および表示用回路ＤＤＲに属するスイッチＳＷＳにて行っている。
【００４９】
ＳＷ１、ＳＷ２は不図示のレリーズボタンに連動したスイッチで、レリーズボタンの第一段階の押下によりＳＷ１がオンし、引き続いて第２段階の押下でＳＷ２がオンする。マイクロコンピュータＰＲＳはＳＷ１オンで測光、自動焦点調節を行い、ＳＷ２オンをトリガとして露出制御とその後のフィルムの巻き上げを行う。
【００５０】
なお、ＳＷ２はマイクロコンピュータであるＰＲＳの「割り込み入力端子」に接続され、ＳＷ１オン時のプログラム実行中でもＳＷ２オンによって割り込みがかかり、直ちに所定の割り込みプログラムへ制御を移すことができる。
【００５１】
ＭＴＲ１はフィルム給送用、ＭＴＲ２はミラーアップ・ダウンおよびシャッタばねチャージ用のモータであり、各々の駆動回路ＭＤＲ１、ＭＤＲ２により正転、逆転の制御が行われる。マイクロコンピュータＰＲＳから駆動回路ＭＤＲ１、ＭＤＲ２に入力されている信号Ｍ１Ｆ、Ｍ１Ｒ、Ｍ２Ｆ、Ｍ２Ｒはモータ制御用の正転及び反転制御信号である。
【００５２】
ＭＧ１、ＭＧ２は各々シャッタ先幕・後幕走行開始用マグネットで、制御信号ＳＭＧ１、ＳＭＧ２、増幅トランジスタＴＲ１、ＴＲ２により通電され、マイクロコンピュータＰＲＳによりシャッタ制御が行われる。
【００５３】
なお、モーター駆動回路ＭＤＲ１、ＭＤＲ２、シャッタ制御は、本発明と直接関わりがないので、詳しい説明は省略する。
【００５４】
レンズＬＮＳ内制御回路ＬＰＲＳにバッファ信号ＬＣＫと同期して入力されるバッファ信号ＤＣＬは、カメラからレンズＬＮＳに対する命令のデータであり、命令に対するレンズＬＮＳの動作は予め決められている。レンズＬＮＳ内制御回路ＬＰＲＳは、所定の手続きに従ってその命令を解析し、焦点調節や絞り制御の動作や、出力ＤＬＣからレンズＬＮＳの各部動作状況（焦点調節光学系の駆動状況や、絞りの駆動状態等）や、各種パラメータ（開放Ｆナンバ、焦点距離、デフォーカス量対焦点調節光学系の移動量の係数、各種ピント補正量等）の出力を行う。
【００５５】
本実施形態では、ズームレンズの例を示しており、カメラから焦点調節の命令が送られた場合には、同時に送られてくる駆動量・方向に従って焦点調節用モータＬＭＴＲを信号ＬＭＦ、ＬＭＲによって駆動して、光学系を光軸方向に正逆移動させて焦点調節を行う。光学系の移動量は光学系に連動して回動するパルス板のパターンをフォトカプラーにて検出し、移動量に応じた数のパルスを出力するエンコーダ回路ＥＮＣＦのパルス信号ＳＥＮＣＦでモニタし、レンズＬＮＳ内制御回路ＬＰＲＳ内のカウンタで計数しており、焦点調節用の所定の移動が完了した時点でレンズＬＮＳ内制御回路ＬＰＲＳ自身が信号ＬＭＦ、ＬＭＲを‘Ｌ’にしてモータＬＭＴＲを制動する。
【００５６】
このため、一旦カメラから焦点調節の命令が送られた後は、カメラの制御装置であるマイクロコンピュータＰＲＳはレンズの駆動が終了するまで、レンズ駆動に関して全く関与する必要がない。また、カメラから要求があった場合には、上記カウンタの内容をカメラに送出することも可能な構成になっている。
【００５７】
カメラから絞り制御の命令が送られた場合には、同時に送られてくる絞り段数に従って、絞り駆動用としては公知のステッピング・モータＤＭＴＲを駆動する。なお、ステッピング・モータＤＭＴＲはオープン制御が可能なため、動作をモニタするためのエンコーダを必要としない。
【００５８】
ＥＮＣＺはズーム光学系に付随したエンコーダ回路であり、レンズＬＮＳ内制御回路ＬＰＲＳはエンコーダ回路ＥＮＣＺからの信号ＳＥＮＣＺを入力してズーム位置を検出する。レンズＬＮＳ内制御回路ＬＰＲＳ内には各ズーム位置におけるレンズ・パラメータが格納されており、カメラ側のマイクロコンピュータＰＲＳから要求があった場合には、現在のズーム位置に対応したパラメータをカメラ側に送出する。
【００５９】
ＩＣＣは、光電変換素子であるＣＣＤ等から構成される焦点検出用エリアセンサ及びその駆動制御回路である焦点検出回路であり、選択信号ＣＩＣＣが‘Ｈ’のとき選択されて、データ信号ＳＯ、ＳＩ、同期信号ＳＣＬＫを用いてマイクロコンピュータＰＲＳから制御される。
【００６０】
制御信号ΦＶ、ΦＨ、ΦＲはエリアセンサ出力の読み出し、リセット信号であり、マイクロコンピュータＰＲＳから信号に基づいて焦点検出回路ＩＣＣ内の駆動回路によりセンサ制御信号が生成される。センサ出力はセンサ部からの読み出し後増幅され、出力信号ＩＭＡＧＥとしてマイクロコンピュータＰＲＳのアナログ入力端子に入力され、マイクロコンピュータＰＲＳは出力信号ＩＭＡＧＥをＡ／Ｄ変換後、そのデジタル値をＲＡＭ上の所定のアドレスへ順次格納してゆく。これらデジタル変換された信号を用いて焦点検出を行っていく。
【００６１】
ＶＲは前述した各差動アンプに共通の蓄積終了判定レベルであり、ＩＮＴＥは蓄積終了出力信号、ＩＣＬＫは焦点検出回路ＩＣＣ内の制御回路部の基準クロック信号である。
【００６２】
上述のカメラの全システム中、特に焦点検出回路ＩＣＣの動作は第１の実施形態で説明したようにエリアセンサによる焦点検出の動作を行ない、その結果はマイクロコンピュータＰＲＳを介してレンズＬＮＳ内制御回路ＬＰＲＳにより適切な焦点ポイントにレンズ系を移動・保持し、その後シャッターが動作することで、焦点のあった画像を取得することができる。
【００６３】
尚、上記図８ではカメラとレンズＬＮＳが別体（レンズ交換が可能）となるもので表現されているが、本発明はカメラ・レンズ一体なるものでも何等問題なく、これ等に限定されるものではない。
【００６４】
［第３の実施形態］
以上の実施形態においては、蓄積時間用のクロック信号をセンサの駆動用発振部の出力パルスを内部で分周し、センサ自身で得ていた。これに対し、図８のマイクロコンピュータＰＲＳの出力パルス信号を直接入力し、この信号をカウントする方法も有効である。
【００６５】
この場合、図９に示すように、マイクロコンピュータＰＲＳから焦点検出用エリアセンサＩＣＣに計時用タイミング信号ＴＣＬＫとして出力する。ＰＲＳ側で蓄積時間の計時に必要十分な周波数の設定が可能となるので、図７におけるカウンタ５８の前後での分周回路５７は省略可能となる。この実施形態での図７と同様な説明図が図１０であり、マイクロコンピュータＰＲＳからの計時用タイミング信号ＴＣＬＫを直接バッファ７１に入力して、クロックカウンタ７２に伝達するだけとなる。但し、図９に示したように、ＰＲＳに新たな出力ポート（ＴＣＬＫ）を用意しなくてはならない。
【００６６】
【発明の効果】
本発明によれば、記録部から光電変換素子外部に出力された蓄積時間の情報を、複数の光電変換画素の信号の補正に用いるようにしたので、精度の良い補正が可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態の焦点検出装置の概略構成図である。
【図２】本発明の第１の実施形態の絞りおよび２次結像系を示す図である。
【図３】本発明の第１の実施形態の光電変換素子を示す図である。
【図４】本発明の第１の実施形態のセンサのブロック構成を示す図である。
【図５】本発明の第１の実施形態のセンサの動作を説明する回路図である。
【図６】本発明の第１の実施形態のセンサの動作説明のタイミングチャートである。
【図７】本発明の第１の実施形態のタイミング信号発生の回路図である。
【図８】本発明の第２の実施形態のカメラおよびレンズの回路図である。
【図９】本発明の第３の実施形態のカメラおよびレンズの回路図である。
【図１０】本発明の第３の実施形態のタイミング信号発生の回路図である。
【図１１】従来の焦点検出領域の分布を示す図である。
【図１２】従来の光電変換素子及びその蓄積制御を説明する図である。
【図１３】従来の光電変換素子及びその蓄積制御を説明する図である。
【図１４】従来の光電変換素子及びその蓄積制御を処理する回路図である。
【図１５】従来の撮影領域内の焦点検出領域の分布を示す図である。
【図１６】従来の焦点検出領域の分布を示す図である。
【図１７】従来の光電変換素子及びその蓄積制御を説明するブロック図である。
【図１８】焦点検出領域を二次元に拡大した場合の説明図である。
【図１９】焦点検出領域を二次元に拡大した場合のセンサ領域の説明図である。
【図２０】焦点検出領域を二次元に拡大した場合の蓄積制御の説明図である。
【図２１】焦点検出領域を二次元に拡大した場合のセンサ列の説明図である。
【図２２】焦点検出領域を二次元に拡大した場合の撮影領域とセンサ列との説明図である。
【符号の説明】
１ 対物レンズの光軸
２ フィルム
３ 主ミラー
４ 第１の反射鏡
５ 結像面
６ 第２の反射鏡
７ 赤外カットフィルタ
８ 絞り
９ ２次結像系
１０ 第３の反射鏡
１１ 光電変換素子
１２ 光束
２４ 対物レンズの光軸
１１２ 光電変換素子
Ａ 撮影画面領域
Ｂ 焦点検出領域
ＰＲＳ カメラ内制御装置
ＬＣＭ レンズ通信バッファ回路
ＳＤＲ センサ駆動回路
ＬＮＳ レンズ
ＬＰＲＳ レンズ内制御回路
ＥＮＣＦ 焦点調節用レンズの移動量検出エンコーダ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a storage type photoelectric conversion element used in a photoelectric conversion device such as a camera, a video, an imaging device, and a focus detection device of various observation devices. More specifically, the present invention relates to an area sensor for focus detection. The present invention relates to a storage type photoelectric conversion element that measures and stores the storage time of each element by the element itself, and an automatic focusing apparatus using the element.
[0002]
[Prior art]
The focus detection function represented by a camera or the like has progressed from a detection area at one central point to a three-point detection area and a five-point detection area, and the detection range is reliably expanded with respect to the imaging area. For this purpose, not only the progress of the detection optical system but also the progress of the sensor corresponding to it is indispensable.
[0003]
Even if the number of sensor pairs that are photoelectric conversion elements is increased due to an increase in the focus detection area, each sensor pair needs to be subjected to accumulation control independently. For example, even when the detection areas are 3 points and 5 points, It is desirable that each has a dedicated accumulation control circuit.
[0004]
In a camera incorporating a focus detection device, the focus detection area is a narrow and one-dimensional range as shown in B with respect to the shooting screen A as shown in FIG. This is a detection device using a set of line sensor arrays 112-1 and 112-2 shown in FIG.
[0005]
FIG. 12 is an explanatory diagram regarding the accumulation control of the sensor array 112. This is because the output (VD) of the light-shielded dark pixel 120 common to the two sensor rows 112-1 and 112-2 and the maximum value detection circuit 121 common to the two sensor rows 112-1 and 112-2. The difference between the output, that is, the output (VP) of the pixel indicating the maximum value is detected and output by the differential amplifier 122, and accumulation is performed until the predetermined level (VR) is reached. ΦR serving as a readout signal to the storage capacity is sent from the storage control unit 123 to the sensor arrays 112-1 and 112-2. Here, the difference between the maximum value VP and the dark output VD is determined based on the dark output VD, and the focus detection is performed by accumulating until a difference between the maximum value VP and the dark output VD reaches a predetermined level VR. This is because it can be determined that the level is sufficiently accurate in the phase difference detection process. On the other hand, if the accumulation time is further increased, there is a problem such that the output signal is saturated and proper detection cannot be performed. Therefore, when the read signal ΦR becomes [VP−VD = VR]. Return to the sensor arrays 112-1 and 112-2.
[0006]
FIG. 13 shows the state of the image signals of the two sensor rows 112-1 and 112-2 on the basis of the output VD of the dark pixel 120, which is the image signal of each of the sensor rows 112-1 and 112-2. For one image and two images, a common maximum output value (VP, one image side in the figure) is a set level (VR). When used as a focus detection device, when any of the sensor pixels in each of the sensor rows 112-1 and 112-2 reaches the set level VR, the accumulation is finished and the images of the sensors are compared. , Detect whether it is in focus.
[0007]
FIG. 14 shows an outline of the circuit configuration after the maximum value detection circuit 121. Each pixel output (nth pixel output Vn) is compared with the current maximum value VP, and if the nth pixel output Vn exceeds the maximum value VP, the differential amplifier 130 is inverted and the MOS switch 132 is turned on. Thus, the pixel output Vn is output via the voltage follower 131, and the pixel output Vn becomes a new maximum value VP. The maximum value VP output of the maximum value detection circuit 121 of the sensor arrays 112-1 and 112-2 is differentially amplified by the dark pixel output VD and the differential amplifier 133, and further compared with the set level VR by the comparator 134. When the dynamic output exceeds the set level VR, the accumulation is completed and the reading signal ΦR is output. This readout signal ΦR is a signal for reading out the electric charges accumulated in the pixels of the sensor arrays 112-1 and 112-2.
[0008]
On the other hand, FIG. 15 shows an example in which the focus detection area is enlarged, and the detection area B is three areas with respect to the shooting screen A. This is obtained by adding three detection areas in a direction orthogonal to the detection areas in FIG.
[0009]
An example in which the focus detection area shown in FIG. 15 is embodied is shown in FIG. In the figure, this is realized by using a photoelectric conversion element having a plurality of sensor array pairs C to F and a focus detection optical system (not shown) corresponding to the photoelectric conversion element. FIG. 17 shows a specific circuit example of accumulation detection using the focus detection areas C to F shown in FIG. 16 as sensor arrays. As shown in FIG. 17, in the accumulation control for the plurality of sensor arrays C to F, a dedicated accumulation control unit is provided for each sensor array, and the combination of the sensor array and the peripheral circuit as shown in FIG. The arrangement is equal to the number of column pairs. In FIG. 17, the dark pixel outputs VD1 to VD4 of each sensor column pair C to F and the maximum value outputs VP1 to VP4 of the maximum value detection circuits 141 to 144 of each sensor column pair C to F are respectively differential amplifiers 145 to 145. The difference is determined at 148, compared with a predetermined level VR by the storage control units 149 to 152, and when the predetermined voltage is reached, read signals ΦR1 to ΦR4 are output, and storage of each pixel of each sensor column pair C to F is performed. Read the charge. Further, the common output of the accumulation control units 149 to 152 outputs a signal indicating the completion of accumulation of the sensor arrays C to F, for example, to a control system including a CPU. Thereafter, the output of each pixel in each sensor array is read as an image output, and the amount of defocus (defocus amount) is detected from this image output.
[0010]
[Problems to be solved by the invention]
The above is a focus detection device using a one-dimensional sensor array, that is, a line sensor. The detection area is a field of view corresponding to the light receiving portion of each sensor array, and is not more than a combination of “lines”.
[0011]
Therefore, when aiming at further expansion of the detection region, a focus detection apparatus using a photoelectric conversion element having a light receiving portion that is two-dimensionally expanded, that is, an area sensor, is necessary.
[0012]
FIG. 18 shows the detection area (B) in the imaging area (A) in the focus detection apparatus using the area sensor, and the detection area is greatly enlarged as compared with FIGS. If the phase difference detection method is used, the photoelectric conversion element used for this is an area sensor pair G in which two area regions are arranged as shown in FIG. 19, and an example of accumulation control of the area sensor pair G in this case is shown in FIG. Shown in In FIG. 20, a difference between the output VD of the dark pixel of the area sensor pair G and the maximum value output VP of the maximum value detection circuit 161 in each area of the area sensor pair G is obtained by the differential amplifier 162, and the accumulation control unit At 163, the output of the differential amplifier 162 is compared with a predetermined reference voltage VR, and when the output of the differential amplifier 162 increases, a stop signal φR for stopping the accumulation is output to the area sensor pair G. Here, if the light receiving area of one area sensor is divided and used as shown in FIG. 21, it is shown in an area area indicated by a plurality of small squares corresponding to FIG. 21 in the imaging area (A) as shown in FIG. In this way, a much larger number of distance measurement areas can be set as compared with FIG. 11 and FIG.
[0013]
However, the handling of the accumulation time for each region is a problem here. That is, if the timer function and interrupt function of the microcomputer are used as in the prior art, the number of areas of the area sensor pair is too large to obtain each information sufficiently accurately. In other words, the frequency of interrupts for focus detection becomes too high while the microcomputer program continues, and the probability that multiple areas of a divided area sensor pair will finish accumulating at the same time becomes high. There is a problem in that the accumulation time cannot be obtained correctly and an accurate focus detection function cannot be performed.
[0014]
[Means for Solving the Problems]
The present invention aims to solve the above-mentioned problems, and the gist thereof is as follows. That is, the photoelectric conversion element itself measures and stores the accumulation times of a large number of areas, thereby reducing the burden on the microcomputer, obtaining accurate information on each area, and enabling an accurate focus detection operation.
[0015]
The present invention is characterized in that, in the storage type photoelectric conversion element, the photoelectric conversion element itself has a clock signal generating means serving as a reference for time measurement, or performs time measurement based on a clock signal input to the photoelectric conversion element, The storage time is also measured, stored and output as digital information from a reference signal.
[0016]
Further, in the focus detection apparatus, the storage type photoelectric conversion element is used.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the present invention will be described in detail with reference to the drawings.
[0018]
[First Embodiment]
FIG. 1 is an optical layout diagram of each component for performing focus detection in each region in the photographing screen. In the figure, 1 is the optical axis of an objective lens (not shown) arranged on the left side of the figure, 2 is a silver salt film arranged at the focal position of the objective lens, and 3 is arranged on the optical axis 1 of the objective lens. The semi-transparent main mirror 4 is similarly a first reflecting mirror disposed obliquely on the optical axis 1 of the objective lens, and 5 is a paraxial image conjugate to the film 2 by the first reflecting mirror 4. Surface 6 is a second reflecting mirror for focus detection, 7 is an infrared cut filter for blocking infrared rays, 8 is a diaphragm having two openings 8-1 and 8-2, and 9 is two openings 8 of the diaphragm 8. -1 and 8-2, a secondary imaging system having two lenses 9-1 and 9-2, 10 is a third reflecting mirror for focus detection, and 11 is two area sensors 11 -1 and 11-2 are respectively shown.
[0019]
Here, the first reflecting mirror 4 has a curvature, and has a convergent power for projecting the two openings 8-1 and 8-2 of the diaphragm 8 in the vicinity of the exit pupil of an objective lens (not shown). Further, the first reflecting mirror 4 is deposited with a metal film such as aluminum or silver so that only a necessary region reflects light, and also serves as a field mask for limiting the range in which focus detection is performed. In the other reflecting mirrors 6 and 10 as well, only the minimum necessary area is deposited in order to reduce the stray light incident on the photoelectric conversion element 11. It is also effective to apply a light-absorbing paint or the like to a region that does not function as a reflecting surface of each of the reflecting mirrors 4, 6, 10 or to provide a light shielding member in the vicinity.
[0020]
FIG. 2 is a plan view of the diaphragm 8 in which two horizontally long openings 8-1 and 8-2 are arranged in a direction in which the opening width is narrow. The dotted lines in the figure indicate the lenses 9-1 and 9-2 of the secondary imaging system 9 disposed behind the apertures 8-1 and 8-2 corresponding to the apertures 8-1 and 8-2. It is.
[0021]
FIG. 3 is a schematic plan view of the photoelectric conversion element 11. The two area sensors 11-1 and 11-2 shown in FIG. 1 are two-dimensionally arranged area sensors as shown in FIG. Two are arranged side by side.
[0022]
In the above configuration, the light beams 12-1 and 12-2 from the objective lens which is one of the photographic lenses (not shown) in FIG. 1 pass through the main mirror 3, and are then substantially reflected by the first reflecting mirror 4. Is reflected in the direction along the inclination of the second reflection mirror 6, and the direction is changed again by the second reflecting mirror 6, and then passes through the two apertures 8-1 and 8-2 of the infrared cut filter 7 and the diaphragm 8, and the secondary image is formed. The light is condensed by the lenses 9-1 and 9-2 of the system 9 and reaches the area sensors 11-1 and 11-2 of the photoelectric conversion element 11 through the third reflecting mirror 10, respectively. The light beams 12-1 and 12-2 in the figure indicate the light beam that forms an image at the center of the film 2, but the light beam that forms an image at other positions also passes through the same path to the photoelectric conversion element 11. As a whole, two light quantity distributions corresponding to a predetermined two-dimensional area on the film 2 are formed on the area sensors 11-1 and 11-2 of the photoelectric conversion element 11.
[0023]
In this embodiment, the 1st reflective mirror 4 is comprised by a part of curved surface formed by rotating a quadratic curve around an axis | shaft, and a spheroidal surface is used especially suitably. In FIG. 1, the surface shape of the first reflecting mirror 4 is composed of a part of a spheroid formed by rotating an ellipse 21 having a point 20 as an apex around the axis 22 of the ellipse 21, and the focal point thereof is the second. Are set in the vicinity of the image position 23 at the center of the diaphragm 8 by the reflecting mirror 6 and a point (not shown) on the extension of the optical axis 24 after passing through the main mirror 3. If the point on the extension of the optical axis 24 of the objective lens is near the exit pupil position of the objective lens (or the average exit pupil position when various objective lenses are used interchangeably), the objective lens Thus, the first reflecting mirror 4 functions as an ideal field lens. As is apparent from FIG. 1, the first reflector 4 is optically used in a region that does not include the rotation axis and vertex of the spheroid. The specific shape of the spheroid of this embodiment is relative to the coordinate axis of FIG.
[0024]
[Expression 1]

However, x, y, and z are triaxial coordinates, and Formula 1 is a formula that represents a quadratic curve. When k = 0, the spherical surface is rotated, k = −1, the paraboloid is rotated, and k> −1. It becomes an ellipsoid. H²= Y²+ Z²Where r represents the on-axis curvature. Assuming a normal camera and objective lens (photographing lens), the range of r and k is
−20 ≦ r ≦ 20−1 <k ≦ −0.2
The degree is preferred.
[0025]
In the present embodiment, the first surface of the secondary imaging system 9 is formed in a concave shape so that light incident on the secondary imaging system 9 is not refracted by force. Good and uniform imaging performance is ensured over a wide range of the two-dimensional region of the conversion element 11.
[0026]
With respect to the two light quantity distributions thus obtained, the relative positional relationship in the vertical direction in the separation direction, that is, in the drawing of the two area sensors 11-1 and 11-2 shown in FIG. By calculating at each of the positions 1, 11-2, the focus state of the objective lens can be detected two-dimensionally. The first reflecting mirror 4 is retracted out of the photographing optical path in the same manner as the main mirror 3 when photographing.
[0027]
Next, the photoelectric conversion element 11 and its drive control circuit will be described. FIG. 4 is a block diagram of an integrated circuit (ICC) 40 in which the photoelectric conversion element 11 and its drive control circuit are integrated into one chip.
[0028]
In the figure, reference numeral 41 denotes a photoelectric conversion element unit, which is a pair of area sensor units 11-1 and 11-2 as shown in the photoelectric conversion element 11 of FIG. As shown in FIG. 21, the area sensor units 11-1 and 11-2 are controlled such that, for example, each region divided in a zigzag form an optimum accumulation end level independently.
[0029]
Reference numeral 42 denotes an analog circuit unit that performs accumulation and output control of the area sensor unit of the photoelectric conversion element unit 41. The level setting is mainly used for determining the end of accumulation, noise cancellation for comparison operation and accumulated charge, and an appropriate gain for analog output. Is detected, controlled, and transmitted.
[0030]
Further, 43 is a logic control unit for the accumulation and output control of the area sensor unit with respect to the analog circuit unit 42, and as described above, accumulation control in sequential scanning such that each divided region ends accumulation at an optimum level, The stored time information is stored. That is, as shown in FIG. 12, FIG. 13 and FIG.
V_R= V_P-V_D
Judgment by the accumulation control unit is sequentially performed in a short time, and the accumulation time measured at the end of accumulation is stored.
[0031]
FIG. 5 is a schematic diagram for explaining the accumulation control operation by the analog circuit unit 42 and the logic control unit 43 shown in FIG. Unlike FIG. 20, each divided region (pair) has maximum value detection circuit units 1 to n and differential amplifiers AP1 to APn, and the outputs of the differential amplifiers AP1 to APn reach a common predetermined level VR. When the arrival is determined, the accumulation operation is terminated, and the read signal ΦR is sent for each divided region to become read signals ΦR1 to n. n is the number of area divisions, and if the division form shown in FIG.
[0032]
Here, in order to reduce the circuit scale while enabling independent accumulation control for each divided area, the control circuit A1 in FIG. 5 is provided with analog switch pairs AS1a, AS1b to ASna, ASnb provided for each divided area. Are sequentially scanned by the area selection timing signals s1 to sn based on the reference clock signal ICLK, and the common comparator COM determines whether or not all areas have been accumulated. Further, the output of the comparator COM is masked by a common mask signal COMK and an AND gate so that the determination for each region is performed correctly. Note that the two area sensor units 11-1 and 11-2 in FIGS. 3 and 4 are controlled simultaneously and in each divided region pair based on a common signal (maximum output value for each divided region pair). .
[0033]
FIG. 6 is a timing chart of each signal in FIG. In the figure, ICLK is obtained by using an oscillation clock of an accumulation time control section described later as an accumulation control reference clock. COMK is a mask signal for masking the output of the common comparator COM as described above, and is generated by dividing ICLK by 4 in FIG. When this COMK signal is High (high level), the output of the comparator COM in FIG. 6 is valid.
[0034]
Next, the region selection timing signals s1 to sn are region selection signals further divided by n with respect to the mask signal COMK and serve as timing signals for the accumulation end determination operation of each region (1 to n). When this signal is High, the maximum value detection circuit unit corresponding to each selected region, the differential amplifiers (AP1 to n), and the analog switch pairs (AS1a, AS1b to ASna, ASnb) are enabled, and only the selected region is selected. When the accumulation is completed, a read signal ΦR is sent for each divided region to become read signals ΦR1 to n.
[0035]
This accumulation end / read signal .PHI.R is also sent to the SRAM 44 of FIG. 4, and is held as the accumulation end signals tr1 to trn of each divided area together with the area selection timing signals s1 to sn. This is to prevent the divided area selection timing signals s1 to sn from being output to the area once accumulated. In FIG. 6, the accumulation of region 1 is completed for the second scan and region 2 is completed for the first scan, but the accumulation of region 3 is not completed for the second scan.
[0036]
On the other hand, reference numeral 44 denotes an SRAM (Static Randum Access Memory) section that stores accumulation time information for each of the divided areas.
[0037]
A communication control unit 45 transmits various information such as the accumulation time for each divided area to the microcomputer that controls the ICC 40 and the entire camera, and receives control communication such as a focus detection instruction. .
[0038]
An accumulation time control unit 46 measures the accumulation time for each of the divided areas, and the result is stored in the SRAM 44.
[0039]
Reference numeral 47 denotes a power supply circuit unit of the ICC 40, which supplies operation power to each unit by appropriate voltage and current, and sets and outputs an accumulation end level.
[0040]
Next, FIG. 7 is a simple configuration explanatory view in the vicinity of the oscillation circuit unit of the storage time control unit 46 in FIG. 4. The crystal 51 and the piezoelectric element vibrator 51, the load capacitors 52 and 53, and the oscillation resistor 54 are not normally used. The attached part constitutes an oscillation circuit together with the oscillation inverter 55. The elapsed time from the start of accumulation is measured by the clock counter 58 through the buffer 56 and through the frequency divider 57 as necessary. As described above, the oscillation clock is also used as it is as a storage control reference clock or a drive clock.
[0041]
The output of the counter 58 is written in the corresponding area of each divided area set in the SRAM 44 of FIG. As a result, the accumulated times of all the divided areas are stored in the element as digital information. If necessary, the information is communicated to a microcomputer (not shown) in the camera in the form of digital information via the communication control unit 45 in FIG. Then, when the correction of various image signals, for example, when the dark current of the sensor changes with the accumulation time, the output of the counter 58 is used to obtain a correction value according to the accumulation time.
[0042]
7 is optimally set together with the oscillation frequency of the oscillator 51 according to the storage capacity of the SRAM 44 and the necessary resolution as the accumulation time information.
[0043]
[Second Embodiment]
FIG. 8 is a circuit diagram showing an example of a specific configuration of a camera provided with each focus detection device shown in each embodiment as described above. First, the configuration of each section will be described.
[0044]
In FIG. 8, PRS is a camera control device, for example, a one-chip microcomputer having a CPU (Central Processing Unit), ROM, RAM, A / D, and D / A conversion function therein. The microcomputer PRS performs a series of camera operations such as an automatic exposure control function, an automatic focus adjustment function, and film winding / rewinding according to the camera sequence program stored in the ROM. For this purpose, the microcomputer PRS uses the communication signals SO, SI, SCLK, the communication selection signals CLCM, CDDR, and CICC to communicate with the peripheral circuit in the camera body and the in-lens control device, and each circuit and lens. To control the operation.
[0045]
SO is a data signal output from the microcomputer PRS, SI is a data signal input to the microcomputer PRS, and SCLK is a synchronous clock of the signals SO and SI.
[0046]
The LCM is a lens communication buffer circuit that supplies power to the lens power supply terminal VL when the camera is in operation, and a selection signal CLCM from the microcomputer PRS is a high potential level (hereinafter abbreviated as 'H', low When the potential level is abbreviated as “L”), it becomes a communication buffer between the camera and the lens.
[0047]
When the microcomputer PRS sets the selection signal CLCM to “H” and sends predetermined data from the data signal SO in synchronization with the synchronization clock SCLK, the lens communication buffer circuit LCM receives the synchronization clock via the camera-lens communication contact. Buffer signals LCK and DCL of SCLK and data signal SO are output to the lens. At the same time, the buffer signal of the signal DLC from the lens LNS is output to the data signal SI, and the microcomputer PRS inputs lens data from the data signal SI in synchronization with the synchronization clock SCLK.
[0048]
DDR is a circuit for detecting and displaying various switches SWS, and is selected when the signal CDDDR is ‘H’, and is controlled by the microcomputer PRS using the data signals SO and SI and the synchronous clock SCLK. That is, the display of the display member DSP of the camera is switched based on the data sent from the microcomputer PRS, and the on / off state of various operation members of the camera is notified to the microcomputer PRS by communication. OLC is an external liquid crystal display device located above the camera, and ILC is a finder internal liquid crystal display device. In the present embodiment, setting of an operation region for focus detection and the like is performed by the switch SWS belonging to the detection and display circuit DDR.
[0049]
SW1 and SW2 are interlocked with a release button (not shown), and SW1 is turned on when the release button is pressed at the first stage, and SW2 is turned on when the release button is pressed at the second stage. The microcomputer PRS performs photometry and automatic focus adjustment when SW1 is ON, and performs exposure control and subsequent film winding with SW2 ON as a trigger.
[0050]
Note that SW2 is connected to the “interrupt input terminal” of the PRS which is a microcomputer, and even when the program is executed when SW1 is turned on, an interrupt is generated when SW2 is turned on, and control can be immediately transferred to a predetermined interrupt program.
[0051]
MTR1 is a film feeding motor, MTR2 is a mirror up / down motor and a shutter spring charging motor, and forward drive and reverse drive are controlled by respective drive circuits MDR1 and MDR2. Signals M1F, M1R, M2F, and M2R input from the microcomputer PRS to the drive circuits MDR1 and MDR2 are forward and reverse control signals for motor control.
[0052]
MG1 and MG2 are shutter front curtain and rear curtain travel start magnets, respectively, which are energized by control signals SMG1 and SMG2 and amplification transistors TR1 and TR2, and shutter control is performed by the microcomputer PRS.
[0053]
The motor drive circuits MDR1 and MDR2 and the shutter control are not directly related to the present invention, and detailed description thereof is omitted.
[0054]
The buffer signal DCL input to the intra-lens LNS control circuit LPRS in synchronization with the buffer signal LCK is command data for the lens LNS from the camera, and the operation of the lens LNS for the command is determined in advance. The control circuit LPRS in the lens LNS analyzes the command according to a predetermined procedure, and operates the focus adjustment and the aperture control, the operation status of each part of the lens LNS from the output DLC (the drive status of the focus adjustment optical system, the drive status of the aperture) Etc.) and various parameters (open F number, focal length, defocus amount vs. moving amount coefficient of the focus adjusting optical system, various focus correction amounts, etc.).
[0055]
This embodiment shows an example of a zoom lens. When a focus adjustment command is sent from the camera, the focus adjustment motor LMTR is driven by signals LMF and LMR in accordance with the drive amount and direction sent simultaneously. Then, the focal point is adjusted by moving the optical system forward and backward in the optical axis direction. The amount of movement of the optical system is monitored by a pulse signal SENCF of an encoder circuit ENCF that outputs a number of pulses corresponding to the amount of movement by detecting the pattern of a pulse plate that rotates in conjunction with the optical system with a photocoupler. It is counted by a counter in the LNS control circuit LPRS, and when the predetermined movement for focus adjustment is completed, the lens LNS control circuit LPRS itself sets the signals LMF and LMR to 'L' to brake the motor LMTR.
[0056]
For this reason, once the focus adjustment command is sent from the camera, the microcomputer PRS, which is the camera control device, does not need to be involved in lens driving at all until the lens driving is completed. Further, when requested by the camera, the contents of the counter can be sent to the camera.
[0057]
When an aperture control command is sent from the camera, a known stepping motor DMTR for driving the aperture is driven according to the number of aperture stages sent simultaneously. Since the stepping motor DMTR can be controlled open, an encoder for monitoring the operation is not required.
[0058]
ENCZ is an encoder circuit associated with the zoom optical system, and the lens LNS control circuit LPRS receives the signal SENCZ from the encoder circuit ENCZ and detects the zoom position. The lens parameter at each zoom position is stored in the lens LNS control circuit LPRS, and when there is a request from the microcomputer PRS on the camera side, a parameter corresponding to the current zoom position is sent to the camera side. To do.
[0059]
ICC is a focus detection area sensor composed of a CCD or the like which is a photoelectric conversion element and a focus detection circuit which is a drive control circuit thereof, and is selected when the selection signal CICC is 'H' and the data signals SO and SI Control is performed from the microcomputer PRS using the synchronization signal SCLK.
[0060]
The control signals ΦV, ΦH, and ΦR are area sensor output readout and reset signals, and a sensor control signal is generated by a drive circuit in the focus detection circuit ICC based on the signal from the microcomputer PRS. The sensor output is amplified after being read out from the sensor unit, and input to the analog input terminal of the microcomputer PRS as the output signal IMAGE. Store sequentially to the address. Focus detection is performed using these digitally converted signals.
[0061]
VR is an accumulation end determination level common to the above-described differential amplifiers, INTE is an accumulation end output signal, and ICLK is a reference clock signal of a control circuit unit in the focus detection circuit ICC.
[0062]
In the entire system of the camera described above, the focus detection circuit ICC operates in the focus detection by the area sensor as described in the first embodiment, and the result is the control circuit in the lens LNS via the microcomputer PRS. By moving and holding the lens system to an appropriate focal point by LPRS and then operating the shutter, a focused image can be acquired.
[0063]
In FIG. 8, the camera and the lens LNS are expressed as separate bodies (lens exchange is possible), but the present invention is not limited to this, even if the camera and the lens are integrated. is not.
[0064]
[Third Embodiment]
In the above embodiment, the clock signal for the accumulation time is obtained by the sensor itself by internally dividing the output pulse of the driving oscillation unit of the sensor. On the other hand, a method of directly inputting the output pulse signal of the microcomputer PRS in FIG. 8 and counting this signal is also effective.
[0065]
In this case, as shown in FIG. 9, the microcomputer PRS outputs a timing signal TCLK to the focus detection area sensor ICC. Since it is possible to set a necessary and sufficient frequency at the time of accumulation time on the PRS side, the frequency divider 57 before and after the counter 58 in FIG. 7 can be omitted. FIG. 10 is an explanatory diagram similar to FIG. 7 in this embodiment, and the timing signal TCLK from the microcomputer PRS is directly input to the buffer 71 and transmitted only to the clock counter 72. However, as shown in FIG. 9, a new output port (TCLK) must be prepared for the PRS.
[0066]
【The invention's effect】
  According to the present invention, since the storage time information output from the recording unit to the outside of the photoelectric conversion element is used for correcting the signals of the plurality of photoelectric conversion pixels, accurate correction can be performed.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a focus detection apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a stop and a secondary imaging system according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a photoelectric conversion element according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a block configuration of a sensor according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating the operation of the sensor according to the first embodiment of the present invention.
FIG. 6 is a timing chart for explaining the operation of the sensor according to the first embodiment of the present invention.
FIG. 7 is a circuit diagram of timing signal generation according to the first embodiment of the present invention.
FIG. 8 is a circuit diagram of a camera and a lens according to a second embodiment of the present invention.
FIG. 9 is a circuit diagram of a camera and a lens according to a third embodiment of the present invention.
FIG. 10 is a circuit diagram of timing signal generation according to the third embodiment of the present invention.
FIG. 11 is a diagram showing a distribution of a conventional focus detection region.
FIG. 12 is a diagram illustrating a conventional photoelectric conversion element and its accumulation control.
FIG. 13 is a diagram for explaining a conventional photoelectric conversion element and its accumulation control.
FIG. 14 is a circuit diagram for processing a conventional photoelectric conversion element and its accumulation control.
FIG. 15 is a diagram illustrating a distribution of focus detection areas in a conventional imaging area.
FIG. 16 is a diagram showing a distribution of a conventional focus detection region.
FIG. 17 is a block diagram for explaining a conventional photoelectric conversion element and its accumulation control.
FIG. 18 is an explanatory diagram when the focus detection area is enlarged two-dimensionally.
FIG. 19 is an explanatory diagram of a sensor region when a focus detection region is enlarged two-dimensionally.
FIG. 20 is an explanatory diagram of accumulation control when a focus detection region is enlarged two-dimensionally.
FIG. 21 is an explanatory diagram of a sensor array when a focus detection area is enlarged two-dimensionally.
FIG. 22 is an explanatory diagram of an imaging region and a sensor array when a focus detection region is enlarged two-dimensionally.
[Explanation of symbols]
1 Optical axis of the objective lens
2 film
3 Main mirror
4 First reflector
5 Imaging surface
6 Second reflector
7 Infrared cut filter
8 Aperture
9 Secondary imaging system
10 Third reflector
11 Photoelectric conversion element
12 luminous flux
24 Optical axis of objective lens
112 photoelectric conversion element
A Shooting screen area
B Focus detection area
PRS In-camera control device
LCM lens communication buffer circuit
SDR sensor drive circuit
LNS lens
LPRS In-lens control circuit
ENCF Encoder for detecting movement of focus adjustment lens

Claims (4)

In a camera having a control unit and a photoelectric conversion element formed on the same semiconductor substrate,
Each of the photoelectric conversion elements has a plurality of divided regions each having a plurality of photoelectric conversion pixels, and a common output unit that outputs signals from the plurality of divided regions arranged in a two-dimensional manner. An area control unit that controls an accumulation time for each of the plurality of divided regions arranged in a two-dimensional manner based on signals sequentially output from the common output unit; and the plurality of divisions arranged in the two-dimensional manner An accumulation time control unit that counts the accumulation time of the region ; a recording unit that records information on the accumulation time counted by the accumulation time control unit; and information on the accumulation time of the recording unit that is external to the photoelectric conversion element. A communication control unit for outputting to
The control unit controls the storage time information output from the recording unit to the outside of the photoelectric conversion element to be used for correcting signals of the plurality of photoelectric conversion pixels.   The camera according to claim 1, wherein the accumulation time control unit includes a clock signal generation unit that serves as a reference for measuring the accumulation time.   The camera according to claim 1, wherein the accumulation time control unit performs the time measurement based on a clock signal input to the photoelectric conversion pixel.   2. The storage time control unit counts the storage time with digital information from a reference signal, the recording unit stores digital information, and the communication control unit outputs digital information. 4. The camera according to any one of items 1 to 3.

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