JPH085457A - Information detecting device - Google Patents

Abstract

PURPOSE:To restrict the chip area at the required minimum without lowering the information detecting function, and to reduce the cost by forming plural circuit parts, which respectively control the storage with a different method, on one chip. CONSTITUTION:A field of view mask MSK has a cross-type opening at a central part and longitudinal openings in the peripheral part of both ends, and a field lens FLDL is formed of three partial FLDL corresponding to the three openings of the field of view mask MSK. A diaphragm DP is provided with four openings at the center and a pair of openings in the peripheral part, and a secondary image forming lens AFL is formed of four lenses. A line sensor SNS is formed of four pairs of sensor lines SNS-1a, SNS-1b SNS-4a, SNS-4b, and receives the image in response to the lens AFL. Since the quantity of displacement of the relative position of an objective image has a special functional relation with the quantity of focus deviation of the photographing lens, quantity of focus deviation of the photographing lens, namely, quantity of de-focus can be detected by respectively performing the appropriate computing to the output of the sensor per each sensor line pair.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an information detecting device which is provided in an optical device such as a camera and is used for focus detection, for example.

[0002]

2. Description of the Related Art In recent years, the number of sensor areas on one chip has increased from one focus detection area to a plurality of focus detection areas, and various storage control methods have been devised to serve as focus detection sensors. Higher performance is being advanced.

The detection area is divided into three areas, from three as disclosed in JP-A-63-11906 to five as disclosed in JP-A-63-47711. There are things such as dots.

On the other hand, the accumulation control method is a method in which the accumulation is controlled by the peak value of the output based on a general dark current level. There is disclosed a method of controlling the accumulation in.

8A, 8B and 9A,
(B) is a diagram for explaining the characteristics of the above-described storage control method.

FIG. 8A is a diagram showing a circuit configuration for realizing a peak value control system based on a dark current. The accumulation control unit 101 has a dark pixel output and a maximum sensor output. When it is detected by the differential amplifier 103 that the output difference of the maximum value detection circuit 102 for detecting the value has reached a certain level, the accumulation is terminated [this method is called Peak-Dark, in the following. Is referred to as P / D].

Therefore, as shown in FIG. 8B, the sensor output has a form in which the dark output of a constant level and the peak output a overlap. In this case, the circuit configuration is the maximum value detection circuit 1
Although only 02 is required, the contrast component, which is important in the focus detection of the phase difference detection method, which is the mainstream today, becomes the level of (ab) in the figure, and a low contrast object is obtained. Will be weak.

On the other hand, FIG. 9 (A) is a diagram showing a circuit configuration for realizing a peak value control system based on a minimum value. The accumulation control unit 201 detects a minimum value in a sensor output. Circuit 202 and maximum value detection circuit 2 for detecting the maximum value
When the difference in the output of 03 is detected by the differential amplifier 204 to reach a certain level, the accumulation is terminated [this method uses a peak-bottom (Peak-Botto) method.
m), hereinafter referred to as P / B].

Therefore, the sensor output is, as shown in FIG. 9B, a constant level offset output (not necessarily).
The output c is the difference between the maximum value and the minimum value.
In this case, the circuit configuration requires not only the maximum detection circuit 203 but also the minimum detection circuit 202, but on the other hand, the contrast component can be taken out in the form of being expanded over the entire output range, so that the focus can be adjusted sufficiently even for a low-contrast subject. Has become the mainstream in today's cameras.

[0010]

It has become possible to improve the performance of the apparatus by adopting the above-mentioned P / B method, that is, by realizing the expansion of the detection area and the complicated accumulation control. The sensor chip area has increased, resulting in an increasingly expensive sensor. When it is used for general consumer use, it is still necessary to make it inexpensive and satisfy its performance.

(Object of the Invention) An object of the present invention is to provide an information detection device which can minimize the chip area and can be made inexpensive without degrading the information detection performance. Is to provide.

[0012]

In order to achieve the above object, the present invention has a circuit section for performing storage control in each of a plurality of photoelectric conversion regions, and the circuit section is provided with a different type of storage control. Formed on a single chip,
Circuit parts for performing storage control of different methods are mixed and formed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the illustrated embodiments.

FIG. 1 is a diagram showing the arrangement of an optical system of a single-lens reflex camera equipped with a focus detection device according to an embodiment of the present invention.

In FIG. 1, LNS is a zoom photographing lens, QRM is a quick return mirror, FSCRN is a focusing screen, ILC is a liquid crystal display device, PP is a pentaprism,
AEL is a photometric lens, SPC is a photometric sensor, EPL is an eyepiece lens, FPLN is a film surface, SM is a submirror,
MSK is a field mask, ICF is an infrared cut filter, F
LDL is a field lens, RM1 and RM2 are first and second reflecting mirrors, SHMSK is a light-shielding mask, DP is a diaphragm, AFL is a secondary imaging lens, and AFP is a reflecting surface AFP-.
1 and the prism member having the exit surface AFP-2, and SNS is the above-described line sensor having the cover glass SNSCG and the light receiving surface SNSPLN.

The prism member AFP has a reflection surface AFP-1 on which a metal reflection film such as aluminum is vapor-deposited, reflects the light flux from the secondary imaging lens AFL, and emits the light from the emission surface AF.
It has a function of polarizing P-2.

FIG. 2 is a diagram showing a schematic configuration of the focus detection device.

In FIG. 2, MSK is a visual field mask, which has a cross-shaped opening MSK-1 in the center and vertically long openings MSK-2 and MSK-3 in the peripheral portions on both sides. F
LDL is a field lens and corresponds to the three openings MSK-1, MSK-2, MSK-3 of the visual field mask, and three parts FLDL-1, FLDL-2, FLDL.
-3. DP is a diaphragm, and there are a total of four openings DP-1a and DP-1 in the center, one pair vertically and horizontally.
b, DP-4c, DP-4d, and a pair of openings DP-2a, DP-2b and DP-3 on the left and right peripheral portions.
a and DP-3b are provided respectively.

Each region F of the field lens FLDL
LDL-1, FLDL-2, FLDL-3 have the function of forming an image of these aperture pairs DP-1, DP-2, DP-3 near the exit pupil of the objective lens (not shown).

AFL consists of 4 pairs of 8 lenses AFL-1.
a, AFL-1b, AFL-4a, AFL-4b, AF
L-2a, AFL-2b, AFL-3a, AFL-3b
Is a secondary imaging lens made up of, and is arranged behind the aperture DP corresponding to each aperture. SNS is 4 vs. 8 in total
Two sensor arrays SNS-1a, SNS-1b, SNS-4
a, SNS-4b, SNS-2a, SNS-2b, SN
A line sensor composed of S-3a and SNS-3b,
Each secondary imaging lens AFL is arranged so as to receive the image thereof.

In the present embodiment, the sensor row pair SNS-1 and SNS-4 in the central area, which is frequently used, is P / B controlled, and the sensor row pair SNS-2 and SNS-3 in the peripheral area is P.
/ D control is used.

In the focus detection system shown in FIG. 2, when the focus of the taking lens is in front of the film surface, the subject images formed on each pair of sensor rows are close to each other and the focus is in the rear. In this case, the subject images are separated from each other. Since the relative position displacement amount of the subject image has a specific functional relationship with the defocus amount of the photographing lens, if an appropriate calculation is performed for each sensor output in each sensor row pair, the defocus amount of the photographing lens, A so-called defocus amount can be detected.

FIG. 3 is a block diagram showing an example of a concrete circuit configuration of the camera having the above configuration.

In FIG. 3, PRS is a control circuit of the camera, for example, a CPU (central processing unit), ROM, R
It is a one-chip microcomputer having an AM and A / D conversion function. The control circuit PRS performs a series of camera operations such as an automatic exposure control function, an automatic focus adjustment function, and film winding / rewinding in accordance with the camera sequence program stored in the ROM. Therefore, the control circuit PRS is provided with communication signals SO, SI, SCL.
K and the communication selection signals CLCM, CSSDR, and CDRD are used to communicate with the peripheral circuits in the camera body and the control device in the lens to control the operation of each circuit and the lens.

SO is a data signal output from the control circuit PRS, SI is a data signal input to the control circuit PRS, and SCLK is a synchronous clock of the signals SO and SI.

LCM is a lens communication buffer circuit,
When the camera is operating, power is supplied to the lens power supply terminal VL, and the selection signal C from the control circuit PRS is supplied.
When the LCM is at a high potential level (hereinafter abbreviated as "H" and a low potential level is abbreviated as "L"), it serves as a communication buffer between the camera and the lens.

The control circuit PRS controls the communication selection signal CLC.
When M is set to “H” and predetermined data is transmitted as the signal SO in synchronization with the synchronization clock SCLK, the lens communication circuit LCM causes the SCL to communicate via the camera-lens communication contact.
The buffer signals LCK and DCL of K and SO are output to the lens. At the same time, the buffer signal of the signal DLC from the lens is output to SI, and the control circuit PRS outputs SCLK.
The lens data is input from SI in synchronization with.

DDR is a circuit for detecting and displaying various switches SWS, which is selected when the signal CDRD is "H" and controlled by the control circuit PRS using SO, SI and SCLK. That is, the display of the display unit DSP of the camera is switched based on the data sent from the control circuit PRS, and the on / off states of various operation members of the camera are notified to the control circuit PRS by communication.

SW1 and SW2 are switches interlocked with a release button (not shown). The switch SW1 is turned on when the release button is pressed in the first step, and the switch SW2 is turned on when the release button is pressed in the second step. The control circuit PRS performs photometry and automatic focus adjustment when the switch SW1 is turned on, and exposure control and subsequent film winding are triggered by turning on the switch SW2.

The switch SW2 is an "interrupt input terminal" of the control circuit PRS which is a microcomputer.
When the switch SW1 is turned on, an interrupt is generated when the switch SW2 is turned on, and control can be immediately transferred to a predetermined interrupt program.

MTR1 is a film feeding motor, MTR2 is a motor for mirror up / down and shutter spring charging, and forward and backward control is performed by respective drive circuits MDR1 and MDR2. The signals M1F, which are input from the control circuit PRS to the drive circuits MDR1 and MDR2,
M1R, M2F and M2R are signals for motor control.

MG1 and MG2 are magnets for starting shutter front and rear curtain running, respectively, which are energized by signals SMG1 and SMN2 and amplification transistors TR1 and TR2, and a control circuit P.
Shutter control is performed by RS.

The motor drive circuits MDR1 and MDR2
Since the control of 1 and the shutter control are not directly related to the present invention, detailed description thereof will be omitted.

The signal DCL input to the in-lens control circuit LPRS in synchronization with LCK is the signal from the camera to the lens LNS.
Command data, and the lens operation in response to the command is predetermined. The in-lens control circuit LPRS analyzes the command according to a predetermined procedure, and performs the focus adjustment and diaphragm control operations, the operation status of each part of the lens from the output DLC (driving status of the focusing optical system, diaphragm driving status, etc.), Various parameters (open F number, focal length, coefficient of defocus amount versus movement amount of focus adjustment optical system, etc.) are output.

In this embodiment, an example of a zoom lens is shown, and when a focus adjustment command is sent from the camera, the focus adjustment motor LTMR is driven by the signal LMF, in accordance with the driving amount and direction sent at the same time. Driven by the LMR, the optical system is moved in the optical axis direction to perform focus adjustment. The movement amount of the optical system is monitored by a pulse signal SENCF of an encoder circuit ENCF which outputs a number of pulses corresponding to the movement amount by detecting a pattern of a pulse plate which rotates in conjunction with the optical system by a photocoupler, The coefficient is calculated by the counter in the lens control circuit LPRS, and when the predetermined movement is completed, the lens control circuit LPRS itself outputs the signals LMF and LMR.
Is set to "L" to control the motor LMTR.

Therefore, once the focus adjustment command is sent from the camera, the control circuit PRS of the camera does not need to be involved in the lens driving at all until the lens driving is completed. Also, the contents of the counter can be sent to the camera when requested by the camera.

When a diaphragm control command is sent from the camera, a stepping motor DMTR known for driving diaphragms is driven in accordance with the number of diaphragm stages sent at the same time. Since the stepping motor DMTR can be open-controlled, it does not need an encoder for monitoring the operation.

ENCZ is an encoder circuit attached to the zoom optical system, and the in-lens control circuit LPRS inputs the signal SENCZ from the encoder circuit ENCZ to detect the zoom position. Lens parameters at each zoom position are stored in the in-lens control circuit LPRS, and when there is a request from the control circuit PRS on the camera side, the parameter corresponding to the current zoom position is sent to the camera.

SPC is a photometric sensor for exposure control that receives light from a subject through a taking lens, and its output SSPC is input to an analog input terminal of the control circuit PRS, and after A / D conversion, according to a predetermined program. , Used for automatic exposure control.

SDR is a sensor drive circuit of a line sensor SNS for focus detection which is composed of a CCD or the like, and an output S of a sensor SRM for receiving a signal from a remote controller (not shown).
SRM processing circuit, which is selected when the signal CSDR is "H" and uses SO, SI, SCLK to control circuit P
It is controlled by RS.

The signals φSEL0 and φSEL1 supplied from the sensor drive circuit SDR to the line sensor SNS are the signals SEL0 and SEL1 themselves from the control circuit PRS, and φ
When SEL0 = “L” and φSEL1 = “L”, the sensor array SNS-1 (SNS-1a, SNS-1b) is changed to φSE.
Sensor array SNS when L0 = “H” φSEL1 = “L”
-4 (SNS-4a, SNS-4b), φSEL0 =
When "L" and φSEL1 = "H", the sensor array SNS-2
(SNS-2a, SNS-2b), φSEL0 =
When “H” and φSEL1 = “H”, the sensor array SNS-3
This is a signal for selecting each of (SNS-3a, SNS-3b).

After the accumulation is completed, the signals SLE0 and SEL1 are appropriately set, and then the clocks φSH and φHRS are sent, whereby the signals SEL0 and SEL1 (φSEL
0, φSEL1) output the image signal of the sensor array selected
It is output serially from VOUT.

VP1, VP2, VP3 and VP4 are sensor arrays SNS-1 (SNS-1a, SNS-1), respectively.
b), SNS-2 (SNS-2a, SNS-2b), S
NS-3 (SNS-3a, SNS-3b), SNS-4
(SNS-4a, SNS-4b) storage control signal,
The voltage rises with the start of accumulation, whereby accumulation control of each sensor array is performed. As described above, the storage control signals VP1 and VP4 are signals of the P / B system, and the storage control signals VP2 and VP3 are signals of the P / D system.

Signals φRES and φVRS are sensor reset clocks, φHRS and φSH are image signal read clocks, and φT1, φT2, φT3 and φT4 are clocks for ending the accumulation of each sensor row pair.

Output VIDEO of the sensor drive circuit SDR
Is an image signal obtained by amplifying the image signal VOUT from the line sensor SNS with a gain determined by the signal level.
The output VIDEO is input to the analog input terminal of the control circuit PRS, and the control circuit PRS, after A / D converting the same signal,
The digital value is sequentially stored in a predetermined address on the RAM.

Signal / TINTE 1, / TINTE 2, / TINTE
3, / TINTE 4 is a sensor array SNS-1 (SN
S-1a, SNS-1b), SNS-2 (SNS-2)
a, SNS-2b), SNS-3 (SNS-3a, SN
S-3b), SNS-4 (SNS-4a, SNS-4)
The control circuit PRS receives the signal indicating that the charge accumulated in b) becomes appropriate and the accumulation is completed, and executes the reading of the image signal.

The signal BTIME is a signal for giving the timing for determining the read gain of the image signal amplification amplifier in the sensor drive circuit SDR. Normally, the sensor drive circuit SDR mentioned above is the storage control signal at the time when this signal becomes "H". VP1 to VP4
The read gain of the corresponding sensor array is determined from the voltage of. Specifically, the control circuits PRS to SCLK, S
It is determined by the vertical relation between the comparison level generated based on the gain determination data sent by using O and the levels of the monitor signals VP1 to VP4 at the timing of the signal BTIME. In this embodiment, this comparison level is common to the monitor signals VP1 to VP4.

CK1 and CK2 are the above clock φRES,
It is a reference clock given from the control circuit PRS to the sensor drive circuit SDR in order to generate φVRS, φHRS, and φSH.

The control circuit PRS sets the communication selection signal CSDR to "H" and sends a predetermined "accumulation start command" to the sensor drive circuit SDR, whereby the line sensor SN
The accumulation operation of S is started.

As a result, the subject image formed on each sensor is photoelectrically converted by the four sensor row pairs, and electric charges are accumulated in the photoelectric conversion element portion of the line sensor SNS. At the same time, the storage control signals VP1 to VP4 of the respective sensors rise, and when this voltage reaches a predetermined level, the sensor drive circuit SDR makes the signals / TINTE1 to / TINTE4 independently "L".

In response to this, the control circuit PRS receives the clock C
A predetermined waveform is output to K2. The sensor drive circuit SDR uses clocks φSH and φHR based on the reference clock CK2.
S is generated and given to the line sensor SNS, the line sensor SNS outputs an image signal according to the clock, and the control circuit PRS synchronizes with CK2 output by itself and has an analog input terminal with an internal A / D conversion function. After the A / D conversion of the output VIDEO input to the
The data is sequentially stored in a predetermined address of M, a predetermined focus detection calculation is performed, and the defocus amount of the photographing lens is obtained.

The operation of the sensor drive circuit SDR and the line sensor SNS is disclosed in Japanese Patent Application Laid-Open No. 63-216905 as a focus detection device having two pairs of sensor lines. Omit it.

FIG. 4 shows the line sensor SNS shown in FIG.
3 is a simple block diagram for explaining the configuration of FIG.

The drive signal generator 301 outputs a signal φSE for selecting a sensor row pair from the sensor drive circuit SDR.
L0, φSEL1, and other reset clock signals φRES, φVRS, and image signal read clock φHR
S, φSH, accumulation end clocks φT1, φT2, φT
3, φT4 is input. And each sensor row pair SNS
The signals generated based on the above input signals are input to the -1 to SNS-4 and its peripheral circuits 302 to 306.

In this embodiment, the central visual field (sensor array pair SNS-1, SNS-) which is considered to be frequently used is used.
The accumulation control for 4) is P / B control, and the control for the peripheral visual field (sensor array pair SNS-2, SNS-3) is P / B control.
Since the D control is used, the sensor array pair SNS-1, SNS-
The peripheral circuit of No. 4 includes not only the maximum value detection circuit 302-2 but also the minimum value detection circuit 303-2. on the other hand,
In the sensor array pair SNS-2 and SNS-3, the dark output value is used instead of the minimum detection value.

The maximum detection result, the minimum detection result, or the dark output value of each sensor row pair is determined by the differential amplifier OP1 to OP.
4 and their outputs are stored control signals VP1 to VP.
It is output as 4. On the other hand, the image signal of each sensor array pair is output as an image signal output VOUT by the shift registers 306-1 to 306-4 through the buffer circuits BUF1 to BUF4.

FIG. 5 shows the maximum value detection circuit 30 shown in FIG.
2-1 to 302-4 are partial diagrams (n and n + 1th pixel) of an equivalent circuit for explaining the configuration and function of 2-1 to 302-4.

As shown in the figure, in order to obtain the maximum detection value Vp, a combination of a comparator COMPn, AMPn serving as a buffer, and a switch SWn is set for each pixel. The minimum value detection circuits 303-2 and 303-4 have the same configuration, and it can be considered that the determination criteria of the comparators are reversed.

For the maximum detected value Vp at the present time, "V
The operation will be described in the case of “n> Vp” and “Vn + 1 <Vp”. The switch SWn is turned on by the “H” output of the comparator COMPn by “Vn> Vp”, and Vn buffered by AMPn is output to the maximum detection line. Output, Vp = V
n. On the other hand, the comparator COMPn + 1 is "Vn + 1 <
It remains off because of "Vp" and has no effect on the maximum detection line. In this way, the maximum value can always be detected.

The description of the minimum value detection circuits 303-2 and 303-4 will be omitted because they are similar, but since both require a comparator and a buffer for each pixel, the area occupied on the chip device is considerable. Become.

Therefore, in this embodiment, the storage control method is selectively used for each area according to the frequency of use, and more specifically, the control method (P / D) having a small circuit scale is used in the area of low frequency of use.
Method) and a control method with a large circuit scale (P / B method) in a frequently used area so as to suppress the increase in the chip area as much as possible while maintaining practical performance.

In the above embodiment, the control method is switched depending on the frequency of use depending on the arrangement of the distance measurement (focus detection) field of view as shown in FIG. 6A, but as shown in FIG. 6B. Considering a structure having areas at four corners, the sensor array pair SNS-
Since na and SNS-nb are not the object of the optical axis, it is optically impossible and highly accurate distance measurement cannot be expected. Therefore, the control method is switched from the viewpoint of a region in which high precision is not expected in the arrangement (the P / D system is used for the four corner regions and the P / B system is used for the central region) to suppress an increase in the chip area. That is also effective. In other words, a control method with a small circuit scale (P / D method) is adopted in a region where high accuracy cannot be expected, and a control system with a large circuit scale (P / B method) is adopted in a region where high accuracy is desired. While maintaining the above performance, we are trying to minimize the increase in chip area.

(Modification) The present invention is described as applied to a camera such as a single-lens reflex camera, a lens shutter camera, a video camera, but other optical devices and other devices,
Furthermore, it can be applied as a constituent unit.

Further, although it is assumed that the present invention is applied to the focus detection area, the present invention is not necessarily limited to this. Further, as the storage control method, an example in which the P / D method and the P / B method are mixed is described. However, the average dark method and the P / B method described below are mixed, and three types of these methods are available. A mixture of methods may be used.

FIG. 7A is a diagram showing a circuit configuration for realizing the dark current reference average (average) value control system. The accumulation control unit 301 detects the output of dark pixels for darkness and focus detection. 1 for the entire longitudinal field of view of the sensor array
When it is detected by the differential amplifier 302 that the output difference between the storage control pixels serving as one sensor area has reached a certain level, the storage is terminated [this method is average dark (A
average-Dark), hereinafter referred to as A / D].

The feature of this A / D system is that even if a small number of pixels in the field of view have an extremely higher output than other pixels, the accumulation is continued until the entire field of view (average) has a constant level of output. . Therefore, in the P / D method described above, FIG.
Even when the sensor output is as shown in Fig. 7, the A / D method saturates an extremely high pixel output as shown in Fig. 7B, while the P / D method is difficult to detect. The output of can be fully extracted. However, the field of view for focus detection and the field of view for storage control are slightly shifted.

On the other hand, in terms of the circuit, the A / D method requires the addition of storage control pixels, but the P / D method does not require a maximum value detection circuit.

It is also possible to draw the output from the focus detection sensor to a common line and use it as the storage control output. However, some measures are taken so as not to affect the original focus detection output. Is required.

Therefore, these merits and demerits are taken into consideration in accordance with the sensor manufacturing process, and the optimum sensor structure is selected.

[0070]

As described above, according to the present invention,
A plurality of photoelectric conversion regions each have a circuit section for performing storage control, and the circuit section is formed so as to perform storage control of different methods, and storage control of different methods can be performed on a single chip. The circuit portions to be performed are mixed and formed.

Therefore, it is possible to reduce the chip area to the necessary minimum and to make it inexpensive, without actually degrading the information detection performance.

[Brief description of drawings]

FIG. 1 is a diagram showing an arrangement of optical systems of a single-lens reflex camera including a focus detection device according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a main configuration of the focus detection device of FIG.

FIG. 3 is a block diagram showing a specific configuration of the camera of FIG.

FIG. 4 is a block diagram showing a configuration of a line sensor SNS shown in FIG.

5 is a circuit diagram for explaining the configuration and operation of the maximum value detection circuit shown in FIG.

FIG. 6 is a diagram for explaining a case where the present invention is applied to another area.

FIG. 7 is a diagram for explaining characteristics of a general storage control method (A / D).

FIG. 8 is a diagram for explaining the characteristics of a general storage control method (P / D).

FIG. 9 is a diagram for explaining the characteristics of the same general storage control method (P / B).

[Explanation of symbols]

 PRS control circuit SNS-1 to SNS-4 sensor column pair OP1 to OP-4 differential amplifier VP1 to VP4 accumulation control signal 301 drive signal generator 302-1 to 302-4 maximum value detection circuit 303-1, 303-4 Minimum value detection circuit 304-1 to 304-4 Reset circuit 305-1 to 305-4 Transfer circuit 306-1 to 306-4 Shift register

Claims (5)

[Claims] 1. An information detecting device, characterized in that each of a plurality of photoelectric conversion regions has a circuit section for performing storage control, and the circuit section is formed to perform storage control of a different method. 2. A circuit section for performing the storage control of the different method has a different occupied area on a chip due to a difference in circuit scale, and a circuit section having a small circuit scale is formed in a region which is rarely used as a device. The information detecting device according to claim 1, wherein 3. The circuit section for performing the storage control of the different method is configured such that the occupied area on the chip is different due to the difference in the circuit scale, and the circuit section having a small circuit scale is placed in a region where high accuracy of detection cannot be expected. The information detection device according to claim 1, wherein the information detection device is formed. 4. The circuit section arranged in the region of low frequency of use is at least one of a circuit section performing accumulation control by a peak / dark method and a circuit section performing accumulation control by an average dark method, 3. The information detection device according to claim 1, wherein the circuit section arranged in the frequently used area is a circuit section that performs peak / bottom type accumulation control. 5. The circuit section arranged in the region where high accuracy cannot be expected is at least one of a circuit section that performs accumulation control by a peak / dark method and a circuit section that performs accumulation control by an average / dark method. 3. The information detecting device according to claim 1, wherein the circuit section arranged in the frequently used area is a circuit section that performs peak / bottom accumulation control.