JPS63169183A - Image sensing system - Google Patents

Abstract

PURPOSE:To reduce the number of connection wires to an external part, and to attain a high speed control without inducing the increase of a current consumption by constituting an image sensing system with two number of chips. CONSTITUTION:An A/D conversion function 54, which is included in an interface IC chip customarily, is arranged in the IC chip of a system controller 51, and an analog signal processing function 18 and a photoelectric converting part 15 are arranged in the IC chip of a photoelectric transducer 12. Accordingly, the system is constitute with two chips substantially. Thus, the number of the connection wires to the external part is reduced, and therefore, the control of the photoelectric converting part 15 goes to a high speed control without inducing the increase of the current consumption, and a focusing detection is made faster.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image sensing system, and more particularly to an image sensing system having a photoelectric conversion element and a system controller for controlling the photoelectric conversion element.

Conventional technology Single-lens reflex autofocus cameras typically include a photoelectric conversion element, a system controller, and an interface circuit that controls the photoelectric conversion element based on control signals from the system controller for focus detection. Here, the interface circuit also has a function of analog processing the output of the photoelectric conversion element and an A/D conversion function of converting the processed analog signal into a digital signal. However, in conventional image sensing systems, these photoelectric conversion elements, system controllers, and interface circuits are each formed by separate IC chips.

The problem that Hatsuko tries to solve: Therefore, in the conventional example, the number of signal lines connecting each chip increases, and the line capacitance (capacitance associated with external wiring) increases.
The drawback was that high-speed control was not possible due to large current consumption. Furthermore, since the unprocessed analog signal from the photoelectric conversion element is transmitted through an external signal line, there is also the problem that it is susceptible to external noise. Furthermore, since the number of connection points increases, it is also unfavorable from the viewpoint of productivity.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image sensing system in which the number of connection lines between chips can be reduced as much as possible.

Means for Solving the Problems The image sensing system of the present invention is a single chip having a photoelectric conversion element formed as one chip and an AID conversion function for A/D converting an analog output signal from the photoelectric conversion element. consisting of a system controller formed. The photoelectric conversion element is configured to include a control section that controls the photoelectric conversion section based on a control signal from a system controller, and an analog processing section that processes the output of the photoelectric conversion section into an analog signal.

Function As mentioned above, the A/D conversion function that was conventionally included in the interface IC chip is integrated into the system controller IC.
By providing the analog signal processing function and the photoelectric conversion control section within the chip and within the IC chip of the photoelectric conversion element, the system is essentially configured with two chips, so the number of external connection lines is significantly reduced. Therefore, the control of the photoelectric conversion unit does not cause an increase in current consumption (it becomes a high-speed control, and the focus detection is speeded up. Even if the integrated value output in the photoelectric conversion unit is small, the output is transferred within the photoelectric conversion element. Analog processing allows external (system controller)
It can be supplied as a sufficient analog signal.

Embodiment As shown in FIG. 1, the focus detection optical system (OF) constituting the focus detection device of the camera is an infrared optical system provided behind the planned focal plane (F) behind the photographic lens (1). A light cut filter (10), a condenser lens (2), a pair of re-imaging lenses (4a) (4b) with an aperture mask (3) located behind them, and these re-imaging lenses (
4a) A charge-coupled device (
A focus detection light receiving section (CCD) having a light receiving element (CCD) as a light receiving element.
It is composed of the main parts (6), (7), etc. of a photosensor array for AF (autofocus) as a component of RF).

When the above-mentioned AF photo sensor array is made of silicon, which has a relatively flat spectral intensity within visible light (V), it is possible to component (e.g. λ = 720 nm) (
Since the imaging point of U) moves to the rear of the intended focal plane (F) due to the axial chromatic aberration of the photographic lens (1),
In general, the image interval (zu) corresponding to a subject that contains many reflected light components is determined by visible light (V) [center of gravity (λ-560n
The image interval C1W (corresponding to the focal position detection signal) corresponding to the object containing a large number of reflected light components (s)) becomes larger than the image interval C1W (corresponding to the focal position detection signal).

FIG. 2 shows the configuration of an AF sensor module (MP) that integrates the focus detection device described above. This AF sensor module (MF) has a built-in mirror (8) for changing the optical path, and Above are the aforementioned condenser lens (2), field mask (9), and infrared light cut filter (which cuts infrared light in the wavelength range of 750 rv or more).
10) are arranged.

Here, the infrared light cut filter (lO) not only removes unnecessary infrared light and minimizes the negative effects of chromatic aberration, but also protects against long wavelength incident light seen in semiconductor line sensors such as CCDs. This also prevents the reliability of the goldfish signal from deteriorating due to increased variations in light sensitivity of each pixel.

Each of these components is supported by a lens holder (11), and is arranged perpendicularly to the optical axis converted by the optical path conversion mirror (8), including an aperture mask (3) and a pair of re-imaging lenses. It has a basic structure in which a substrate (5) having (4a) and (4b) and a photoelectric conversion element (12) containing the aforementioned photosensor array are supported.

FIG. 3 shows the configuration of the photoelectric conversion element (12) of the AF sensor module (MP).

In the photoelectric conversion element (12), a focus detection light receiving part (R
F) (in Fig. 3, the main parts (6) and (7) of the two photosensor arrays shown in the principle diagram of Fig. 1 are shown as continuous) , a pair of color temperature detection photodiodes (13)
(14) are lined up almost parallel to each other. Then, the two re-imaging lenses (4a) (4b) are used to detect the photo sensor array and color temperature detection photodiode (13).
) (14) A subject image is formed above.

Figure 4 shows the spectra of the photodiodes (PD'') that make up the color temperature detection photodiodes (13) and (14), and the dye filter placed above them, with wavelength on the horizontal axis and relative spectral sensitivity on the vertical axis. This shows the sensitivity characteristics.

Here, (13') shows the spectral sensitivity characteristics of the yellow dye filter and (14') shows the spectral sensitivity characteristics of the red dye filter.Therefore, the spectral sensitivity characteristics of the color temperature detection photodiodes (13) and (14) are shown in FIG. PD ”) to (13”) (14'
) are multiplied by each.

The color temperature detecting photodiodes view approximately the same subject through separate re-imaging lenses.

The graph in FIG. 5 is drawn together with the spectral energy distribution of light from various light sources. The horizontal axis is wavelength, and the vertical axis is relative spectral sensitivity or energy.

The curves (A), (B), and (C) in the figure are, respectively,
Light from standard light source A such as a tungsten lamp, sunlight,
It shows the spectral energy distribution of light from a white fluorescent lamp. Also, in the figure (13'), (14') and (PD'
) is based on Figure 4.

In addition, in the figure, the two-dot chain line (IR) at the position of 750n* is
The cut wavelength by the infrared light cut filter (10) described above is shown.

As will be described later, based on the output currents from the color temperature detection photodiodes (13) and (14), which are the pair of light receiving sections for color temperature correction, specifically, based on the ratio, the focus detection It is designed to detect the spectral energy distribution of the measurement light.

That is, as can be seen from the graph, the difference in output from both photodiodes (13) and (14) is significant.
Since the area is about 600n- or more, if the area of both is designed to be 1:1, the output from both photodiodes (13) and (14) will be almost the same for the light from the white fluorescent lamp, and the ratio is It is approximately 1.0. Furthermore, under the light of the standard light source A, since the light energy becomes significant at 60 on- or more, the ratio of the outputs from both photodiodes (13) and (14) is large, and is approximately 2.0. Furthermore, the distribution of light energy in the infrared light region of sunlight is approximately between the light from a white fluorescent lamp and the light from standard light source A, and the output from both photodiodes (13) (14) The ratio is approximately 1.5.

Further, a first color temperature detection photodiode (13),
The second color temperature detection photodiode (14) is provided on the same chip adjacent to a reference part and a reference part of the photodiode array part, which will be described later. There is.

Next, the structure of the photoelectric conversion element will be explained using FIGS. 6 to 13. First, as shown in FIG. 6, the photoelectric conversion element (12) includes a photoelectric conversion section (15) having a photodiode, a shift register, etc. that generates a photocharge according to the amount of irradiated light, and a photoelectric conversion section (15) that has a photoelectric conversion element (15) that generates photocharges according to the amount of light irradiated. A data output control unit (16) that controls charge transfer to the register side, control of charge transfer in the shift register, and signal processing timing of the analog processing unit (described later), integration time of the photoelectric conversion unit (15), etc. an analog processing section (18) that processes analog signals from the photoelectric conversion section (15), and a temperature control section (18) that processes analog signals from the photoelectric conversion section (15); Detection unit (19) and i10 control unit (2
0). And this photoelectric conversion element (
12) is formed as a one-chip IC with each of the above-mentioned components provided on one substrate.

The photoelectric conversion section (15) includes the aforementioned pair of color temperature detection photodiodes (13) (14), a photodiode array section (21), a photodiode array section (22), an accumulation section (23) for temporarily storing charge, Accumulation part clear game) (24
), a shift gate (25), and a shift register (26), and each output buffer thereof, that is, an output buffer (27) of the shift register (26), and a photodiode as described later. Monitor photodiode (MPD) inserted into the array
Output buffer (2 days) for color temperature detection photodiode (13) (14) (29) (3
0), a monitor output compensation signal output buffer (31) for dark-time correction of the monitor photodiode (MPD) output, and a color temperature detection signal (OSY) (O3
It is equipped with a reference voltage buffer (31'') for R).

Furthermore, color temperature detection photodiodes (13) (14)
and the buffer (29) (30), and between the monitor photodiode (MPD) and the buffer (28),
Furthermore, capacitors and switching transistors are provided in the preceding stages of the buffers (31) and (31'), respectively, and the details of these capacitors and transistors will be explained with reference to the specific circuit configuration of the photoelectric conversion section (15) shown in FIG. I will add this to the explanation. Data output control section (
16) is composed of a signal processing timing generation section and a transfer lock generation section, and generates a transfer lock (φl
) (φyo), it also generates a shift gate pulse (SR) to the shift gate (25). It also provides the analog processing section (18) with a signal useful for creating a timing signal for switching the sampling signal and the signal output from the photoelectric conversion element (12) to the outside.

The integration time control section (17) monitors the signal (AGCO5) given from the monitoring photodiode (MPD) of the photoelectric conversion section (15) through the buffer (28), and controls the barrier gate (22) and the accumulation according to the monitoring result. (23) and the storage section clear gate (24), respectively, to control the integration time by appropriately outputting control signals (BG) (S?) (STICG). (17) is the monitor signal (AGCO
5) is compensated for in the dark using the monitor output compensation signal (AGCooS) given from the buffer (31). The integral time control section (17) communicates signals with the system controller via the control section (20), among which the integral time control section (17) sends an integration completion signal (〒IN?) to the system controller. can be mentioned. Furthermore, this integral time control section (17) receives a command signal (
SHM), the integration is forcibly completed, but in order to correct the insufficient integration output accompanying this at the analog processing stage, an automatic gain control signal (8GC) is generated according to the integral value and analog processing is performed. Also give to the department (18),
The basic functions of the analog processing section (18) are the signal (O8) from the shift register (26) and the output signal (O5) from the color temperature detection photodiodes (13) (14).
Y) It performs various analog processing such as removing noise components from (O5R), dark output signal compensation, and automatic gain control. As will be described in detail later, this analog processing section (18) also has a configuration for performing reference voltage clamping in order to match the output signal with the dynamic range of the A/D conversion section of the system controller.

110 control section (20) includes a signal processing timing generation section (16B) and an integral time control circuit (16B) shown in FIG.
17b), refers to the human output buffers distributed in the transfer lock generation unit (16A),
10 The external device connected to the control section (20) is connected to the terminal (T
1) to (T, ) and (T++) (Lx), (T+
) (Tm) is an input terminal that receives a mode signal (MDI) (Mot) that selectively specifies an integration start mode, a low-intensity integration mode, a high-intensity integration mode, and a data dump mode that provides an integral output to the system controller; T,)
is the input terminal for the integration clear signal (ICS) related to the start of integration, (T4) is the data request terminal for forcibly ending the integration and requesting data from the shift register (26), (T, ) is the data A terminal (T,) is an input terminal for a basic clock (CP), which outputs an A/D conversion start signal (80T) to the outside (system controller) in the dump mode. Furthermore, (Ti+) is the integration completion signal (TINT
), and (TI□) are a group of terminals that output data (80C) for automatic gain control. Further, terminals (Ty) and (Ts) shown at positions apart from the I10 control section (20) are an input terminal for a power supply (Vcc) and a terminal for grounding, respectively. Further, (T,) is an analog signal output terminal, and (T,.) is an input terminal for a reference voltage (Vref).

Next, the specific configuration of each part of the photoelectric conversion element (12) will be described in detail. First, the entire photoelectric conversion section (15) is configured as shown in FIG. 7, and the portion including main elements such as photodiodes and shift registers will be explained using FIGS. 8 to 13. . As shown in FIG. 8, the photodiode array section (21) has a plurality of pixel photodiodes (PD) and monitor photodiodes (MPD) arranged therebetween, which are alternately arranged. One longitudinal end of each pixel photodiode is open, while the other end is coupled to the source of a first MO5 transistor (TR,) forming a barrier gate (22).

The drain of this MOS transistor (TI?,) is coupled to the next stage storage section (23), and the gate is coupled to the barrier gate signal supply terminal (32). Accumulation section (23)
is shielded from light by an aluminum film and is not irradiated with light, but it generates so-called dark charges. The output end of the storage section (23) is connected to a second MO forming the storage section clear gate 1-(24).
The source of the S transistor (TRz) and the third transistor forming the shift gate (25). lO5) transistor (TR
The drain of the second MO5) transistor (TRz) is coupled to the power supply terminal (T,) to which the power supply (Vcc) is applied, and the gate is connected to the storage section clear gate signal supply terminal (33). It is connected to the. On the other hand, the drain of the third M05) transistor (TR3) is coupled to the segment (26a) constituting the shift register (26), and the gate is connected to the shift gate signal supply terminal (34).
is combined with

The monitor photodiodes (MPDs) are connected to each other by photodiodes at the upper end of the figure, so the monitor output is the total output of the plurality of connected monitor photodiodes (MPDs).

By combining a plurality of monitoring photodiodes in this manner, a subject brightness monitoring photodiode device having a wide field of view can be realized.

The physical structure of the photodiode array section (21) is schematically illustrated in FIG. 9, which shows a cross section taken along the line A-A' in FIG. and an n-type region (37) by implantation method,
a channel stopper (38) made of Pl applied to the upper n-type region (37) to separate the pixel photodiode (PD) and the monitor photodiode (MPD);
It consists of a P0 film (39) provided on the surface to suppress the dark output of each photodiode and suppress the surface depletion layer. A positive potential is applied to the substrate (35) from the outside, and a ground potential is applied to the intermediate P wall region (36). Note that the n-type region (37) is formed by phosphorus implantation, and the P-wall region (36) is formed by boron diffusion.

By the way, the charge accumulated in the pixel photodiode (PD) mentioned above is transferred to the accumulation section (23) through the barrier gate (22).
) to the pixel photodiode CP
It is known that the length of D') is approximately proportional to the square of Il). On the other hand, as a focus detection device, the total area of each pixel photodiode (PD) is increased (by making the length thicker (by doing so, the total area of each pixel photodiode (PD) is thicker (
Therefore, it is desirable to increase the amount of generated charge. Increasing the width of the pixel photodiode (PD) is undesirable because it deteriorates the accuracy of the focus detection device.In order to satisfy these contradictory requirements, the present inventor developed We considered changing the depth of the n-type region (37) along the longitudinal direction. That is, as shown in FIG. 10(c), which is taken in the direction indicated by the dotted line (40) in the planar configuration diagram of FIG. 10(a), the structure of the main part (portion near the surface) is shown. Regarding the creation of the n-type region under (39), by changing the amount of phosphorus ion implanted along the longitudinal direction (left and right direction in FIG. 10), the n- region (37a) and the n-type region (37a) and
sI region (37b). In this way, the same figure (b
), the potential of the pixel photodiode (PD) gradually decreases toward the barrier gate (22), making it easier for the charge to move to the left (towards the barrier gate). This means that the time required to transfer the charge accumulated in the pixel photodiode (PD) is reduced. Therefore, it is possible to solve the problem of increasing the length (1) of the pixel photodiode (PD) in the longitudinal direction to increase the amount of charge generated by the photodiode and quickly transporting the generated charge toward the storage section. In FIG. 10, (41), (42), (43), and (44) are the electrodes of the barrier gate (22), the storage section (23), the shift gate (25), and the shift register (26), respectively.
Aluminum material is usually used to form these electrodes. (45) is an insulating film formed of 5iO1 or the like.

Next, the structure of the entire photoelectric conversion section will be explained with reference to FIG.

The pixel photodiode (PD), monitor photodiode (MPD), and barrier gate (22
), a storage section (23), a storage section clear gate (24), a shift gate (25), and a shift register (26) are arranged in large numbers in the horizontal direction, for example, the number of segments of the shift register (26) is In other words, there are 128 of them. However, as seen at the right end of the array, the pixel photodiode (PD), monitor photodiode (MPD)
), the barrier gate (22), the storage section (23), the storage section clear gate (24), and the shift gate (25) have five fewer segments on the right end side than the shift register (26). For example, shift register (26
) is formed five more segments on the right end side, and this is due to the following reason.

A capacitor (C) receives the output of the shift register (26).
1) is formed integrally with the shift register (26), specifically, as shown in the conventional example of FIG. (4
7) is formed by the junction capacitance generated between However,
A distribution volume 1i (C') is also generated between the light-shielding aluminum film (49) coated on the surface via the insulation U1 (4B) and the n area 46). This undesirable distribution volume 1
As shown in Fig. 11(c), i(C') is connected in parallel to the original capacitor (C,) formed of junction capacitance, increasing the output capacitance and resulting in a decrease in photosensitivity. . Moreover, the distributed capacitance (C') generated between the light-shielding aluminum film (49) and the n''' region (46)
There is a lot of variation, which causes variations in photosensitivity from product to product, which is undesirable. Therefore, as shown in FIG. 11(b), the aluminum film (49) located in the output stage portion is
(50). In this way, the distribution capacitance W(C') almost disappears 1, the output capacitor (C1) is hardly affected, and the photosensitivity increases.

On the other hand, the removed portion is shielded from light by a visual field mask (9) shown in FIG. That is, the junction capacitance portion as the capacitor (C1) is covered with a field mask (9).
) is placed away from the window. This is not limited to the capacitor (C,) provided at the output stage of the shift register (26), but also removes the Narminiram film above the capacitors (C3) to (C6) provided at each output stage. has been done.

Figure 12 shows this configuration as a schematic square shape of the photoelectric conversion unit (15) seen from the field mask side, where (51) indicates the photodiode array (21) and color temperature detection photodiodes (13) (14). The light receiving part consists of (52
) represents the projection of the window of the field □ mask (9), and the condensers (C, ) to (C6) are placed at a distance 1 from the projected image of the window, and therefore at a position where no light hits. Here, the opening areas of the capacitors (Ct) to (C1) are set equal to each other. With this configuration, the output voltages of the capacitors (C1) to (C6) can be made equal for the same output from the light receiving elements of the same size. These capacitors (C8) to (C6
), only the capacitor (C1) is located further away from the shift register segment corresponding to the light receiving part, so a segment is required to connect them, and this segment is shown in Figure 7. These are the first to fifth segments shown. Therefore, these five segments merely function as photo-charge transfer paths. Since the capacitors (Ct) to <cb> directly input the output of the light receiving section, there is no need for extra segments as mentioned above.The output of the shift register (26) is a transistor ( Transfer lock (φ1) (
φ) is applied to the capacitor (C3) and output through the buffer (27).

In FIG. 7, among the pixel photodiodes (PD') and monitor photodiodes (MPD), the five on the right end,
The three on the left end are shielded from light by an aluminum film. These light-shielded photodiodes generate a dark charge that is used, for example, for dark correction of the output of the pixel photodiode. A part of the photodiode array (21) is a reference part (M.) and another part is a reference part (M,).
Assigned as

For example, the standard part (MO) is for 40 parts, and the reference part (L) is for 50 parts.
It includes a combination of individual pixel photodiodes and a monitor photodiode. However, structurally, the standard part (M.)
There is no distinction between the reference section (M) and the reference section (M,), and they are distinguished by software processing in the system controller, which will be described later.

Regarding the unnecessary parts between the standard part (M.) and the reference part (M,), only the shift register (26) is left, and other pixel photodiodes, monitor photodiodes, barrier gates, storage parts, and storage parts are removed. The clear gate and shift gate have been deleted from the drawing. This deleted part (
Each segment (26a) of the shift register corresponding to the deleted portion (S), indicated by S), has a different pitch in order to reduce the number of transfer locks required to transfer all pixel outputs and shorten the total charge transfer time. It is formed to be larger than the pitch of the part.

The monitor photodiodes (?1PD) are connected to each other so that only those located in the standard part (hyu) and reference part (Ml) are used, and those located in other parts are not used. The unused monitor photodiode (MPD) is also connected to the power supply terminal (as shown in Figure 13).
It is desirable to stabilize it by connecting it to T7). This is because if it is electrically floating, it will receive induction from other pixel photodiodes or cause induction to other pixels, eventually affecting other pixel photodiodes. The output of the monitor photodiode is directly applied to a capacitor (Cz), where it is held and output as a monitor signal (AGCO5) via a buffer (28).

In order to remove power supply fluctuations and temperature-dependent components of this monitor signal (AGCO5), a transistor (O3) having the same configuration as the initialization transistor (aX) of the capacitor (CZ) is used.
) is simultaneously prepared for the output (AGCDO3) from the capacitor (C1). A photodiode (D,) which is shielded from light by an aluminum film and has approximately the same size as a monitor photodiode (MPD) is connected to this capacitor (C1) as shown in the figure. Transistors (O2) (O3) are integrated clear gate signal (ICG
) is turned on simultaneously during the application period.

Next, a pair of color temperature detection photodiodes (13) (1
4) are respectively arranged in the standard part (M.) and the reference part (Ml) as shown in the figure, and these two photodiodes (
13) The output of (14) is the integral clear gate signal (IC
The capacitor (C,) (C5) is initialized by the transistor (Q&) (Qt) that is turned on at G), and the transistor (port a) (Qs) is turned on by the color temperature detection gate signal (PDS), respectively. Output as temperature detection signal (OSY) and red temperature detection signal (OSR). These color temperature detection photodiodes (13
) A color filter (not shown) is provided on the surface of (14). Here, the output buffer following the shift register (26), the output buffer for the red temperature detection signal, and the output buffer for the yellow temperature detection signal are formed identically, and
By setting the sizes of the pixel photodiode (PD) and the color temperature detection photodiodes (13) (14) to be approximately the same, the yellow temperature detection signal (OSY) and red temperature detection signal (OSR) can be output. The voltage is the reference part (M.),
It is output as the product of the average output of the pixel photodiode of the reference section (MI) and the transmittance of the color filter. Therefore,
This red temperature detection signal (OSR) and yellow temperature detection signal (
OSY) has approximately the same dynamic as the output voltage of the pixel photodiode (PD), and can be used as a processing circuit for the pixel signal (O3) by processing it in a time-division manner in a subsequent analog processing section. Furthermore, since the size of the color temperature detection photodiodes (13) and (14) is the same as the size of the light-shielded pixel photodiode (OPD), the difference between the output voltage of the light-shielded pixel photodiode (OPD) must be taken. It is also possible to compensate for dark output. In addition, FIG. 7 shows the color temperature detection signal (OSY
) (OSR) output to remove power supply noise etc.
A capacitor (C1) that generates PDDO9) and a switching transistor (O8) are also provided.

In Fig. 7, color temperature detection photodiodes (13) (1
4) output signal (OSY) (OSR) is connected to a separate transistor (port 4) (Qs) and capacitor (C4) (c
s), buffers (29), (30), etc., but it is also possible to take out using the output system of the pixel output (O5) without installing a separate output system like this. It is.

FIG. 13 shows an embodiment based on this viewpoint, in which any one of the three light-shielding pixel photodiodes (OPDs) arranged on the left side of FIG.
), and the output signal of the red temperature detection photodiode (14) is sent to the shift register (26) using the barrier gate, storage section, and shift gate sequentially coupled thereto. This output signal is transferred from the shift register (26) to the capacitor (C+
) and further output via a buffer (27). FIG. 13 shows the red temperature detection photodiode (14) corresponding to the reference part (Ml) as described above, and one end of the second light-shielded pixel photodiode (OPD) from the left end that is shielded with an aluminum film is connected to the other end. The reference part (M) is formed longer than the pixel photodiode and is connected to the output end of the red temperature detection photodiode (14).
The output end of the yellow temperature detecting photodiode (13) corresponding to the yellow temperature detecting photodiode (13) is similarly formed long and connected to any one of the five one-blocking pixel photodiodes (OPD) on the right side in FIG.

Next, FIG. 14 shows the photoelectric conversion section (15) as one block, and also shows other parts of the photoelectric conversion element (12) in detail, and also shows the system controller (
53) and its peripheral circuits.

The system controller (53) is formed by a one-chip microcomputer, and includes the photoelectric conversion element (1).
A/D converter (54) that converts the analog signal (Vout) from R inputs data such as focus amount, lens extension amount conversion coefficient (KL), color temperature defocus amount (dpt), etc. in advance, and stores digital data from the A/D converter (54) one by one.
A memory part (55) formed of AM, and the memory part (55)
a focus detection section (55) that detects the focus based on the output of the
6), a correction calculation unit (57) that calculates a correction amount from the detected focus data and lens data, etc., and sends a signal for driving the lens to a lens drive circuit (63) based on the correction amount. In addition, to monitor whether the integral value at the lens drive control section (58) that receives data on the movement status of the lens from the motor encoder section (64) and the photoelectric conversion section (15) reaches a predetermined value in a predetermined time. A timer circuit (59) for measuring time and a photoelectric conversion element (12)
) and the sensor control section (60
). In addition, (65) is the lens drive motor, (
62) is a display circuit controlled by the system controller (53). The photoelectric conversion element (12) and the system controller (53) are each formed separately with one chip each, so that the image sensing system is composed of two chips in total.

The integral time control section (17) in FIG. 6 includes a brightness determination circuit and an integral time control circuit, and in FIG. 14, this brightness control circuit (17a) and the integral time control circuit (1
7b) is shown separately. Further, the signal processing timing generation section (16B) shown in FIG. 14 is included in the data output control section (16) shown in FIG.

The I10 control section (20) in FIG. 6 is distributed into the signal processing timing generation section (16B), the integral time control circuit (17b), and the transfer lock generation section (16A) in FIG. 14. The system controller (53) first provides a basic clock (CP) to the photoelectric conversion element (12). This basic tarlock (CP) is the transfer lock generation unit (1
6A) and an integral time control circuit (17b), respectively. The system controller (53) also sends a mode signal (MDI) (MDx) to the photoelectric conversion element (12).
)give. The mode signal consists of 2 bits,
Four modes can be expressed: initialization mode, low brightness integral mode, high brightness integral mode, and data dump mode of the photoelectric conversion element (12), and are transmitted using two lines.

In the initialization mode, the transfer lock generation section (1
6A) to the photoelectric conversion unit (15) is a transfer lock (φ,
) (φ2) is supplied at a high frequency, and the charge that has been unnecessarily accumulated in the shift register (26) before the transfer lock is supplied is discharged to the capacitor (C3) on the output side of the shift register (26). The charge discharged to this capacitor (C,) is transferred to the reset signal (OSR) by the transistor (Ql) in Figure 7.
5↑) When turned on, it is discharged to the power supply (Vcc). In addition, in the initialization mode, the analog processing section (18)
is also initialized.

Next, the system controller (53) first instructs the low brightness integration mode and supplies an integration clear signal (rcs) shown in FIG. 16 to the integration time control circuit (17b). By inputting this integral clear signal (IC3), the integral time control circuit (17b) controls the integral clear signal (IC3).
), the integral clear gate signal (ICG), the barrier gate signal (BG), and the storage section clear gate signal (ST
ICG) is generated and applied to a predetermined portion of the photoelectric conversion unit (15) shown in FIG. Integral clear gate signal (
ICG) is the monitor output signal (AGCOS), monitor output compensation signal (AGCDOS), color temperature detection output signal (
OSR) (OSY), color temperature detection compensation signal (FDDO
5), respectively, and on the other hand, the barrier gate signal (B
G) and the storage section clear gate signal (STICG) initialize the pixel photodiode (PD) and the storage section (23).

When the integral clear signal (ICS) disappears, the integral clear gate signal (ICG), barrier gate signal (BG),
The storage unit clear gate signal (STICG) also disappears. As a result, the transistor (at) (O2) turns off, and the capacitor (Ct), which was initially charged to the power supply voltage (Vcc), begins to drop in voltage in proportion to the charge generated by the monitor photodiode (MPD). , capacitor (C
3) drops the voltage slightly in response to a small amount of charge generated by the photodiode (D+) that is shielded from light. Also, (PDS)
is given to the transistor (O4), and the capacitors (Ca) (Cs) also change from the initial power supply voltage (Vcc) to the photodiode (1) for color temperature detection.
3) Drop the voltage according to the amount of charge generated in (14). On the other hand, the barrier gate (22) and the power storage unit clear gate (24) are turned off, and as a result, the pixel photodiode (PD) starts generating and accumulating photocharges in response to the irradiation light, and the light-shielding photodiode (MPD) starts generating and accumulating photocharges. The dark output charge starts to accumulate. Furthermore, an accumulation section (23)
Then, the dark output charge generated by itself is accumulated.

As can be seen from FIG. 16(a), for the integral clear signal (IC5), the aforementioned (BG) (STICG)
(TCG) have the same pulse width. Therefore,(
The pulse width of IC5) is determined by the pulse width of the pixel photodiode (PD) to remove all charges previously accumulated (i.e. before initialization) to the barrier gate (22), the accumulation section (23), and the accumulation section clear gate (24). Power supply (Vcc) through
It is limited by the time required to discharge the water to the Specifically, the pulse width is selected to be 50 μs to 100 μs or more.

The integration operation of the photoelectric conversion unit (15) does not need to be performed forever; rather, it must be completed at some point, because once the integral value reaches a predetermined level, there is no need to continue integrating it any further. In addition, if it takes a long time for the integral value to reach a predetermined level, the time from pressing the shutter button to being able to release the camera will be significantly longer, so it is necessary to complete the integral midway and avoid shortfalls in the integral value. This is because it is better to correct the amount at the signal processing stage.

The brightness determination circuit (17a) determines the integration state from the monitor output signal (AGCOS) of the monitor photodiode (MPD) and the monitor output correction signal (AGCDOS), and when it reaches a predetermined value, Generates an instruction signal (VFLG) to instruct the integration time control circuit (
17b), and also outputs a gain control signal (AGC) corresponding to the shortfall in the integral value. Its gain control signal (A
GC) is supplied to an AGC subtraction circuit (71).

The AGC@ calculation circuit (71) receives the input pixel output signal (O
3) and the gain of the color temperature detection output signal (OSR) (OSY). The AGC subtraction circuit (71) also has a function of performing dark output compensation of the pixel output signal (O8), as will be described later. AGC data is also supplied to the system controller (53). The system controller (53) determines whether or not to emit an auxiliary light (not shown) based on AGC data.
This is to enable judgment to be made. A specific configuration of the brightness determination circuit (17a) is shown in FIG. 15. 15th
In the figure, the block indicated by the dotted line (17a) is the brightness determination circuit, and the other dotted line blocks are the AGC subtraction circuits (71
), the brightness determination circuit (17a) calculates the monitor output compensation signal (AGCDOS) through resistors (R) (2R) (4R) (8R) whose resistance values are 1x, 2x, 4x, and 8x. Amplifier (A+) (At) (A+) (A
4) is applied to the positive input (+). At this time, a constant current (1) flows through each resistor due to the constant current source (B), so the voltage drop due to the resistor is 1 times, 2 times, and 2 times, respectively.
The relationship is 4x and 8x. Operational amplifier (A,) ~ (A4
) is connected to the negative input terminal (-) of the monitor output signal (A
GCOS) is supplied, and the outputs are (AGCOS) and (A
However, as shown in Figure 7, there are capacitors (CZ) and (C1), transistors (Q2) and (Q, ), buffers (28) and (3) on the same chip.
1) are designed identically, so both signals (
AGCOS) and (AGCDOS) are at the same potential immediately after the integral clear gate signal (ICG) is applied, and the monitor output signal (AGCOS) is the monitor photodiode (M
PD), the monitor output compensation signal (AGCDOS) remains unchanged and always maintains the initial potential of the monitor output signal. Therefore, by taking the difference between these signals, it is possible to monitor the amount of accumulated charge (integral value). Moreover, by taking the difference between the two signals, fluctuations in the power supply voltage can be canceled.Furthermore, if the dark output increases due to temperature rise, the light-shielding photodiode (D+) is sensitive to this, so the monitor output compensation signal (AGCDOS) ) includes the temperature fluctuation of the dark output, and the difference voltage between the two signals becomes a correct monitor information signal from which temperature effects are also removed. When it is considered that the integral value at the pixel photodiode (PD) has reached a predetermined value, the monitor output signal (A
GCOS) drops by I×8R from the initial potential, so
The instruction signal (VFLG) is generated from the operational amplifier (A4), and the control signal (VFLc) is generated by the integral time control circuit (1
7b). The integral time control circuit (17b) is
Instruction signal (vy.) or forced integration completion signal (SHM
), it causes the photoelectric conversion unit (15) to perform an integration completion operation, generates a latch signal (LCK), and sends this latch signal (LCK) to the D flip-flop of the brightness determination circuit (17a). (FF I) ~ (FF
The data terminals (D) of the D flip-flops (FFI) to (Fh), which are supplied to the clock terminal (CP) in 3), are connected to the operational amplifiers (A1) to (A,) in the preceding stage, respectively. It becomes a latch state depending on the value of the monitor output signal (AGCOS).

Each D flip-flop (FFI) (FFg) (FF
The output terminal of 3) is connected to the AND gate 1- (N,) (at) as shown in the figure, and as a result, the brightness judgment circuit (
17a) output path (72) (73) (74) (75
), gain control signals (8GC) corresponding to correction amounts of 1x, 2x, 4x, and 8x are output. Incidentally, in a situation where the instruction signal (VFLG) is output within a predetermined time managed by the system controller (53), (AGC) is generated in the output path (72).

However, within the predetermined time, the instruction signal (V, L,)
In a situation where no
An AGC signal will be generated in one of (74) and (75).

An explanation of the low luminance integration mode will be added using the time chart of FIG. 16(a). The integration operation starts in the photoelectric conversion unit (15) from the moment the integration clear signal (IC5) disappears, and after a while, when the monitor output signal (AGCOS) drops to a level corresponding to a predetermined integral value, the instruction signal (
VFLl,) is generated from the brightness determination circuit (17a).

In response to this, the integration time control circuit (17b) generates a storage section clear gate signal (STICG) to open the storage section clear gate (24) and remove the small amount of dark charge that was unnecessarily accumulated in the storage section (23). is discharged to the power supply (Vcc) side. Subsequently, the accumulation section clear gate (24) is closed by the disappearance of this accumulation section clear gate signal. After this, the integral time control circuit (17b) immediately switches on the barrier gate signal (B
G) is generated to open the barrier gate (22) and transfer the accumulated charge in the pixel photodiode (PO) to the accumulation section (23). It takes about 50~50 seconds from the generation of the instruction signal (Vyte) until the transfer operation to the storage section (23) is completed.
A time (1) of 100 μs is required. After the charges accumulated in each pixel photodiode (PD) are transferred to the accumulation section (23) in this way, the integration time control circuit (17) is transferred to the accumulation section (23).
b) provides an integration completion signal (TINT) to the system controller (53). In this example (TINT)
The transition from high level to low level represents the completion of the integration.

This integration completion signal (TINT) is accepted as an interrupt signal in the system controller (53), and even while the system controller (53) is performing other processing, the processing is not important and therefore interrupts are disabled. Unless the processing is performed in step 1, the recognition processing of the integration completion signal (TINT) is immediately performed. Furthermore, if the other process is an interrupt prohibition process, the system controller (53) processes the integration completion signal (TINT) at the time when that process is finished, based on this integration completion signal (TINT). After setting the address etc. for storing image information data in the memory section (55), the photoelectric conversion element (12)
A shift pulse generation signal (SHM) is supplied to the transfer lock generation section (16A) inside. As a result, the transfer lock generation section (16A) generates a shift pulse (SH), and applies this shift pulse (SH) to the shift gate 1-(25) of the photoelectric conversion section (15), and then transfers the shift pulse (SH) to the shift gate (25) of the photoelectric conversion section (15). The charge accumulated to the proper integration level, which has already been transferred to the shift register (26), is transferred to the shift register (26). Thereafter, the system controller (53) immediately sends the mode signal (MD
I) (Gives a data dump mode signal to the photoelectric conversion element (12) as MD, and sets the photoelectric conversion element (12) to data dump mode. In the above, the system controller (53) outputs the integration completion signal (TINT). )
Even if it is not possible to recognize the completion of integration due to interrupt disabling processing for about 10IIs after reception of the pixel photodiode (PD) and the storage section (2
3) Since the barrier gate signal (BG) disappears and the barrier gate (22) becomes non-conductive, the charge accumulated in the pixel photodiode (PD) during the 1OIIIs is transferred to the accumulation section (23). It has no effect on the accumulated desired charge, and its Loss
Since the signal (ST) is set to a low level in order to raise the potential level of the storage section during the interval s (details will be described later), the dark charge generated in the storage section (23) itself and added to the desired charge. is extremely small and poses no problem.

In FIG. 16(a), from the time when the integration completion signal (TINT) is inverted to low level, the shift pulse generation signal (S
HM) and a shift pulse (SHM) approximately synchronized with the (SHM).
The slight delay in the generation of SH) indicates that the processing of the integration completion signal (TINT) in the system controller (53) is delayed.

The integration time control circuit (17b) receives a barrier gate signal (
The color temperature detection gate signal (P
DS) also occurs. This color temperature detection gate signal (PDS
) is the color temperature detection photodiode (13) during the period corresponding to the integral clear gate signal (ICG).
(14) The charge that was unnecessarily accumulated in the capacitor (C
4) Color temperature detection photodiodes (13) (14) and capacitor CCa> (C
Even after the integral clear gate signal (ICG) disappears, the switch transistor (Q4) (Q%) between
) is turned on, and each color temperature detection photodiode (
13) Accumulate the charge generated in (14) in each capacitor (C4) (cs). Then, from the generation of the instruction signal (V FLG), the storage section clear gate signal (S
After the generation of the barrier gate signal (BG), the color temperature detection gate signal (PDS) falls, turning off the transistors (Q4) (QS). As a result, each color temperature detection photodiode (13)
(14) The charge generated in the capacitor (C4) (
The integration operation at C5) is completed, and the potential at the time of completion is the color temperature detection output signal (OSR) until the start of the next integration.
OSY).

The above explanation is about the low-luminance integration mode when the subject is relatively bright, but the integration completion operation etc. are slightly different in the low-luminance integration mode when the subject is extremely dark. A time chart of each signal at this time is shown in FIG. 16(b). After starting the above-mentioned integration, the system controller (53)
While waiting for reception of the integration completion signal (TINT), the timer circuit (59) is used to measure the integration time. Then, if the integration continues even after 10100I have passed after the start of integration and the integration completion signal (TINT) is not received, the system controller (S3) sends a shift pulse generation signal to force the photoelectric conversion element (12) to complete the integration. (S
HM). This shift pulse generation signal (SKIM
), the integration time control circuit (17b) of the photoelectric conversion element (12) supplies the above-mentioned storage section clear gate signal (STICG) to the photoelectric conversion section (15) to clear the storage section (2).
3) After discharging unnecessary charges, the barrier gate signal (BG
) to transfer the accumulated charge of the pixel photodiode (PD) to the accumulation section (23). This completes the integration. The reason why the signal (ST) is not set to low level to raise the potential level of the storage section at this time is because there is almost no storage time in this storage section. The charges in each accumulation section (23) are subsequently shifted to the shift register (26) by a shift pulse (SH) given from the transfer lock generation section (16A), and then transferred to the transfer lock (φ1) ( φ2) is sequentially transferred to the capacitor (C2) side. In this way, when the integration is forced to complete based on a command from the system controller, the charge is not accumulated to the appropriate integration level, so the output level is small, which may cause a decrease in the S/N ratio or cause the system The dynamic range of the A/DC 8 section (54) of the controller (53) may become inappropriate. Therefore, in such a case, it is desirable to perform gain correction in the analog processing section (18).

The brightness determination circuit (17a) described earlier in FIG. 15 determines the amount of gain correction, and the output path (72 ) (7
3) Either (74) or (75) is selected (set to high level), and the selected state is maintained until the next integration is completed and the monitor output signal is processed.

This concludes the explanation of the integration operation in the low-brightness integration mode. However, if integration is started in the low-brightness integration mode and the integration completion signal (TINT) is detected before 1ms, there will be many excessive integral components in the low-brightness integration mode. Therefore, the system controller (53) switches the mode signal (MD I ) (Mow) to the high-luminance integration mode because the analog processing and A/D conversion processing of the pixel output signal become saturated.

Next, the integration operation in this high brightness integration mode is shown in Figure 17 (
This will be explained with reference to the time chart of a).

First, the system controller (53) generates an integral clear signal (ICS) as in the low brightness integral mode.

This pulse width is chosen to be the same as in the low brightness integration mode.

Upon receiving this integral clear signal (IC5), the integral time control circuit (17b) initializes the photoelectric conversion section (15).

Integral clear gate signal (ICG), storage section clear gate signal (STICG), barrier gate signal (BG)
occurs. Next, as the integral clear signal (ICS) disappears, integration is started in the same way as in the low-luminance integration mode, but since this time it is high-luminance integration, the barrier gate signal (BG ) is the integration time control circuit (17b) as a high level signal from the start to the end of integration.
It is output from. This means that the pixel photodiode (
Integration is performed with the barrier gate (22) between the storage section (PD) and the storage section (23) turned on, and the storage section (23) is connected from the beginning.
) means that the charge generated in the pixel photodiode is accumulated. Note that during this integration, the storage section clear gate (2
4) is turned off. Integration starts in this way, and the monitor output signal (AGCOS) changes to the monitor output compensation signal (AGCD) corresponding to its initial potential, as in the low-luminance integration mode.
A predetermined amount Vth (= I x 8R) from the level of OS)
At the point when the brightness has decreased by
supplied to The integral time control circuit (17b) receives this instruction signal (VFLG) and outputs a barrier gate signal (BG).
is set to a low level, and the barrier gate (22), which had been on until that point, is turned off. This stops the charge flow from the pixel photodiode (PD) to the storage section (23) and also stops the charge flow from the pixel photodiode (PD) to the storage section (23).
3) Sends an integration completion signal (TINT) to In this way, in the high-brightness integration mode, there is no need to transfer charge from the pixel photodiode (PD) to the storage section (23), which was seen in the low-brightness integration mode, but simply by transferring the charge from the barrier gate (22).
Since the integration completion operation can be completed simply by switching from the on state to the off state, it is possible to eliminate the delay in the completion of integration with respect to the instruction signal (VFIJ) as shown in FIG. 17(a). On the other hand, in the low-luminance integration mode, there is a time delay (t) of 50 to 100 μs as described above.
[See FIG. 16(a)] occurs. When the barrier gate (22) is turned off, the signal (ST) is set to a low level to raise the potential of the storage section and reduce the generation of dark charges. The storage part (23) where the potential has become high in this way
The charge integrated to the appropriate integration level stored in the system controller (53) is stored in
The signals are sequentially shifted to the shift register (26) under the control of the transfer lock generation section (16A) which inputs the shift pulse generation signal (SHM) from and forms the shift pulse (SH) and transfer locks (φ1) (φ2). It is transferred to the output capacitor (C+) of the shift register (26). The signal (ST) becomes high level in synchronization with the disappearance of the shift pulse (SH), thereby returning the charge in the storage section to its original state. In addition, the color temperature detection photodiode (13)
The color temperature detection gate signal (PDS) that controls the integration of the output in (14) is output here as a signal with the same value as the barrier gate signal (BG), and falls at the falling edge of the barrier gate signal (BG), and is output to the pixel photodiode. Color temperature detection output signal (OSR) at the time of completion of integration of (PD) (O5Y)
hold the output of .

Incidentally, a case where the brightness of the subject is extremely low in the high brightness integration mode is shown in the time chart of FIG. 17(b). In this case, since the integration completion signal is not generated within the predetermined time measured by the timer circuit of the system controller (53), the system controller side (TIN
(SH old occurs before T) is received, and the integral operation is completed. The operation for completing the integral operation is the same as that in FIG. 17(a).

In the above, the integration operation of the photoelectric conversion unit (15) has been explained in the low-intensity integration mode and in the high-intensity integration mode. Gate (22), storage section (23), shift gate (25), shift register (
26) schematically shows the physical operation.

Also, in these figures, the pixel photodiode (PD)
Other parts are indicated by symbols of applied signals. Furthermore, (OG
) shows an outgate attached to the end of the pixel photodiode (PD), and if necessary, for example, as shown in FIGS. This out gate (O
G) can discharge unnecessary charges.゛First
FIG. 9 shows the low-brightness integration mode, and FIG. 20 shows the high-brightness integration mode.

In FIG. 19, (a) is during integration. (b) shows an operation in which the charge in the storage section (23) is discharged to the power supply (Vcc) through the storage section clear gate (24) before transferring the charge in the pixel photodiode (PD) as the integration completion operation (i). There is. (C) shows the operation of transferring the charge of the pixel photodiode to the storage section (23) as the integration completion operation (ii). (d) shows the state at the time of completion of the integration, where the potential control signal of the storage section ( ST) is changed from high level to low level to raise the potential level of the storage part.
This is due to the following reason: When the charge from the 0 pixel photodiode (PD) is held, the storage section (23) has a deep potential, so dark charge is likely to occur in the storage section itself, and the amount of stored charge changes. Therefore, by making the potential shallow, the generation of dark charges in the storage section itself is suppressed. Regarding this point, the same applies to the high brightness integration mode shown in FIG. 20. FIG. 19(e) shows the initialization, that is, the clearing operation of the integral.

In high-intensity integration mode, Fig. 20(a) shows that during integration, (
b) shows the completion of integration, and (c) shows charge transfer to the shift register. Even in this case, the integration clearing operation is performed as shown in FIG. 19(e).

Next, regarding the analog processing section (18) shown in FIG.
This will be explained with reference to the time charts of FIGS. 16 to 18. As shown in FIG. 7, the first to fifth segments from the right of the shift register (26) do not have corresponding pixel photodiodes, so the buffer (27)
The first five of the pixel output signals (O5) output through are the outputs of the register segment without photodiodes, followed by the outputs of the shaded pixel photodiodes (OPD) from the 6th to the 10th, and then , the output of the pixel photodiode in the reference part (M.), the unnecessary part (
The output of the register segment corresponding to S), the reference part (
1 photodiode, and finally the output of the light-shielded pixel photodiode (OPD) on the left side. The output waveform is shown in Figure 18 (O5
).

The pixel output signal (O8) is initialized by resetting the capacitor (C+) in FIG.

At that time, a reset pulse (OSRST) is applied to the gate of the transistor (Q, ) to make the transistor (Ql) conductive and charge the capacitor (C1) to the power supply voltage (Vcc). When applied, a signal induced by the clock field-through effect of the MOS transistor (Q,) is generated, and when this reset pulse (OSRST) ends, the capacitor (Cυ) is charged to approximately the power supply voltage and returns to the original reference level. However, this reference level is the reset pulse (
Varies depending on power supply voltage fluctuations when applying OSRST). Next, at the falling edge of the transfer lock (φ,), the shift register (
26) transfers one phase, and the accumulated charge of the next pixel photodiode flows into the capacitor (C1) and is output. The amount of voltage drop at this time is the pixel output signal V os (n) that is proportional to the amount of light incident on the pixel photodiode.

Next, another reset pulse (OSRST) is applied to the transistor (Ql) to reset the capacitor (C3), and at the next transfer lock (φ,), the pixel output signal V os (n + 1) of the next pixel photodiode is ) is obtained. Pixel output signals are sequentially output in this manner.

The series of pixel output signals output in this way is sampled and held at the timing of (RSS/H) in FIG. Subtraction circuit (67)
By taking this value, the reset level of the differential output (OSdir) is adjusted to a constant value, and the voltage drop from that level becomes the value of the pixel output signal. This power supply noise removal ability is generally called a double sampling method.

Next, using the differential output (OSdir) obtained in this way, a second sample and hold circuit (not shown) provided in the same subtraction circuit (67) performs sample and hold. This is to ensure time for keeping the input analog amount constant for the A/D converter (54) in (53). The subtraction circuit (67)
The pixel output signal sampled and held in Figure 18 (7
) From (VosS/H), the difference is Vos(n),
Vos(n+1) and Vos(n+2) become the lower value signals.

Among the pixel output signals (Vos) processed in this way, the seventh to ninth dark pixel output signals are sampled and held in the next third sample and hold circuit (70). The sampling pulse (OBS/H) at this time is the first
As shown in FIG. 6, the pulse is such that the output signal of the light-shielded pixel photodiode (OPD) that is shielded by the seventh to ninth aluminum films of the pixel output signal (Vos) is extracted. Note that the sixth signal is not sampled and therefore is not used for the following reason. That is, as shown in FIG. 7, the sixth pixel output signal is located at the end of the light-shielded pixel photodiode (OPD), so it is easily affected by external noise, and therefore its output This is because this does not necessarily result in accurate dark pixel output. Said (OBS/
The 7th to 9th dark pixel outputs sampled by H) are processed at least until the output of a series of pixel photodiodes ends (12 in the shift register segment).
(until the eighth output is processed).

In this way, the sample-held dark pixel output (■
. , ) and the pixel output signal (Vos) output from the 11th and subsequent stages is taken by the AGC subtraction circuit (71) in the next stage, so that the pixel output is based only on the photocharge output with the dark output removed. A signal (Vos) can be obtained. This subtraction is performed by the AGC subtraction circuit (71) shown in FIG.
It will be held in In Figure 15, (A,) is the terminal (7
7) and the dark pixel output (Vow) input from the terminal (7).
This is an operational amplifier that takes a differential with the pixel output signal (Vos) input from 6). In addition, a resistor (
r, ) (r-) (r3) (r4) and the reference voltage (
The resistor (rs) (ra) (r, t) (re) connected between the positive input terminal (+) and the positive input terminal (+) is connected to the analog switch (S, ) by the aforementioned gain control signal (AGC).
~(S, ) to compensate for the lack of gain in the image output signal due to the forced stop of integration during low brightness. The signal passing through this AGC subtraction circuit (71) is output from the photoelectric conversion element (12) to the system controller (53). Therefore, the output level is adjusted to the dynamic range (1/3 V ref ≦ I) R ≦ V ref) of the A/D converter (54) in the system controller (53), and the dark pixel output is set as (V ref). ,
The AGC subtraction circuit (71) is configured so that when the pixel output (Vos) increases, it can take an output form of Vref-Vos. That is, when a pixel output voltage (Vos) equal to the dark output voltage (V on ) input to the terminal (77) is input to the terminal (76), the output of the operational amplifier (A, ) is Vref. Then, the input (V.

When S) becomes lower than (■.,), the operational amplifier (A,
) output becomes Vref-Vos.

On the other hand, the color temperature detection output signal (OSR) (OSY) is differentiated from the color temperature detection compensation signal (PDDO3) which acts as a reference voltage output in the second and third subtraction circuits (68) and (69).

Furthermore, the above-mentioned AGC is used to compensate the differential output in the dark, to make it an appropriate gain, and to adjust it to the reference voltage.
The subtraction circuit (71) is supplied with the subtraction circuit (71). At this time, the timing of supply to the AGC subtraction circuit (71) is determined by the timing of supply to the subtraction circuit (67) (6
8) Analog switch (AND) following (69)
(aNt) (aNs), the control signal (ANS+) (ANSz) (8N5) shown in FIGS. 16 and 17 is given from the signal processing timing generator (16B)
3).

As a result, in this embodiment, as shown in the pixel output signal (Vos) in FIGS. 16 and 17, during the output of the 10th pixel output signal immediately after the sampling of the dark output, the The yellow temperature detection signal (OSY) is
During the output of the 11th pixel output signal, the red temperature detection signal (OSR) is sent to the AGC subtraction circuit (7
1). In addition, the color temperature detection signal (O3I?)
Instead of outputting (OSY) using a separate output buffer in the photoelectric conversion unit (15), a light-shielded pixel photodiode (OPD) is used as shown in Fig. 13 to generate the same signal as a normal pixel output signal. In the case of outputting through the path, the buffer (27) outputs the signals as the 10th and 12727th elementary output signals. Therefore, these outputs are subjected to the aforementioned double sampling to remove noise components,
After the dark time output is compensated by taking the difference from the dark time output sampling value, it is supplied to the Accl calculating circuit (71). In this case, the second, i-th subtraction circuit (68) (6
9) and analog switch (AND) (ANt) (A
N3) becomes unnecessary.

This concludes the explanation of the analog processing section (18), and next the temperature detection section (19) will be explained. Among the autofocus detection mechanisms shown in Fig. 2, for example, the lens holder (9)
acrylic material part and re-imaging lens (4a) (4b)
The substrate (5) etc. that hold the holder expand depending on the temperature, causing slight changes in the dimensions of a predetermined portion.

This causes autofocus errors due to temperature.

From this point of view, a temperature detection section (19) is provided to electrically perform temperature compensation;
), as shown in Figure 21, a resistor (R1) (Rz) is connected in series between the reference voltage (V ref), which has a predetermined potential lower than the power supply (Vcc), and the ground, and the midpoint of the connection is connected to the operational amplifier. Connected to the positive input terminal (+) of (A,). Connect the negative input terminal (-) and output terminal directly. Here, resistance (Rυ is temperature coefficient βRI = 5000pp
m ion-implanted resistance, (R2) is the temperature coefficient βR2=
It is a polysilicon resistor of 500 ppa+, and the resistance value at 25°C is both (R1) and (Ih) 10 KΩ. FIG. 22 shows the output characteristics of the temperature detection section when the power supply voltage Vcc=13V and the reference voltage Vref=5V in FIG. 21. The detection output is expressed by the voltage across the resistor (R+).

In the time charts of FIGS. 16 and 17, AG
The pixel output signal (Vo
s), up to the 9th output are photoelectric conversion elements (12
) is not necessary to be supplied to the system controller (53) as an output signal.The signal to be supplied to the system controller (53) is from the red temperature detection signal (OSR) located at the 10th position. Therefore, up to the ninth pixel output signal, the temperature detection signal (Vt□) is supplied to the system controller (53) through the same output line. For this reason, analog switches (ANA) (AN,) are provided in front of the connection point (a) between the AGC subtraction circuit (71) and the temperature detection circuit (19), and these analog switches (ANa) (ANs) The gate signal (ANSa) shown in FIG. 16 (and FIG. 17) is generated from the signal processing timing generator (20a) at
(ANSs) is provided.

Next, the specific configuration of the transfer lock generating section (16) will be explained in the second section.
This is shown in FIG. 6(a) and FIG. 26(b). Of these, the 26th
Figure (a) shows the part that forms the shift pulse (SH), and Figure 26 (b) shows the transfer lock (φ, ) (φ2), (O3RST) (R3S/■) (O3S/H)
In FIG. 26(a), which shows the part that generates the clock signal (ADT), etc., (16a) is the first frequency divider that divides the basic clock (cp) from the system controller (53); Output is (SHM) (ICG) (TINT)
The second pulse is reset by the output of the shift pulse forming section (16b) which forms the shift pulse (SH) according to the logic of
The frequency is divided by the frequency divider (16c), ([100) (QDI
) (QD2) is generated. These outputs are shown in Figure 26 (b
) is decoded by the decoder unit (16d) of the decoder unit (
(φ1) (φz) (
O5RST) etc. are created.

FIG. 27 shows a specific example of the signal processing timing generation section (20a), which inputs (φt) (SH) (IC5) and generates (ANS r ) ~ (ANSs) and (085
/H) Generates (ADT). (AnT) is a control signal that triggers A/D conversion of the system controller (53).

Next, the system controller (53) will be explained.
A/D converter (54) in the system controller (53)
) is formed as shown in Fig. 23, and the terminal (78
) is the pixel output signal (
Vout) is input, and the reference voltage (Vr
ef), (ADT) is input to the terminal (80). Then, the A/D conversion output is derived from the terminals (0+) (0□)... (On).

The system controller (53) thus performs the A/D i
The color temperature of the subject is detected by calculating the ratio R of the digital values (Vasll) (Vosy) of the converted color temperature detection signal (OSR) (O5Y), and correction is performed according to the color temperature. , the flowchart is shown in the second
4, FIG. 24 shows the overall flow of the focus detection operation, and FIGS. 25 (a), (b), (c), and (d) show the flow of color temperature correction in particular.

First, an outline of the focus detection operation will be explained using FIG. 24. When the focus detection operation is started by pressing the shutter button on the camera, the system controller (53) resets the flag and inputs lens data including color temperature correction data from the lens data output section (61). The system controller (53) sets an integration mode (ST) in which the storage unit performs storage (signal MDI = low level, Mn2 - high level), and sets the maximum integration time to 20a+sec. Then, an integration clear signal (IC5) is generated to start integration. At this time, the integration of the color temperature detection photodiodes (13) and (14) is also performed at the same time. Then, it waits for the integration end signal (TINT) indicating the end of integration to become low level, and when it becomes low level, it is determined that the integration has ended, and the time required for this is determined. If the time is within 1m5ec, the high-speed flub ()ILP) is set to set the next integration mode to the mode (ST mode) that performs integration into the storage section, and the time is 1t.
sec~20m5ec, the next integration mode will be the same as this time, and the integration end signal (T
If INT) does not go to low level, the next integration mode is set to a mode that performs integration to the light receiving section (PD mode) and the low luminance flag (LLF) is set.In either case, the integration completion operation is performed. (Signal (SHM)
output and wait for the integration end signal (T I NT) to go low level.
Only when the integration is not completed within 9 seconds, it is waited for the integration end signal to become low level; otherwise, it is already low level. Note that pixel data is sent to the shift register by a shift pulse in terms of hardware. If the integration end signal (TINT) is at the low level, the system controller (53) sets the data input mode and inputs the AGC data of the digital signal. Next, temperature data is input, but ^/D conversion for this analog data is started by the pulse of the signal (ADT), and we wait for this A/D conversion to finish.
When the /D conversion is completed, temperature data (SBT) is input and stored in a predetermined register. As described above, this temperature data input is at the timing of the ninth data input of the shift register (26) (see the time chart) (no data is input to the shift register).

Next, the system controller (53) sets the number of pixels of the captured data including the number of color temperature detection photodiodes and the number of pixel output signals, and sets the input analog signal (Vo
Perform A/D conversion of s), store data in the internal memory every time an interrupt signal occurs due to the completion of this, and repeat this for the number set above. In this way, the memory (
55) The reference section side stored within. ) as well as the reference part (Ml
) The digital signals corresponding to each image of
The defocus df is calculated by determining the image interval between the two parts (M.) and (Ml) using a correlation calculation as disclosed by the applicant in No. 0-247211. After calculating df by distance measurement calculation, temperature correction is also performed based on the output from the temperature detection section (19). Therefore, β is the temperature correction coefficient of the camera itself, SBT is the temperature information, and 5BT6 is 25°
This is basic temperature information when C. The temperature-corrected defocus dfo is set to take the true value when the light source of the subject is sunlight.

This defocus amount df is a predetermined value Tdf (=2 to 3
m), the color temperature correction value is not that large (approximately 100 to 200μ or less), so the correction value itself does not have a large effect, and the lens is driven and remeasured. When defocus is detected below a predetermined value Tdf, the color temperature correction value Δd
f will be added. In this way, the color temperature correction value Δd
After f is added, focus is determined, and if it is within the focus range, an in-focus display is performed, and if it is determined that it is out of focus, the detection diagonal is added by adding the color temperature correction value Δdf to the defocus amount dfo. Lens driving is started in accordance with the focus ldf, and after setting the integration mode, the routine from the step of starting integration by IC3 generation is repeated.

Here, we will add an explanation of the internal operation of color temperature correction.

As mentioned earlier, the lens color temperature correction data dFL is input at the top of the flowchart.

This value is, for example, the amount of chromatic aberration of each lens with respect to 550 nm (daylight) when an 800 nm monochromatic light source is stored in the memory within the lens. On the other hand, the output signal (O5R) of the color temperature detection photodiode is integrally controlled simultaneously with each pixel photodiode and subjected to analog processing.
OSY) is digitized by the A/D converter (54) of the system controller (53) and (Vos*) (Vosv
) is stored in the memory (55). The system controller (53) calculates this ratio R of (Vos*) (Vosv) as shown in FIG. 25(a). When this ratio R is a predetermined value, for example 1.8 or more, it is determined that the incident light from the subject has many long wavelength components and has a low color temperature, and a predetermined coefficient k is added to dFL of the color temperature correction data.
Multiply (0≦ and 1≦1) to obtain the color temperature correction amount Δdf. Conversely, when the ratio R is 1.2 or less, it is determined that the incident light from the subject has many short wavelength components and the color temperature is low, and a predetermined coefficient -kt (2 for 0≦) is added to the color temperature correction data dFL.
≦1) and set the color temperature correction amount to Δdf. When the ratio R is between 1.2 and 1.8, the incident light from the subject is integrated by a light component close to daylight, and color temperature correction is not necessary, and the color temperature correction amount Δdf is
=O. The color temperature correction amount Δdf determined based on the light from the object is added to the defocus amount df obtained by the distance measurement calculation to calculate the true detected defocus amount df.

Color temperature correction is performed in this way, but another method is to include the necessity of color temperature correction as lens data depending on the type of lens, and perform color temperature correction as shown in the flowchart in FIG. 25(b). By first determining whether or not to perform color temperature correction, if color temperature correction is not necessary, speed can be increased without going through an extra flow. Also, instead of determining each correction value in terms of M numbers as in (a) and (b),
The second flow of determining the correction value continuously for the value of R is
As shown in Figure 5 (c), R may show infinity for a subject with a short single wavelength component, whereas in the case of chromatic aberration in an optical system, as long as it is visible light, chromatic aberration is naturally finite. value. To add restrictions for that, R
In the case of ≧2.5, the value of R is limited to 2.5, and the correction amount is determined based on the color temperature defocus correction amount of the lens mentioned above, a predetermined coefficient, and the ratio R at the reference daylight color. 1.
Determined by multiplying by the value subtracted by 5.

Next, when performing discretely as shown in FIG. 25(a),
If it is possible to set the value of the correction amount Δdf for each lens, the correction amount Δdf will be R≧1 as shown in FIG. 25(d).
．． When R≦1.2, the value df, . . . art is given to each lens, such as df8 when R≦1.2.

In any case, in the embodiments described above, the color temperature of long wavelength components and short wavelength components within visible light is detected and corrected, so that the accuracy of focus detection is improved.

Effects of the Invention According to the present invention, since an image sensing system is configured with two chips, the number of external connection lines connecting them to each other is reduced, and the line capacity is accordingly reduced, which does not lead to an increase in current consumption. This enables high-speed control. Furthermore, since the signal can be processed within the photoelectric conversion element and supplied to the outside (to the system controller) as a sufficient analog signal, external noise is also reduced. Furthermore, the present invention has the effect of improving productivity by reducing the number of connection points, making the present invention extremely useful.

[Brief explanation of the drawing]

All figures relate to the present invention, and FIG. 1 is a principle diagram of an optical system when the image sensing system of the present invention is used for focus detection of a camera. FIG. 2 is an exploded perspective view of the sensor module, and FIG. 3 is a schematic configuration diagram of the photoelectric conversion element. FIGS. 4 and 5 are characteristic diagrams for explaining the spectral sensitivity of the color temperature detection photodiode. FIG. 6 is a block circuit diagram of the photoelectric conversion element, and FIG. 7 is a diagram showing the circuit configuration of the photoelectric conversion section. FIG. 8 is an enlarged view of a part of FIG. 7, and FIG. 9 is a sectional view taken along the line AA' in FIG. FIG. 10 is a structural diagram showing the physical structure of a pixel photodiode. FIG. 11 is a diagram showing the structure of the output section of the shift register in FIG. 7 in comparison with a conventional example. 12th
The figure is a diagram showing a schematic shape of a photoelectric conversion unit viewed from the light incident direction. FIG. 13 is a diagram of another embodiment corresponding to FIG. 8. FIG. 14 is a block circuit diagram showing the overall configuration of the image sensing system, and FIG. 15 is a specific circuit diagram of a portion thereof. 16 and 17 are time charts of each partial signal of FIG. 14 in the low-luminance integration mode and the high-luminance integration mode, respectively. Figure 18 is the first
5 is a diagram of various signal waveforms for explaining the operation of the analog processing section in FIG. 4. FIG. FIGS. 19 and 20 are diagrams showing the physical operation of the photoelectric conversion section in the low-brightness integration mode and the high-brightness integration mode, respectively. FIG. 21 is a specific circuit diagram of the temperature detection section, and FIG. 22 is its output characteristic diagram. FIG. 23 is a circuit diagram of the A/D conversion section of the system controller. FIG. 24 is a flowchart showing the operation of the system controller, and FIG. 25 is a flowchart showing a portion thereof in detail. FIG. 26 is a specific circuit diagram of the transfer lock generation section, and FIG. 27 is a specific circuit diagram of the signal processing timing generation section. (12)...Photoelectric conversion element, (15)...Photoelectric conversion section, (16)...Data output control section, (16A)...
・Transfer lock generation unit, (16B)...Signal processing timing generation unit, (53)...System controller,
(54)...A/D lli exchange part.

Claims (1)

[Claims] (1) A photoelectric conversion element formed as one chip and A/D converter for analog output signals from the photoelectric conversion element
a system controller formed in one chip having a /D conversion function; further, the photoelectric conversion element includes a photoelectric conversion section; a control section that controls the photoelectric conversion section based on a control signal from the system controller; An image sensing system comprising an analog processing section that processes the output of the photoelectric conversion section into an analog signal.