JPS63288582A - Image sensor - Google Patents

Abstract

PURPOSE:To obtain the image signal of a high quality and a little noise by forming a circuit to remove the power source noise of the image signal and a circuit to remove a dark time noise. CONSTITUTION:In a first subtracting circuit 67, the reference voltages of each shift are uniformly made constant and the output signal of a shift resistor in a photoelectric converting part 15 is indicated by a difference from this reference voltage. In a second subtracting circuit 71, a noise base on a dark time electric charge is removed. Thus, the high grade image signal, in which the influence of a power source noise or the influence of the dark time electric charge are removed, can be obtained. Further, since a constitution to execute theses noise removings is wholly provided in one IC chip, it comes to be immune to a noise from an external part. Thus, the image signal of the high quality and a little noise can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image sensor used for autofocus, etc. in a camera.

Conventional distortion-type image sensors generally include a light receiving element that outputs an electrical signal according to the intensity of incident light, and a CCD register that receives the electrical signal from the light receiving element and sequentially outputs the electrical signal in accordance with a clock pulse. It has and,
The output of the shift register is once received by a capacitor and supplied to the subsequent circuit through this capacitor. At that time, the capacitor is connected to the power supply via a switching means such as a transistor, and this switching means is turned on once every time an electrical signal is shifted to reset the capacitor, and then the electrical signal from the shift register is connected to the capacitor. It is designed to be transferred.

On the other hand, when a light-receiving element starts its operation, it not only outputs an electric signal according to the intensity of incident light, but also has the property of generating an electric signal (dark charge) even when it is not exposed to light. Therefore, such dark charge that becomes noise must be removed, but U.S. Patent No. 4,293,877 provides a light-shielded light-receiving element in addition to the original light-receiving element for photoelectric conversion, and takes the difference in their outputs. It is disclosed that the dark output is compensated for by the following.

Problems to be Solved by the Invention However, in reality, not only the dark-time noise mentioned in the above-mentioned US patent (but also power supply noise enters when resetting the capacitor following the shift register mentioned above, degrades the quality of the image signal. It has deteriorated.

In view of these points, it is an object of the present invention to provide an image sensor that can obtain high-quality image signals with less noise.

. In order to achieve the above-mentioned purpose of reading divination, the image sensor of the present invention has the following features:
a first light-receiving element that outputs an electrical signal according to the intensity of incident light; a second light-receiving element formed of the same material as the first light-receiving element and shielded from light; a shift register that outputs an eruption (in response to a clock signal); a capacitor connected to an output terminal of the shift register; a means for once coupling the capacitor to a power supply every time the electric signal is shifted to reset the capacitor; means for sampling and holding a reset voltage from the , a first subtracting means for taking a difference between the sampled and held voltage and an output signal from the capacitor based on the reset electrical signal, and an output of the first subtracting means. A structure in which a holding means for holding the output of the second light-receiving element and a second subtraction means for taking the difference between the output of the holding means and the output of the first light-receiving element are formed on the same IC chip. It has become.

According to this configuration, the reference voltage for each shift is made constant in the first subtraction circuit, and the output signal of the shift register is expressed by the difference from this reference voltage. Furthermore, the second subtraction circuit removes noise based on dark charges. In this way, it is possible to obtain a high-quality image signal from which the effects of power supply noise and dark charge are removed, but it is also difficult to provide all the components for removing these noises within one IC chip. , it also becomes resistant to noise intrusion from outside the IC chip.

Example The following example describes the entire image sensing system, which includes not only the image sensor but also the system controller (microcomputer) that digitally processes and calculates the output signal, in automatic focus detection for camera autofocus. The structure of the image sensor is also explained.

As shown in Fig. 1, the focus detection optical system (OF) that constitutes the focus detection device of the camera is an infrared light cutter that is provided behind the planned focal plane (F) behind the photographic lens (1). A filter (10), a condenser lens (2), a pair of re-imaging lenses (4a) (4b) with an aperture mask (3) located behind them, and these re-imaging lenses (
4a) A charge-coupled device (
A focus detection light receiving section (CCD) having a light receiving element (CCD) as a light receiving element.
It consists of the main parts (6), (7) of an AF (autofocus) photosensor array as a component of the RF).

When using a photo sensor array for AF that has a relatively flat spectral sensitivity within visible light (V), such as silicon, for example, the long wavelength component ( For example, λ=720na+) (
11) Since the imaging point of 11) moves to the rear of the intended focal plane (F) due to the axial chromatic aberration of the photographic lens (1), it generally corresponds to objects that contain many reflected light components. Image spacing (j!o > is visible light (V) [center of gravity (λ=
Image interval (fv) corresponding to a subject that contains a large amount of reflected light components (560 nm) (corresponding to the focal position detection signal)
Become bigger.

FIG. 2 shows the configuration of an AF sensor module (MP) that integrates the above-described focus detection device. This AF sensor module (MP) has a built-in optical path conversion mirror (8), and above this mirror (8) is the above-mentioned condenser lens (2), field mask (9), and 7501- or higher. Infrared light cut filter that cuts infrared light in the wavelength range (
10) are arranged.

Here, the infrared light cut filter (10) not only removes unnecessary infrared light to minimize the adverse effects of chromatic aberration, but also protects against long wavelength incident light, which is seen in semiconductor line sensors such as CCDs. This also prevents the reliability of the focusing signal from deteriorating due to an increase in the variation in photosensitivity of each pixel.

Each of these components is supported by a lens holder (11), and is arranged perpendicularly to the optical axis converted by the optical path conversion mirror (8), including an aperture mask (3) and a pair of re-imaging lenses. It has a basic structure in which a substrate (5) having (4a) and (4b) and a photoelectric conversion element (12) containing the aforementioned photosensor array are supported.

FIG. 3 shows the configuration of the photoelectric conversion element (12) of the AF sensor module (MF).

In the photoelectric conversion element (12), a focus detection light receiving part (R
F) for configuring the photo sensor array (in Fig. 3, the main parts (6) and (7) of the two photo sensor arrays shown in the principle diagram of Fig. 1 are shown as continuous). , a pair of color temperature detection photodiodes (13)
(14) are lined up almost parallel to each other. Then, the two re-imaging lenses (4a) and (4b) are used to detect the photo sensor array and color temperature detection photodiode (13).
) (14) A subject image is formed above.

Figure 4 shows the spectra of the photodiodes (PD'') that make up the color temperature detection photodiodes (13) and (14), and the dye filter placed above them, with wavelength on the horizontal axis and relative spectral sensitivity on the vertical axis. This shows the sensitivity characteristics.

Here, (13') is a yellow dye filter, (14'')
indicates the spectral sensitivity characteristic of the red dye filter. Therefore, the spectral sensitivity characteristic of the photodiodes (13) and (14) for color temperature detection is (13''> (1
4').

The color temperature detecting photodiodes view approximately the same subject through separate re-imaging lenses.

The graph in FIG. 5 is drawn together with the spectral energy distribution of light from various light sources. The horizontal axis is wavelength, and the vertical axis is relative spectral sensitivity or energy.

The curves (A), (B), and (C) in the figure are, respectively,
Light from standard light source A such as a tungsten lamp, sunlight,
It shows the spectral energy distribution of light from a white fluorescent lamp. In addition, (13"), (14') and (PD"
) is based on Figure 4.

In addition, in the figure, the two-dot chain line (IR) at the position of 750rv is
The cut wavelength by the infrared light cut filter (10) described above is shown.

As will be described later, based on the output currents from the color temperature detection photodiodes (13) and (14), which are the pair of light receiving sections for color temperature correction, specifically, based on the ratio, the focus detection It is designed to detect the spectral energy distribution of the measurement light.

That is, as can be seen from the graph, the difference in output from both photodiodes (13) and (14) is significant.
Since the area is about 600 nm or more, if the area of both is designed to be 1=1, the output from both photodiodes (13) and (14) will be almost the same for light from a white fluorescent lamp, and the ratio will be approximately It is 1.0. Furthermore, under the standard light sA, the light energy becomes significant at wavelengths above 600 nm, so the ratio of the outputs from both photodiodes (13) and (14) is large, and is about 2.0. Furthermore, the distribution of light energy in the infrared light region of sunlight is approximately between the light from a white fluorescent lamp and the light from standard light source A, and the output from both photodiodes (13) (14) The ratio is approximately 1.5.

Further, a first color temperature detection photodiode (13),
The second color temperature detection photodiode (14) is provided on the same chip adjacent to a reference part and a reference part of the photodiode array part, which will be described later. There is.

Next, the structure of the charging conversion element will be explained using FIGS. 6 to 13. First, as shown in FIG. 6, the photoelectric conversion element (12) includes a photoelectric conversion section (15) having a photodiode, a shift register, etc. that generates a photocharge according to the amount of irradiated light, and a photoelectric conversion section (15) that has a photoelectric conversion element (15) that generates photocharges according to the amount of light irradiated. A data output control unit (16) that controls charge transfer to the register side, control of charge transfer in the shift register, and signal processing timing of the analog processing unit (described later), integration time of the photoelectric conversion unit (15), etc. an analog processing section (18) that processes analog signals from the photoelectric conversion section (15), and a temperature control section (18) that processes analog signals from the photoelectric conversion section (15); Detection section (19) and I10 control section (2
0). And this charging conversion element (
12) is formed as a one-chip IC with each of the above-mentioned components provided on one substrate.

The photoelectric conversion section (15) includes the aforementioned pair of color temperature detection photodiodes (13) (14), a photodiode array section (21), a photodiode array section (22), an accumulation section (23) for temporarily storing charge, Accumulation section clear gate (24)
, a shift gate (25), and a shift register (26), and each output buffer thereof, that is, an output buffer (27) of the shift register (26), and a photodiode array as described later. Output buffer (28) for monitor photodiode (MPD) inserted inside, output buffer (29) (30) for color temperature detection photodiode (13) (14)
), a monitor output compensation signal output buffer (31) for dark-time correction of the monitor photodiode (MPD) output, and a color temperature detection signal (OSY) (OSR
) is provided with a reference voltage buffer (31').

Furthermore, color temperature detection photodiodes (13) (14)
and the buffer (29) (30), and between the monitor photodiode (MPD) and the buffer (28),
Furthermore, capacitors and switching transistors are provided in the preceding stages of the buffers (31) and (31'), respectively, and the details of these capacitors and transistors will be explained in detail with respect to the specific circuit configuration of the photoelectric conversion section (15) shown in FIG. I will add this in the explanation. Data output control section (
16) is composed of a signal processing timing generation section and a transfer lock generation section, and generates a transfer lock (φI
) (φ2) and also generates a shift gate pulse (SH) to the shift gate (25). It also provides the analog processing section (18) with a signal useful for creating a timing signal for switching the sampling signal and the signal output from the charge conversion element (12) to the outside.

The integration time control section (17) monitors the signal (AGCOS) given from the monitoring photodiode (MPD) of the photoelectric conversion section (15) through the buffer (28), and controls the barrier gate (22) and the accumulation according to the monitoring result. (23) and the storage section clear gate (24), respectively, to control the integration time by appropriately outputting control signals (BG) (ST) (STICG). 17) is the monitor signal (8GCO
5) is compensated for in the dark using the monitor output compensation signal (AGCooS) given from the buffer (31). The integral time control section (17) also communicates signals with the system controller via the I10 control section (20), among which an integral completion signal (TIN?) is given to the system controller. . Furthermore, this integral time control section (17) sends a command signal (S
IN), the integration is forcibly completed, but in order to correct the insufficient integration output that accompanies this at the analog processing stage, an automatic gain control signal (AGC) is generated according to the integral value and the analog processing unit The basic functions of the analog processing section (18) are the signal (O3) from the shift register (26) and the output signal (OSY) from the color temperature detection photodiodes (13) and (14).
) It performs various analog processing such as removing noise components from (OSR), dark output signal compensation, and automatic gain control. As will be described in detail later, this analog processing section (18) sends the output signal to A of the system controller.
It also includes a configuration for performing reference voltage clamping to match the dynamic range of the /D conversion section.

The I10 control section (20) includes a signal processing timing generation section (16B) and an integral time control circuit (16B) shown in FIG.
17b), which refers to the human output buffers distributed in the transfer lock generation unit (16A),
10 The external device connected to the control section (20) is connected to the terminal (T
, ) ~ (T, ) and (Tit) (Tit), (T
I) (To is a mode signal (
(T3) is the input terminal for receiving the integral clear signal (ICS) related to the start of integration, (
T4) forcibly ends the integration and transfers the shift register (2
6) a data request terminal for requesting data from (
Ts) is a terminal that outputs an A/D conversion start signal (ADT) to the outside (system controller) in the data dump mode, and (T,) is an input terminal for a basic clock (CP). Furthermore, (T,) is a terminal that outputs an integration completion signal (TINT), and (Tit) is a terminal that outputs data for automatic gain control (A
This is a group of terminals that output GC). In addition, a terminal (T
? ) (Tll) are the input terminal for the power supply (Vcc) and the ground terminal, respectively. Further, (T,) is an analog signal output terminal, and (it.) is an input terminal for a reference voltage (Vref).

Next, the specific configuration of each part of the photoelectric conversion element (12) will be described in detail. First, the entire photoelectric conversion section (15) is configured as shown in FIG. 7, and the portion including main elements such as photodiodes and shift registers will be explained using FIGS. 8 to 13. . As shown in FIG. 8, the photodiode array section (21) has a plurality of pixel photodiodes (PD) and monitor photodiodes (MPD) arranged therebetween, which are alternately arranged. One longitudinal end of each pixel photodiode is open, while the other end is coupled to the source of a first MO3 transistor (TR,) forming a barrier gate (22).

The drain of this MOS transistor (TRl) is coupled to the next stage storage section (23), and the gate is coupled to the barrier gate signal supply terminal (32). Accumulation section (23)
is shielded from light by an aluminum film and is not irradiated with light, but generates so-called dark charges. The output end of the storage section (23) is connected to a second MOS forming the storage section clear gate (24).
The source of the transistor (rpz) and the shift gate (
25) forming a third MOS) transistor (TR3)
), the drain of the second M05) transistor (TRz) is coupled to the power supply terminal (T?) to which electric current m (Vcc) is applied, and the gate is connected to the storage section clear gate signal supply terminal (33). It is connected to the. on the other hand,
The drain of the third M05) transistor (TR3) is coupled to the segment (26a) constituting the shift register (26), and the gate is coupled to the shift gate signal supply terminal (34).

The monitor photodiodes (MPDs) are connected to each other by photodiodes at the upper end of the figure, so the monitor output is the total output of the plurality of connected monitor photodiodes (MPDs).

By combining a plurality of monitoring photodiodes in this way, a subject brightness monitoring photodiode device having a wide field of view can be realized.

The physical structure of the photodiode array section (21) is schematically illustrated in FIG. 9, which shows a cross section taken along the line A-A' in FIG. and an n-type region (37) by implantation,
a channel stopper (38) made of Po applied to the upper n-type region (37) to separate the pixel photodiode (PD) and the monitor photodiode (MPD);
It consists of a P1 film (39) provided on the surface to suppress the dark output of each photodiode and suppress the surface depletion layer. A positive potential is applied to the substrate (35) from the outside, and a ground potential is applied to the intermediate P wall region (36). Note that the n-type region (37) is formed by phosphorus implantation, and the P-wall region (36) is formed by boron diffusion.

By the way, the charge accumulated in the pixel photodiode (PD) mentioned above is transferred to the accumulation section (22) through the barrier gate (22).
3) The time required to transfer the data to the pixel photodiode (
It is known that the length of PD) is approximately proportional to the square of 1). On the other hand, as a focus detection device, the total area of each pixel photodiode (PD) is increased by increasing the length ff1) so that it can operate even for subjects with considerably low brightness, and the amount of generated charge is increased. However, increasing the width of the pixel photodiode (two ports) is not preferable because it deteriorates the accuracy of the focus detection device. In order to satisfy these contradictory demands, the present inventors proposed the above-mentioned P
We considered changing the depth of the n-type cell (37) just below the membrane (39) along the longitudinal direction. That is, Fig. 10 (a
) is cross-sectionally taken in the direction shown by the dotted line (40), and the structure of the main part (portion close to the surface) is shown in the figure (c), which shows the structure of the main part (portion near the surface). Regarding the creation of the mold region, the n-fJ region (37a
) and the n fiI region (37b). By doing this, the pixel photodiode (PD)
The potential gradually decreases toward the barrier gate (22), making it easier for charges to move to the left (toward the barrier gate). This means that the pixel photodiode (PD)
This means that the time required to transfer the accumulated charge is reduced. Therefore, the pixel photodiode (PD
) by increasing the longitudinal length (f) of the τ photodiode, it is possible to solve the problem of increasing the amount of charge generated by the τ photodiode and quickly transferring the generated charge toward the storage section. Furthermore, the first
In figure 0, (41) (42) (43) (44
) are pariage) (22) and storage part (23), respectively.
), shift gate (25), and shift register (26), and aluminum material is usually used to form these electrodes. (45) is an insulating film formed of SiO□ or the like.

Next, the configuration of the entire charging conversion section will be explained with reference to FIG. 7.

The pixel photodiode (PD), monitor photodiode (MPD), and barrier gate (22
), a storage section (23), a storage section clear gate (24), a shift gate (25), and a shift register (26) are arranged in large numbers in the horizontal direction, for example, the number of segments of the shift register (26) is In other words, there are 128 of them. However, as seen at the right end of the array, the pixel photodiode (PD), monitor photodiode (MPD)
), the number of segments of the barrier gate (22), storage section (23), storage section clear gate (24), and shift gate (25) is 5 fewer than that of the shift register (26) on the right end side. , shift register (2G)
The number of segments is 5 more on the right end side, and this is due to the following reason.

A capacitor (C) receives the output of the shift register (26).
1) is formed integrally with the shift register (26), specifically, as shown in the conventional example of FIG. (4
7) is formed by the junction capacitance generated between However,
A distributed capacitance (C') also occurs between the light-shielding aluminum film (49) coated on the surface via the insulating film (48) and the n'61 region (46). This undesired distribution capacity (
As shown in FIG. 11(c), C') is connected in parallel to the original capacitor (C8) formed of a junction capacitance, increasing the output capacitance and resulting in a decrease in photosensitivity. Moreover, the light-shielding aluminum film (49) and n″
The distribution volume 1t (C'') generated between the regions 46) has many variations and causes variations in photosensitivity from product to product.
Undesirable. Therefore, as shown in FIG. 11(b), the aluminum film (49) located in the output stage portion is removed (50).
(C') is almost gone 1, and the output capacitor (C6
) is hardly affected and the photosensitivity increases. on the other hand,
The removed part is blocked by the field of view mask shown in Figure 2 (
9). That is, the junction capacitance portion as the capacitor (C1) is placed at a position away from the window of the visual field mask (9). This is due to the capacitor (C8) provided at the output stage of the shift register (26).
), and the aluminum film on the top of the capacitors (Cz) to CCh) provided in each output stage is also removed.

Figure 12 shows this configuration as a schematic shape of the photoelectric conversion section (15) seen from the field mask side, and (51) is connected to the photodiode array (21) and color temperature detection photodiodes (13) and (14). (52)
represents the projection of the window of the field mask (9), and the condensers (C,) to (Ch) are arranged at a position away from the projected image of the window, and therefore at a position not exposed to light. Here, the opening areas of the capacitors (C1) to (C,) are set equal to each other. With this configuration, the output voltages of the capacitors (C1) to (Ch) can be made equal for the same output from the light receiving elements of the same size. Among these capacitors (CI) to (C6), only the capacitor (C+) is located at a position further away from the shift register segment corresponding to the light receiving part, so a segment is required to connect them. The segments are the first to fifth segments shown in FIG. Therefore, these five segments merely function as photo-charge transfer paths. Since the capacitors (C2) to (C6) directly input the output of the light receiving section, there is no need for extra segments as mentioned above.The output of the shift register (26) is a transistor ( Transfer lock (φI) (φ2) when Ql) is off
is given to the capacitor (C+) by the buffer (
27).

In FIG. 7, of the pixel photodiodes (PD) and the monitor photodiodes (MPD), five on the right end and three on the left end are shielded from light by an aluminum film. These light-shielded photodiodes generate a dark charge that is used, for example, for dark correction of the output of the pixel photodiode. A part of the photodiode array (21) is assigned as a reference part (M.) and another part as a reference part (Ml).

For example, there are 40 reference parts (M.) and 5 reference parts (Ml).
Contains a combination of 0 pixel photodiodes and a monitor photodiode, but structurally the reference part (M.

) and the reference part (M, ), and they are distinguished by software processing in the system controller, which will be described later.

Regarding the unnecessary parts between the standard part (io) and the reference part (MO), only the shift register (26) is left, and other pixel photodiodes, monitor photodiodes, barrier gates, storage parts, and storage part clear gates are installed. , the shift gate has been deleted from the drawing.This deleted part is referred to as (S
), each segment (26a) of the shift register corresponding to the deleted portion (S) has a different pitch in order to reduce the number of transfer locks required to transfer all pixel outputs and shorten the total charge transfer time. It is formed to be larger than the pitch of the parts.

The monitor photodiode (MPD) is in the reference section (M.)
and the reference part (M,) are connected to each other so that only those located in the reference part (M,) are used, and those located in other parts are not used. As shown in the figure, the power terminals (T,
) to stabilize it. If it is electrically floating, it will receive induction from other pixel photodiodes or cause induction to other pixels, and eventually other pixels This is because it affects the photodiode. The output of the monitor photodiode is once given to a capacitor (Cg), held there, and output as a monitor signal (AGCOS) via a buffer (28). In order to remove power supply fluctuations and temperature-dependent components of this monitor signal (AGCOS), the output from the capacitor (C3) is initialized by a transistor (Q, ) having the same configuration as the initialization transistor (Q2) of the capacitor (C2). (8GCDO5) are prepared at the same time. This capacitor (C
5), a photodiode (DI) shielded from light by an aluminum film and having approximately the same size as the monitor photodiode (MPD) is connected as shown. The transistor (port 2) (Q3) is turned on simultaneously during the application period of the integral clear gate signal (ICG).

Next, a pair of color temperature detection photodiodes (13) (1
4) are respectively arranged in the standard part (M.) and the reference part (Ml) as shown in the figure, and these two photodiodes (
13) The output of (14) is the integral clear gate signal (IC
The capacitor (C4) (C%) is initialized by the transistor (Q&) (Q?) that is turned on by G), and the transistor (port 4) (Qs) is turned on by the color temperature detection gate signal (PDS), respectively. Output as yellow temperature detection signal (OSY) and red temperature detection signal (OSR). These color temperature detection photodiodes (13
) A color filter (not shown) is provided on the surface of (14). Here, the output buffer following the shift register (26), the output buffer for the red temperature detection signal, and the output buffer for the yellow temperature detection signal are formed identically, and
By setting the sizes of the pixel photodiode (PD) and the color temperature detection photodiodes (13) (14) to be approximately the same, the yellow temperature detection signal (OSY) and red temperature detection signal (OSR) can be output. The voltage is the reference part (M.),
It is output as the product of the average output of the pixel photodiode of the reference section (M,) and the transmittance of the color filter. Therefore,
This red temperature detection signal (OSR) and yellow temperature detection signal (
OSY) has approximately the same dynamic as the output voltage of the pixel photodiode (PD), and can be used as a processing circuit for the pixel signal (O5) by processing it in a time-division manner in a subsequent analog processing section. Furthermore, since the size of the color temperature detection photodiodes (13) and (14) is the same as the size of the light-shielded pixel photodiode (OPD), the difference between the output voltage of the light-shielded pixel photodiode (OPD) must be taken. It is also possible to compensate for dark output. In addition, FIG. 7 shows the color temperature detection signal (OSY
) (OSR) output to remove power supply noise etc.
A capacitor (C6) for generating PDDO5) and a switching transistor (Q@) are also provided.

In Fig. 7, color temperature detection photodiodes (13) (1
4) The output signal (OSY) (OSR) is connected to a separate transistor (gate a> (Qs), capacitor (Ca) (C
s), buffers (29), (30), etc., but it is also possible to take out using the output system of the pixel output (O3) without installing a separate output system like this. It is.

FIG. 13 shows an embodiment based on this viewpoint, in which any one of the three light-shielding pixel photodiodes (OPDs) arranged on the left side of FIG.
), and the output signal of the red temperature detection photodiode (14) is sent to the shift register (26) using the barrier gate, storage section, and shift gate sequentially coupled thereto. This output signal is transferred from the shift register (26) to the capacitor (CI
) and further output via a buffer (27). FIG. 13 shows the red temperature detection photodiode (14) corresponding to the reference part (Ml) as described above, and one end of the second light-shielded pixel photodiode (OPD) from the left end that is shielded with an aluminum film is connected to the other end. The reference part (M) is formed longer than the pixel photodiode and is connected to the output end of the red temperature detection photodiode (14).
The output end of the yellow temperature detecting photodiode (13) corresponding to the yellow temperature detecting photodiode (13) is similarly formed long and connected to any one of the five light-shielding pixel photodiodes (OPD) on the right end side in FIG.

Next, FIG. 14 shows the photoelectric conversion section (15) as one block, and also shows other parts of the photoelectric conversion element (12) in detail, and also shows the system controller (
53) and its peripheral circuits.

The system controller (53) is formed by a one-chip microcomputer, and includes the photoelectric conversion element (1).
An A/D converter (54) that converts the analog signal (Vout) from 2) into a digital signal, and a lens data output unit (61) that includes a ROM for the photographing lens (interchangeable lens).
, data such as the defocus amount, lens extension amount conversion coefficient (KL), color temperature defocus amount (dpi), etc., which are different for each lens, are input in advance, and digital data from the A/D converter (54) is input. Store them one by one,
A memory section (55) formed of a RAM, and a focus detection section (55) that detects a focus based on the output of the memory section (55).
56), a correction calculation unit (57) that calculates a correction amount from the detected focus data and lens data, etc., and a signal for driving the lens based on the correction amount to the lens drive circuit 1B (63). A lens drive control section (58) that transmits and receives data on the movement status of the lens from a motor encoder section (64), and a photoelectric conversion section (15).
) for monitoring whether the integral value reaches a predetermined value in a predetermined time, and a sensor control section (60) for transmitting and receiving signals to and from the charge conversion element (12). Note that (65) is a lens drive motor, and (62) is a display circuit controlled by a system controller (53). The photoelectric conversion element (12) and the system controller (53) are formed separately with one chip each, so that the image sensing system is composed of two chips in total.

The integral time control section (17) in FIG. 6 includes a brightness determination circuit and an integral time control circuit, and in FIG. 14, this brightness control circuit (17a) and the integral time control circuit (1
7b) is shown separately. Further, the signal processing timing generation section (16B) shown in FIG. 14 is included in the data output control section (16) shown in FIG.

The I10 control section (20) in FIG. 6 is distributed into the signal processing timing generation section (16B), the integral time control circuit (17b), and the transfer lock generation section (16A) in FIG. 14. The system controller (53) first provides a basic clock (CP) to the photoelectric conversion element (12). This basic tarok (CP) is the transfer lock generation part (
16A) and an integral time control circuit (17b), respectively. The system controller (53) also sends a mode signal (io+) (M
DZ). The mode signal is composed of 2 bits and can express four modes: initialization mode, low brightness integral mode, high brightness integral mode, and data dump mode of the charging conversion element (12), and is transmitted using two lines. be done.

In the initialization mode, the transfer lock generation section (1
6A) to the photoelectric conversion unit (15) is a transfer lock (φ1
) (φ2) is supplied at a high frequency, and the charge that was unnecessarily accumulated in the shift register (26) before the transfer lock is supplied is discharged to the capacitor (C1) on the output side of the shift register (26). The charge discharged to this capacitor (CI) is transferred to the reset signal (OS) as shown in Figure 7.
When turned on by RST), it is discharged to the power supply (Vcc).

In addition, in the initialization mode, the analog processing section (18
) are also initialized.

Next, the system controller (53) first instructs the low brightness integration mode and supplies an integral clear signal (ICS) shown in FIG. 16 to the integral time control circuit (17b). By inputting this integral clear signal (IC3), the integral time control circuit (17b) controls this integral clear signal (IC3).
5) Integral clear gate signal (ICG), barrier gate signal (BG), storage section clear gate signal (S
TICG) is generated and applied to a predetermined portion of the photoelectric conversion unit (15) shown in FIG. The integral clear gate signal (ICG) is the monitor output signal (AGCOS), the monitor output compensation signal (AGCDOS), the color temperature detection output signal (O3R) (OSY), and the color temperature detection compensation signal (PDD).
O5) are respectively initialized, while the barrier gate signal (
BG) and the storage section clear gate signal (STICG) initialize the pixel photodiode (PD) and the storage section (23).

When the integral clear signal (IC5) disappears, the integral clear gate signal (ICG), barrier gate signal (BG),
The storage section clear gate signal (STICG) also disappears. As a result, the transistor (Qi) ((b) is turned off,
The capacitor (CCt), which was initially charged to the power supply voltage (Vcc), starts to drop in voltage in proportion to the charge generated by the monitor photodiode (MPD), and the capacitor (C3)
The voltage drops slightly in response to a small amount of charge generated by the light-shielded photodiode (D+). In addition, since (PDS) is applied to the transistors (Qa) and (Qs), the capacitors (C4 and C5) are also connected to the color temperature detection photodiode (13) from the initial power supply voltage (Vcc).
(14) The voltage is lowered according to the amount of charge generated.
On the other hand, the barrier gate (22) and the storage section clear gate (24) are turned off, and as a result, the pixel photodiode (PD) starts generating and accumulating photocharges in response to the irradiation light, and the light-shielding photodiode (MPD) starts generating and accumulating photocharges. The dark output charge starts to accumulate. Furthermore, in the storage section (23),
Accumulates the dark output charge generated by itself.

As can be seen from FIG. 16(a), for the integral clear signal (IC5), the aforementioned (BG) (STICG)
(ICG) have the same pulse width. Therefore,(
The pulse width of IC5) is determined by the pulse width of the pixel photodiode (PD) to transfer all charges previously (that is, before initialization) M to the barrier gate (22), the storage section (23), and the storage section clear gate (24). ) through the power supply (Vcc)
It is limited by the time required to discharge the water to the Specifically, the pulse width is selected to be 50 μs to 100 E or more.

The integration operation of the photoelectric conversion unit (15) does not need to be performed forever; rather, it must be completed at some point, because once the integral value reaches a predetermined level, there is no need to continue integrating. Also, if it takes a long time for the integral value to reach a predetermined level, the time from pressing the shutter button to being able to release the camera will be significantly longer. This is because it is better to correct this at the signal processing stage.

The brightness determination circuit (17a) determines the integration state from the monitor output signal (AGCOS) of the monitor photodiode (MPD) and the monitor output correction signal (AGCDOS), and when it reaches a predetermined value, It generates an instruction signal (VFLG) and supplies it to the integration time control circuit (17b), and also outputs a gain control signal (AGC) corresponding to the shortfall in the integral value. Its gain control signal (
AGC) is supplied to an AGCl calculation circuit (71).

The GC subtraction circuit (71) receives the input pixel output signal (O
3) and the gain of the color temperature detection output signal (OSR) (O3Y). The AGC subtraction circuit (71) also has a function of performing dark output compensation of the pixel output signal (O3), as will be described later. AGC data is also supplied to the system controller (53). The system controller (53) determines whether or not to emit an auxiliary light (not shown) based on AGC data.
This is to enable judgment to be made. A specific configuration of the brightness determination circuit (17a) is shown in FIG. 15. 15th
In the figure, the block indicated by the dotted line (17a) is the luminance determination circuit, and the other dotted line blocks are the GC subtraction circuit (71).
), the brightness determination circuit (17a) passes the monitor output compensation signal (8GCDO5) through resistors (R) (2R) (su) (8R) whose resistance values are 1x, 2x, 4x, and 8x. It is applied to the plus input (+) of the operational amplifier (At) (A2) (^, ) (A4). At this time, each resistor has a constant current! Since a constant current (1) flows due to (B), the voltage drop due to the resistance is 1, 2, 4, and 8, respectively.
The relationship is doubled. The monitor output signal (AGCOS) is connected to the negative input terminal (-) of the operational amplifiers (A,) to (A4).
) is supplied, and the outputs are (AGCOS) and (AGCDO
A voltage difference S) occurs, but as shown in Figure 7, capacitors (C8) and (C2), transistors (Q, ) and (port 3), and buffers (28) and (31) are on the same chip. Since they are designed identically, both signals (AGCO
S) and (AGCDOS) are the integral clear gate signal (IC
G) Immediately after application, the potential is the same, and soon the monitor output signal (
AGCOS) decreases with the generation of photocharge in the monitor photodiode (MPD), while the monitor output compensation signal (AGCDOS) remains unchanged.
The initial potential of the monitor output signal is always maintained. Therefore, by taking the difference between these signals, it is possible to monitor the amount of accumulated charge (integral value). Moreover, by taking the difference between the two signals, fluctuations in the power supply voltage can be canceled.
Furthermore, if the dark output increases due to temperature rise, the light-shielding photodiode (0+) will respond to it, so the monitor output compensation signal (AGCDOS) will include the temperature fluctuation of the dark output. , the difference voltage between the two signals becomes a correct monitor information signal with temperature effects removed.When it is considered that the integral value at the 0 pixel photodiode (PD) has reached a predetermined value, the difference voltage between the two signals becomes the correct monitor information signal with temperature effects removed. Monitor output signal (AGCOS
) is lower than the initial potential by I×8R, so an instruction signal (VFLG) is generated from the operational amplifier (A4).The instruction signal (VFLG) is generated by the integral time control circuit (17b).
is supplied to The integration time control circuit (17b) receives an instruction signal (VFII) or a forced integration completion signal (SHM).
When it receives either of these, it causes the photoelectric conversion unit (15) to perform an integration completion operation, generates a latch signal (LCK), and sends this latch signal (LCK) to the luminance determination circuit (15).
The D flip-flops (FF, ) to (PF3), which are supplied to the clock terminals (CP) of the D flip-flops (FFI) to (Fh) of 17a), are connected to the operational amplifiers (
Since the data terminal (D) is connected to A, ) to (A, ), the latched state depends on the value of the monitor output signal (AGCOS).

The output end of each D flip-flop (FFI) (Fh) (Fh) is connected to an AND gate (Nt) (Nz) as shown, and as a result, the output path (72) ( 73) (74) (75) is 1x,
Gain control signals (AGC) corresponding to correction amounts of 2 times, 4 times, and 8 times are output. Incidentally, under the situation where the instruction signal (VFLG) is output within a predetermined time managed by the system controller (53), (
AGC) occurs on the output path (72).

However, within the predetermined time, the instruction signal (V, L,)
In a situation where no
One of (74) and (75) will be generated.

An explanation of the low luminance integration mode will be added using the time chart of FIG. 16(a). The integration operation starts in the photoelectric conversion section (15) from the moment the integration clear signal (ICS) disappears, and after a while, when the monitor output signal (AGCO5) drops to a level corresponding to a predetermined integral value, the instruction signal (
VFLG) is generated from the brightness determination circuit (17a). In response to this, the integration time control circuit (17b) generates a storage section clear gate signal (STICG) to open the storage section clear gate (24) and remove the small amount of dark charge that was unnecessarily accumulated in the storage section (23). It is discharged to the power supply (Vcc) side. Subsequently, the accumulation section clear gate (24) is closed by the disappearance of this accumulation section clear gate signal. After this, the integral time control circuit (17b) immediately outputs the barrier gate signal (BG).
is generated, the gate gate (22) is opened, and the charges stored in the pixel photodiodes (two ports) are transferred to the storage section (23). It takes approximately 50 to 50 minutes from the generation of the instruction signal (VFLG) until the transfer operation to the storage section (23) is completed.
A time (1) of lOOμs is required. After the charges accumulated in each pixel photodiode (PD) are transferred to the accumulation section (23) in this way, the integration time control circuit (17) is transferred to the accumulation section (23).
b) gives an integration completion signal (TINT) to the system controller (53). In this embodiment, (TINT)
The transition from high level to low level at represents the completion of the integration.

This integration completion signal (TINT5) is accepted as an interrupt signal in the system controller (53), and even while the system controller (53) is performing other processing, the processing is not important and therefore processing is performed with interrupts disabled. Unless otherwise, the integration completion signal (TINT) is recognized immediately.If another process is an interrupt prohibition process, the integration completion signal (TINT) is processed when that process is finished. Based on this integration completion signal (TINT), the system controller (53) sets the address etc. for storing image information data in the memory section (55), and then sets the address etc. of the photoelectric conversion element (12).
A shift pulse generation signal (SHM) is supplied to the transfer lock generation section (16A) inside. As a result, the transfer lock generation section (16A) generates a shift pulse (SH), and applies this shift pulse (SH) to the shift gate (25) of the photoelectric conversion section (15) to transfer the shift pulse (SH) to the storage section (23). Transferring the charges accumulated to the appropriate integration level to the shift register (26) is carried out. Thereafter, the system controller (53) immediately sends the mode signal (?ID
I) (Gives a data dump mode signal to the photoelectric conversion element (12) as MO operation, and sets the photoelectric conversion element (12) to data dump mode. In addition, in the above, the system controller (53) outputs the integration completion signal (TINT). )
Even if the completion of integration cannot be recognized due to the interrupt disabling process after receiving the IOMS, the photoelectric conversion unit (1
In 5), the pixel photodiode (PD) and storage section (23)
Since the period between 1
The charge accumulated in the pixel photodiode (PD) during the oIls period has no effect on the desired charge accumulated in the accumulation section (23), and the potential level of the accumulation section is raised during that 10m5 period. signal (ST)
) is set to a low level (details will be described later), the dark charge generated in the storage section (23) itself and added to the desired charge is extremely small and does not pose a problem. 16th
In Figure (a), the shift pulse generation signal (SHA) starts from the time when the integration completion signal (TINT) is inverted to low level.
and a shift pulse (SH) approximately synchronized with said (SHM).
There is a slight delay in the occurrence of the system controller (5
This indicates that the processing of the integration completion signal (TINT) in 3) is delayed.

The integration time control circuit (17b) receives a barrier gate signal (
The color temperature detection gate signal (P
DS) also occurs. This color temperature detection gate signal (PrJ
S) indicates that during the period corresponding to the integral clear gate signal (ICG), the color temperature detection photodiode (13)
(14) The unnecessary accumulated charge is removed from the capacitor (C
4) Color temperature detection photodiodes (13) (14) and capacitors (C4) (Cs)
5) The switching transistors (O4) (O5) between the transistors (O4) and (O5) are turned on, and even after the integral clear gate signal (ICG) disappears, the high level is maintained and the transistor CQa) (
Qs) is turned on, and charges generated in each color temperature detection photodiode (13) (14) are accumulated in each capacitor (C4) (C3). Then, from the generation of the instruction signal (VrtG), the storage unit clear gate signal (ST
After the generation of ICG), the color temperature detection gate signal (PDS) falls at the falling edge of the barrier gate signal (BG).
The transistor (Qa) (Qa) is turned off. As a result, each color temperature detection photodiode (13)
(14) Said capacitor (C4) of the charge generated in
The integration operation at (C8) is completed, and the potential at the time of completion is the color temperature detection output signal (O5R) until the start of the next integration.
(OSY).

The above explanation is for the low-luminance integration mode when the subject is relatively bright, but in the low-luminance integration mode when the subject is extremely dim, the integration completion operation etc. are slightly different. A time chart of each signal at this time is shown in FIG. 16(b). After starting the above-mentioned integration, the system controller (53)
While waiting for reception of the integration completion signal (TINT), the timer circuit (59) is used to measure the integration time. Then, the integration continues even after 100m5 has passed after the start of the integration,
If the integration completion signal (TINT) is not received, the system controller (53) sends a shift pulse generation signal (SI) to force the photoelectric conversion element (12) to complete the integration.
IM). This shift pulse generation signal (SIIM
), the integration time control circuit (17b) of the photoelectric conversion element (12) supplies the above-mentioned storage section clear gate signal (STICG) to the photoelectric conversion section (15) to clear the storage section (
After discharging the unnecessary charge of 23), the burr 7 gate signal (B
G) to transfer the accumulated charge of the pixel photodiode (PD) to the accumulation section (23). This completes the integration.

The reason why the signal (ST) is not set to low level in order to raise the potential level of the storage section at this time is because there is almost no storage time in this storage section. Each storage section (23)
Subsequently, the charge is shifted to the shift register (26) by the shift pulse (SH) given from the transfer lock generating section (16A), and the charge is sequentially transferred to the capacitor (26) by the transfer locks (φ1) (φt) sent subsequently. C+)
transferred to the side. In this way, when the integration is forced to complete based on a command from the system controller, the charge is not accumulated to the appropriate integration level, so the output level is small, which may cause a decrease in the S/N ratio or cause the system The dynamic range of the A/D converter (54) of the controller (53) may become inappropriate. Therefore, in such a case, it is desirable to perform gain correction in the analog processing section (18).

The brightness determination circuit (17a) previously described in FIG. 15 determines the amount of gain correction, and the output path (72 ) (7
3) Either (74) or (75) is selected (set to high level). The selected state is held until the next integration is completed and the monitor output signal is processed.

This concludes the explanation of the integration operation in the low-brightness integration mode, but if integration is started in the low-brightness integration mode and the integration completion signal (TINT) is detected before 1 ms, an excessive integral component will be generated in the low-brightness integration mode. The system controller (53) switches the mode signal (MD+) (MDz) to the high-luminance integration mode because the number of pixels increases and the analog processing and A/D conversion processing of the pixel output signal become saturated.

Next, the integration operation in this high brightness integration mode is shown in Figure 17 (
This will be explained with reference to the time chart of a).

First, the system controller (53) generates an integral clear signal (IC5) as in the low luminance integral mode.

This pulse width is chosen to be the same as in the low brightness integration mode.

In response to this integral clear signal (IC5), the integral time control circuit (17b) initializes the photoelectric conversion section (15) by sending an integral clear gate signal (ICG), an accumulation section clear gate signal (STICG) <barrier gate signal ( BG) is generated. Next, with the disappearance of the integral clear signal ('IC5), integration is started in the same way as in the low-luminance integration mode, but since this time it is high-luminance integration, the barrier gate signal ('IC5) is BG) is output from the integration time control circuit (17b) as a high-level signal from the start to the end of integration. 'This means that the pixel photodiode (P
Integration is performed with the barrier gate (22) between D) and the storage section (23) in the on state, and the storage section (23)
This means that the charge generated in the pixel photodiode is accumulated. Note that during this integration, the storage section clear gate (24
) is turned off. Integration starts in this way, and the monitor output signal (AGCO5) changes to the monitor output compensation signal (AGCDO) corresponding to its initial potential, as in the low-luminance integration mode.
5), an instruction signal (VrLa) is generated from the brightness determination circuit (17a) and supplied to the integration time control circuit (17b) at the time when the level has decreased by a predetermined value of 1Vth (=IX8R). The integral time control circuit (17b) receives this instruction signal (VFLG) and outputs a barrier gate signal (BG).
is set to a low level, and the barrier gate (22), which had been on until that point, is turned off. This stops the charge flow from the pixel photodiode (PD) to the storage section (23) and also stops the charge flow from the pixel photodiode (PD) to the storage section (23).
3) Sends an integration completion signal (TINT) to In this way, in the high-brightness integration mode, there is no need to transfer charge from the pixel photodiode (PD) to the storage section (23), which was seen in the low-brightness integration mode, but simply by transferring the charge from the barrier gate (22).
Since the integration completion operation can be completed simply by switching from the on state to the off state, the completion of integration in response to the instruction signal (VFI4) can be delayed as shown in FIG. 17(a). On the other hand, in the low-luminance integration mode, there is a time delay (t) of 50 to 100 μs as described above.
[See FIG. 16(a)] occurs. When the barrier gate (22) is turned off, the signal (ST) is set to a low level to raise the potential of the storage section and reduce the generation of dark charges. The storage part (23) where the potential has become high in this way
The charge integrated to the appropriate integration level stored in the system controller (53) is stored in
The signal is shifted to the shift register (26) under the control of the transfer lock generation unit (16A) which inputs the shift pulse generation signal (SHM) from and forms the transfer lock (φ, ) (φ1) with the shift pulse (SH). It is sequentially transferred to the output capacitor (C1) of the shift register (26). The signal (ST) becomes high level in synchronization with the disappearance of the shift pulse (SH), thereby returning the charge in the storage section to its original state. In addition, the color temperature detection photodiode (13)
The color temperature detection gate signal (PDS) that controls the integration of the output in (14) is output here as a signal with the same value as the barrier gate signal (BG), and falls at the falling edge of the barrier gate signal (BG), and is output to the pixel photodiode. Color temperature detection output signal (OSR) at the time of completion of integration of (PD) (OSY)
hold the output of .

Incidentally, a case where the brightness of the subject is extremely low in the high brightness integration mode is shown in the time chart of FIG. 17(b). In this case, since the integration completion signal is not generated within the predetermined time measured by the timer circuit of the system controller (53), the system controller side (TfN
(SHM) occurs before the reception of T), completing the integration operation. The operation for completing the integral operation is the same as that shown in FIG. 17(a).

In the above, the integration operation of the photoelectric conversion unit (15) has been explained in the low-intensity integration mode and the high-intensity integration mode, respectively. The physical operations of the gate (22), storage section (23), shift gate (25), and shift register (26) are schematically shown.

Also, in these figures, the pixel photodiode (PD)
Other parts are indicated by symbols of applied signals. Furthermore, (OG
) shows an outgate attached to the end of the pixel photodiode (PD), and if necessary, for example, as shown in FIGS. This out gate (O
G) can discharge unnecessary charges. 19th
The figure shows the low-brightness integration mode, and FIG. 20 shows the high-brightness integration mode.

In FIG. 19, (a) is during integration. (b) shows the integration completion operation (1) in which the charge in the storage section (23) is transferred to the storage section clear gate before the charge of the pixel photodiode (PD) is transferred.
) (24) to the power supply (Vcc). (C) shows the operation of transferring the charge of the pixel photodiode to the storage section (23) as the integration completion operation (ii). (d) shows the state at the time of completion of the integration, where the potential control signal of the storage section ( ST) is changed from a high level to a low level to raise the potential level of the storage section, and this is for the following reason. Pixel photodiode (PD)
In a state where the storage part (23) retains charge from a deep potential, dark charge is likely to occur in the storage part itself and the amount of stored charge changes. Therefore, by making the potential shallow, the storage part itself This is to suppress the generation of dark charge. Regarding this point, the same applies to the high brightness integration mode shown in FIG. 20. FIG. 19(e) shows initialization,
That is, it shows an integral clearing operation.

In the high-intensity integration mode, Fig. 20(a) shows that during integration, (
b) shows the completion of integration, and (c) shows charge transfer to the shift register. Even in this case, the integration clearing operation is performed as shown in FIG. 19(e).

Next, regarding the analog processing section (18) shown in FIG.
This will be explained with reference to the time charts of FIGS. 16 to 18. As shown in FIG. 7, the first to fifth segments from the right of the shift register (26) do not have corresponding pixel photodiodes. Therefore, the buffer (27)
The first five of the pixel output signals (O8) output through are the outputs of the register segment without photodiode, followed by the output of the shaded pixel photodiode (OPD) from the 6th to the 10th, and then , the output of the pixel photodiode in the reference part (M.), the unnecessary part (
The output of the register segment corresponding to S), the reference part (
The output from the photodiode (Ml), and finally the output from the light-blocking pixel photodiode (OPD) on the left end side. The output waveform is shown in Figure 18 (
O3).

Initialization of the pixel output signal (O8) is performed by resetting the capacitor (C1) in FIG.

At that time, a reset pulse (OSRST) is applied to the gate of the transistor (Ql) to make the transistor (Ql) conductive and charge the capacitor (C+) to the power supply voltage (Vcc). Sometimes, a signal induced by the clock field through effect of the MOS transistor (Q,) is generated, and this (7)
)+J At the end of the set pulse (OSRST), the capacitor (C1) is charged to approximately the power supply voltage and represents the original reference level. However, this reference level fluctuates due to fluctuations in the power supply voltage when the reset pulse (OSRST) is applied. Next, at the falling edge of the transfer lock (φ1), the shift register (26) transfers one phase, and the capacitor (C1)
The accumulated charge of the next pixel photodiode flows into and is output. The amount of voltage drop at this time is the pixel output signal V os (n
), a reset pulse (OSRST) is also applied to the transistor (Ql) and the capacitor (C1)
is reset, and the pixel output signal Vos(n+1) of the next pixel photodiode is obtained at the next transfer lock (φ,). Pixel output signals are sequentially output in this manner, and the series of pixel output signals output in this way is sent to the 18th pixel output signal in the first sample and hold circuit (66).
A subtraction circuit (6
7), its differential output (O5dir)
The reset level of is set to a constant value, and the voltage drop from that level becomes the value of the pixel output signal. This power supply noise removal method is generally called a double sampling method.

Next, using the differential output (O5dir) obtained in this way, a second sample and hold circuit (not shown) provided in the same subtraction circuit (67) performs sample and hold. This is to ensure time for keeping the input analog amount constant for the A/D converter (54) in (53). The subtraction circuit (67)
The pixel output signal sampled and held is shown in Figure 18 (
VosS/H), Vos(n) and Vos, respectively.
(n+1), Vos becomes a signal with a value lowered by (n+2).

Among the pixel output signals (Vos) processed in this way, the seventh to ninth dark pixel output signals are sampled and held in the next third sample and hold circuit (70). The sampling pulse (OBS/H) at this time is the first
As shown in FIG. 6, the pulse is such that the output signal of the light-shielded pixel photodiode (OPD) that is shielded by the seventh to ninth aluminum films of the pixel output signal (Vos) is extracted. Note that the sixth signal is not sampled and therefore is not used for the following reason. That is, as shown in FIG. 7, the sixth pixel output signal is located at the end of the light-shielded pixel photodiode (OPD), so it is easily affected by external noise, and therefore its output is This is because the dark pixel output is not necessarily accurate. Said (OBS/
The 7th to 9th dark pixel outputs sampled by H) are processed at least until the output of a series of pixel photodiodes ends (12 in the shift register segment).
(until the eighth output is processed).

In this way, the sampled and held dark pixel output (V
OW) and the pixel output signal (V os) outputted from the 11th onwards, the next stage AGC subtraction circuit (71)
By taking this, it is possible to obtain a pixel output signal (Vos) based only on the photocharge output with the dark output removed. This subtraction is performed by the AGC subtraction circuit (7) shown in FIG.
1). In FIG. 15, (8) is an operational amplifier that takes the difference between the dark pixel output (Vos) input from the terminal (77) and the pixel output signal (Vos) input from the terminal (76). be. Furthermore, this operational amplifier (A
, ) Resistor (r+) (rz) (r-) (r4) connected between the output terminal and the negative input terminal (-) and the resistor connected between the reference voltage (Vref) and the positive input terminal (+) (rs) (ra) (rt) (rs) is connected to the analog switch (S,
) to (S8), the gain deficiency of the image output signal due to the forced stop of integration at low luminance is corrected. The signal that has passed through the AGCM calculation circuit (71) is output from the photoelectric conversion element (12) to the system controller (53). Therefore, the output level is adjusted to the dynamic range (1/3 V ref≦DR≦Vref) of the A/D converter (54) in the system controller (53), the pixel output in the dark is set to (V ref), and the pixel output The AGC subtraction circuit (71) is configured so that when (Vos) increases, the output form becomes Vref-Vos. That is, when a pixel output voltage (Vos) equal to the dark output voltage (VOW) input to the terminal (77) is input to the terminal (76), the output of the operational amplifier (A,) becomes Vref. , the input (
V.

When S) becomes lower than (VOR), the operational amplifier (A,
) output becomes Vref~Vos.

On the other hand, the color temperature detection output signals (O5R) (O5Y) are differentiated from the color temperature detection compensation signal (PDDOS) which acts as a reference voltage output in the second and third subtraction circuits (68) and (69).

Furthermore, the above-mentioned AGC is used to compensate the differential output in the dark, to make it an appropriate gain, and to adjust it to the reference voltage.
The subtraction circuit (71) is supplied with the subtraction circuit (71). At this time, the supply timing to the AGC subtraction circuit (71) is determined by the subtraction circuit (j7) (6B
) (69) followed by an analog switch (ANI)
(AND) The control signal (ANS+) (ANSi) (ANSi) shown in FIGS. 16 and 17 is given from the signal processing timing generator (16B) to (ANTI).
) is carried out by

As a result, in this embodiment, as shown in the pixel output signal (Vos) in FIGS. 16 and 17, during the output of the 10th pixel output signal immediately after the sampling of the dark output, the The yellow temperature detection signal (O5Y) is
During the output of the 11th pixel output signal, the red temperature detection signal (O5R) is sent to the AGC subtraction circuit (7
1). In addition, the color temperature detection signal (O3R) (
Instead of outputting O3Y) in the photoelectric conversion section (15) using a separate output sofa, as shown in Fig. 13, a light-blocking pixel photodiode (OPD) is used to output the same signal as the normal pixel output signal. If output is made through the route, the signals are output from the buffer (27) as the 10th and 12727th elementary output signals. Therefore, these outputs are supplied to the AGC subtraction circuit (71) after the noise components are removed by the aforementioned double sampling and the dark output is compensated by taking the difference from the dark output sampling value. In this case, the second and third subtraction circuits (68) (69
) and analog switch (ANI) (8Nri (AN3)
becomes unnecessary.

This concludes the explanation of the analog processing section (18), and next the temperature detection section (19) will be explained. Among the autofocus detection mechanisms shown in FIG. 2, for example, the lens holder (9
) and the reimaging lens (4a) (4b
), etc., expand depending on the temperature, causing slight changes in the dimensions of a predetermined portion.

This causes autofocus errors due to temperature.

From this point of view, a temperature detection section (19) is provided to electrically perform temperature compensation;
), as shown in Figure 21, connect a resistor (R+') (Ri) in series between the reference voltage (V ref), which is a predetermined potential lower than the power supply (Vcc), and the ground, and calculate the midpoint of the connection. Connected to the positive input terminal (+) of the amplifier (A6). Connect the negative input terminal (=) and the output terminal directly. Here, the resistance (R+) has a temperature coefficient βR+=5000p
Ion implanted resistance in pm, (R2) is temperature coefficient βR2=
It is a polysilicon resistor of 500 ppm, and the resistance value at 25° C. is 10 KΩ for both (R1) and (R2). FIG. 22 shows the output characteristics of the temperature detection section when the ia voltage Vcc=13V and the reference voltage Vref=5V in FIG. 21. The detection output is expressed by the voltage across the resistor (R+).

In the time charts of FIGS. 16 and 17, AG
The pixel output signal (V
up to the 9th output of the charging conversion element (1
There is no need to provide the system controller (53) as the output signal of step 2). System controller (53)
The signal to be supplied to is from the yellow temperature detection signal (OSY) located at the 10th position. Therefore, up to the 9th position, the temperature detection signal (Vtz, 1) is used instead of the pixel output signal.
through the same output line to the system controller (5
3) Give. For this reason, analog switches (ANA) (AN,) are provided in front of the connection point (a) between the AGC subtraction circuit (71) and the temperature detection circuit (19), and these analog switches (ANa) (ANs) The gate signal (ANS) shown in FIG. 16 (and FIG.
4) (ANSS) is supplied.

Next, the specific configuration of the transfer lock generating section (16A) is shown in FIGS. 26(a) and 26(b).
Figure 6 (a) shows the part that forms the shift pulse (SH),
Figure 26(b) shows transfer locks (φ,) (φ2), (OSR5T) (RSS/H) (O3S/H)
(ADS) etc. is shown. Figure 26(a)
(16a) is a system controller (53)
This is the first frequency divider that divides the basic clock (CP) from CP, and its divided output is (SHM) (IC5) (TEXT
) is frequency-divided by the second frequency divider (16c) which is reset by the output of the shift pulse forming section (16b) which forms the shift pulse (SH) according to the logic of (QDO) (QDI
) (QD2) is generated. These outputs are shown in Figure 26 (b
) is decoded by the decoder unit (16d) of the decoder unit (
(φl) (φz) C through the circuit following 16d)
05R5T) etc. are created.

FIG. 27 shows a specific example of the signal processing timing generation section (20a), which inputs (φ, ) (SH) (ICS) and generates (ANS+) to (ANSs) and (OBS/H).
(ADT) is generated. (ADT) is a control signal that triggers A/D conversion of the system controller (53).

Next, the system controller (53) will be explained.

A/D converter (54) in the system controller (53)
) is formed as shown in Fig. 23, and the terminal (78
) is the pixel output signal (
Vout) is input, and the reference voltage (Vr
ef), (^DT) is input to the terminal (80). Then, the A/D conversion output is derived from the terminals (01) (0□)... (On).

The system controller (53) detects the color temperature of the subject by calculating the ratio R of the digital values (Vast) (Vosy) of the A/D-converted color temperature detection signal (OSR) (OSY), and calculates the color temperature of the subject. Corrections are made according to the temperature, and the flowchart is shown in the 24th section.
As shown in the figure. Figure 24 shows the overall flow of focus detection operation.
25(a), (b), (c), and (d) particularly show the flow of color temperature correction.

First, an outline of the focus detection operation will be explained using FIG. 24. When the focus detection operation is started by pressing the shutter button on the camera, the system controller (53) resets the flag and inputs lens data including color temperature correction data from the lens data output section (61). The system controller (53) sets an integration mode (ST) in which the storage unit performs storage (signal MDI = low level, MD2 = high level), and sets the maximum integration time to 20a+sec. Then, an integration clear signal (ICS) is generated to start integration. At this time, the integration of the color temperature detection photodiodes (13) and (14) is also performed at the same time. Then, it waits for the integration end signal (TINT) indicating the end of integration to become low level, and when it becomes low level, it is determined that the integration has ended, and the time required for this is determined. If the time is within 1m5ec, the high-luminance flag (HLF) is set to set the next integration mode to a mode (ST mode) that performs integration to the storage section, and the time is 1m5ec.
If it is between 5ec and 20m5ec, the next integration mode will be the same as this time, and the integration end signal (TI) will be sent within 20m5ec.
NT) does not become a low level, a low luminance flag (LLF) is set so that the next integration mode will be a mode (PD mode) for integrating into the light receiving section. In either case, a signal (SHM) -
is output and waits for the integration end signal (TINT) to become low level. This allows 20m5 in low brightness integration mode.
Only when the integration is not completed within ec, the process waits for the integration end signal to become low level; otherwise, it is already low level. Note that pixel data is sent to the shift register by a shift pulse in terms of hardware. If the integration end signal (TINT) is at the low level, the system controller (53) sets the data input mode and inputs the AGC data of the digital signal. Next, temperature data is input, but AID conversion for this analog data is started by a pulse of the signal (ADT), and the completion of this A/D conversion is waited. When the A/D conversion is completed, temperature data (SBT) is input and stored in a predetermined register. As described above, this temperature data input is at the timing of the ninth data input of the shift register (26) (see the time chart) (no data is input to the shift register).

Next, the system controller (53) sets the number of pixels of the captured data including the number of color temperature detection photodiodes and the number of pixel output signals, and sets the input analog signal (Vo
s) is performed, and data is stored in the internal memory each time an interrupt signal is generated due to the completion of the A/D conversion, and this is repeated for the set number of times. In this way, memory (
55), the reference part (M.) and the reference part (M.
The digital signal corresponding to each image in l) is used to obtain the image interval of both parts (M.) and (Ml) using a correlation calculation as disclosed by the applicant in Japanese Patent Laid-Open No. 60-247211. Calculate the defocus df. After calculating df by distance measurement calculation, temperature correction is also performed based on the output from the temperature detection section (19). Therefore, β is the temperature correction coefficient of the camera itself, SBT is the temperature information, and SBT is 25
This is basic temperature information in °C. The temperature-corrected defocus dfo is set to take the true value when the light source of the subject is sunlight.

This defocus! dfo is a predetermined value Tdf (=2 to 3
mm), the color temperature correction value is not that large (approximately 100 to 200 μm or less), so
The correction value itself does not have a large effect, and when the lens is driven and re-measurement is performed, if defocus of less than the predetermined value Tdf is detected, the color temperature correction value Δd
f will be added. In this way, the color temperature correction value Δd
After f is added, focus is determined, and if it is within the focus range, the focus is displayed, and if it is determined that it is not in focus, the color temperature correction value △df is added to the defocus 1taro. Start lens driving according to defocus 1ldf,
After the integration mode is set, the routine from the step of starting integration upon generation of TC3 is repeated.

Here, we will add an explanation of the internal operation of color temperature correction.

As mentioned earlier, the lens color temperature correction data dFt is input at the top of the flowchart.

This value is, for example, the amount of chromatic aberration of each lens with respect to 550 nm (daylight) when an 800 nm monochromatic light source is stored in the memory within the lens. On the other hand, the output signal (OSR) of the color temperature detection photodiode is integrally controlled simultaneously with each pixel photodiode and subjected to analog processing.
OSY) is digitized by the A/D converter (54) of the system controller (53), and (Vos++) (Vo
sy) in the memory (55). The system controller (53) calculates the ratio R of (■.s++)(V.sv) as shown in FIG. 25(a). When this ratio R is a predetermined value, for example, 1.8 or more, it is determined that the incident light from the subject has many long wavelength components and has a low color temperature, and a predetermined coefficient k (0) is added to dFL of the color temperature correction data.
≦kl71) and set the color temperature correction amount Δdf. Conversely, when the ratio R is 1.2 or less, it is determined that the incident light from the subject has many short wavelength components and the color temperature is low, and the color temperature correction data dF is set to a predetermined coefficient -2 (0≦). 2≦1
) and set the color temperature correction amount to Δdf. When the ratio R is between 1.2 and 1.8, the incident light from the subject is integrated by a light component close to daylight, and color temperature correction is not necessary, and the color temperature correction amount Δdf is =0
shall be. The color temperature correction amount Δdf determined based on the light from the object is added to the defocus Wtdro determined by distance measurement calculation to calculate the true detected defocus amount df.

Color temperature correction is performed in this way, but as another method, the necessity of color temperature correction is determined as a lens index depending on the type of lens, and color temperature correction is performed as shown in the flowchart in FIG. 25(b). By first determining whether the color temperature is correct or not, if color temperature correction is not necessary, the processing speed can be increased without going through an extra flow. Also, instead of deciding each correction value in a dissipative manner as in (a) and (b),
The second flow of determining the correction value continuously for the value of R is
This is shown in Figure 5(c). Here, R may show infinity for an object having a single wavelength component of a short wavelength, whereas the chromatic aberration of an optical system naturally has a finite value as long as it is visible light. To add restrictions for that, R
In the case of ≧2.5, the value of R is limited to 2.5, and the correction amount is set to the above-mentioned lens color temperature defocus correction amount and a predetermined coefficient of 1 and the ratio R to 1 at the reference daylight color. .5
Determined by multiplying by the value obtained by subtracting .

Next, when performing discretely as shown in FIG. 25(a),
If the value of the correction amount Δdf can be set for each lens, as shown in FIG. 25(d) (the correction amount Δdf is R≧1).
．． When R is 8, it is df, and when R≦1.2, it is dfz, which are the values given to each lens individually.

In any case, in the embodiments described above, the color temperature of long wavelength components and short wavelength components within visible light is detected and corrected, so that the accuracy of focus detection is improved.

In the embodiments described above, especially FIGS. 7 and 14.

As mentioned in connection with FIG. 18, the shift register (26
) is connected to the capacitor (C1) that receives the output of the transistor (
After resetting with Q, ), the sample and hold circuit (66) uses the pulse (RSS/H) to sample and hold, and the subtraction circuit (67) in the next stage uses this hold output and the reset value of the capacitor (C1). By subtracting from the output, power supply fluctuation noise introduced at the time of reset is removed. Of the output signal from which power supply fluctuation noise has been removed in this way, the light-shielded pixel photodiode (OPD)
The sample and hold output is sampled and held by the sample and hold circuit (70), and this hold output and the pixel photodiode (PD
), dark noise is removed.

According to the present invention, since power supply noise and dark noise are removed from the photoelectric conversion signal from the light receiving element in the subsequent circuit, the quality of the image signal finally obtained is improved. effective. Moreover, since the means for removing these noises are provided in the same IC chip, there is an effect that the IC chip is resistant to external noise.

[Brief explanation of drawings]

All figures relate to the present invention, and FIG. 1 is a diagram showing the principle of an optical system when the image sensor of the present invention is used for focus detection of a camera. FIG. 2 is an exploded perspective view of the sensor module.
FIG. 3 is a schematic configuration diagram of a photoelectric conversion element. FIGS. 4 and 5 are characteristic diagrams for explaining the spectral problems associated with the color temperature detection photodiode. FIG. 6 is a block circuit diagram of the photoelectric conversion element, and FIG. 7 is a diagram showing the circuit configuration of the photoelectric conversion section. FIG. 8 is an enlarged view of a part of FIG. 7, and FIG. 9 is a sectional view taken along the line AA' in FIG. FIG. 10 is a structural diagram showing the physical structure of a pixel photodiode. FIG. 11 is a diagram showing the structure of the output section of the shift register in FIG. 7 in comparison with a conventional example. 12th
The figure is a diagram showing a schematic shape of a photoelectric conversion unit viewed from the light incident direction. FIG. 13 is a diagram of another embodiment corresponding to FIG. 8. FIG. 14 is a block circuit diagram showing the overall configuration of the image sensing system, and FIG. 15 is a specific circuit diagram of a portion thereof. 16 and 17 are time charts of each partial signal of FIG. 14 in the low-luminance integration mode and the high-luminance integration mode, respectively. FIG. 18 is a diagram of various signal waveforms for explaining the operation of the analog processing section in FIG. 14. FIGS. 19 and 20 are diagrams showing the physical operation of the photoelectric conversion section in the low-brightness integration mode and the high-brightness integration mode, respectively. FIG. 21 is a specific circuit diagram of the temperature detection section, and FIG. 22 is its output characteristic diagram. FIG. 23 is a circuit diagram of the A/D conversion section of the system controller. FIG. 24 is a flowchart showing the operation of the system controller, and FIG. 25 is a flowchart showing a portion thereof in detail. FIG. 26 is a specific circuit diagram of the transfer lock generation section, and FIG. 27 is a specific circuit diagram of the signal processing timing generation section. (PDn--pixel photodiode (first light receiving element)
. (OP D) - Light-shielding pixel photodiode (second light receiving element), (C+)... Capacitor. (12) ---One photoelectric conversion element (image sensor),
(26)--Shift register, (66)--Sample and hold circuit. (67)...-subtraction circuit (first subtraction means), (70)
-Sample and hold circuit (holding means), (71)
- a subtraction circuit (second subtraction means);

Claims (1)

[Claims] (1) A first light receiving element that outputs an electrical signal according to the intensity of incident light, a second light receiving element formed of the same material as the first light receiving element and shielded from light, and receiving electrical signals from each of the light receiving elements. a shift register that sequentially outputs output in accordance with a predetermined clock signal; a capacitor connected to the output end of the shift register; and means for resetting the capacitor by once coupling it to a power source each time the electric signal is shifted; means for sampling and holding the reset voltage from the capacitor; first subtracting means for taking a difference between the sampled and held voltage and the output signal from the capacitor based on the reset electrical signal; and the first subtracting means. A holding means for holding the output of the second light receiving element among the outputs of the holding means and a second subtraction means for taking the difference between the output of the holding means and the output of the first light receiving element are formed on the same IC chip. An image sensor characterized by: