JPS63166237A - Method of processing semiconductor substrate - Google Patents

Method of processing semiconductor substrate

Info

Publication number
JPS63166237A
JPS63166237A JP31168186A JP31168186A JPS63166237A JP S63166237 A JPS63166237 A JP S63166237A JP 31168186 A JP31168186 A JP 31168186A JP 31168186 A JP31168186 A JP 31168186A JP S63166237 A JPS63166237 A JP S63166237A
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor substrate
defect
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31168186A
Other languages
Japanese (ja)
Inventor
Tetsuo Fukuda
哲生 福田
Ritsuo Takizawa
滝沢 律夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31168186A priority Critical patent/JPS63166237A/en
Publication of JPS63166237A publication Critical patent/JPS63166237A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify an intrinsic gettering process and reduce its time, by a method wherein a non-defective layer is formed on the surface layer part of a substrate by performing, in a non-oxidizing atmosphere and at a specified temperature, heat treatment of a semiconductor substrate whose surface is subjected to lapping, heat treatment is performed to form a defective layer in the inside, and then polishing of the non- deflective layer in the substrate is performed up to a necessary depth. CONSTITUTION:A sliced semiconductor substrate, for example, a silicon substrate 1 is subjected to a mechanical lapping up to a depth necessary to eliminate damages due to slicing. In a heating process, a silicon substrate 3 subjected to this lapping is heated at a temperature higher than or equal to 1000 C for a specified time in a non-oxidizing gas, such as nitrogen (N2) or rare gas. Thus, I-Si existing in a substrate surface layer is diffused, and a non-defective layer is formed in the substrate surface layer. Further, I-Si existing in the inside is collected, and a defective layer is formed. After a heat treatment 4, the substrate is abraded up to a necessary width for a non- defective layer, and subjected to polishing to form a mirror type substrate 6. Thereby, the forming process of a substrate with intrinsic gettering effects can be remarkably simplified and its necessary time can be reduced.

Description

【発明の詳細な説明】 〔概 要〕 半導体基板をラッピングした後、該半導体基板を100
0℃以上の温度に加熱してその表層部に存在する格子間
原子を外拡散させて該表層部に無欠陥層を形成すると共
に、内部層に存在する格子間原子を集合させて該内部層
に積層欠陥を生成せしめ、しかる後上記無欠陥層を、該
無欠陥層に形成される半導体素子の底面と内部の欠陥析
出層との間が所要の距離になるような厚さまでポリッシ
ングする半導体基板の処理方法で、半導体素子形成領域
の汚染不純物を内部の積層欠陥に捕捉せしめて半導体素
子性能を向上する効果を有する半導体基板構造の形成工
程が、従来より単純化され且つ大幅に短時間化される。
[Detailed Description of the Invention] [Summary] After lapping the semiconductor substrate, the semiconductor substrate is
The interstitial atoms present in the surface layer are heated to a temperature of 0°C or higher to diffuse out to form a defect-free layer in the surface layer, and the interstitial atoms present in the internal layer are aggregated to form the inner layer. Stacking faults are generated in the semiconductor substrate, and the defect-free layer is then polished to a thickness such that the distance between the bottom surface of the semiconductor element formed in the defect-free layer and the internal defect precipitation layer is a required distance. With this processing method, the process of forming a semiconductor substrate structure, which has the effect of trapping contaminant impurities in the semiconductor element formation region into internal stacking faults and improving semiconductor element performance, is simplified and significantly shorter than conventional methods. Ru.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体基板の処理方法に係り、特にイントリン
シック・ゲッタリング構造を形成するための半導体基板
の処理方法に関する。
The present invention relates to a method of processing a semiconductor substrate, and more particularly to a method of processing a semiconductor substrate for forming an intrinsic gettering structure.

半導体装置の製造に用いられるシリコン単結晶は一般に
チョクラルスキー(CZ)法によって製造されるが、そ
の際坩堝として通常石英ガラス製のものが用いられるた
めに、最終的に得られた該シリコン単結晶中には30〜
40ppm程度の高濃度に酸素原子が含まれる・ 従って該シリコン単結晶から形成されたシリコン基板を
用いてIC等の半導体装置を製造する際には、特に高温
に曝される製造工程において該基板中に含まれる酸素原
子が、該基板内で結晶欠陥に成長し、更に重金属等の汚
染不純物と結合して半導体装置の性能を低下させるとい
う問題を生ずる。
Silicon single crystals used in the manufacture of semiconductor devices are generally manufactured by the Czochralski (CZ) method, but since a crucible usually made of quartz glass is used, the silicon single crystals finally obtained are 30~ in the crystal
Oxygen atoms are included at a high concentration of about 40 ppm. Therefore, when manufacturing semiconductor devices such as ICs using a silicon substrate formed from the silicon single crystal, there are Oxygen atoms contained in the semiconductor grow into crystal defects within the substrate, and further combine with contaminant impurities such as heavy metals, resulting in a problem that the performance of the semiconductor device is degraded.

そこで、上記高温製造工程における重金属等による汚染
を回避するための半導体基板の処理方法が必要とされる
Therefore, there is a need for a method for processing semiconductor substrates to avoid contamination by heavy metals and the like during the above-mentioned high-temperature manufacturing process.

〔従来の技術〕[Conventional technology]

上記重金属不純物等による汚染を回避するために従来量
も広く用いられていたのが、イントリンシック・ゲッタ
リング(IG)法と呼ばれる基板の熱処理方法である。
A substrate heat treatment method called the intrinsic gettering (IG) method has been widely used in the past to avoid contamination by heavy metal impurities and the like.

IC等の半導体装置における動作領域は、通常シリコン
基板の表面から10μm以下程度の表層部に形成される
ので、上記汚染不純物による性能劣化を回避するために
は、少なくとも該表層部のみを無欠陥で且つ汚染不純物
を含まない層に形成してやればよい。
The operating region of semiconductor devices such as ICs is usually formed in the surface layer about 10 μm or less from the surface of the silicon substrate, so in order to avoid performance deterioration due to the above-mentioned contaminating impurities, at least only the surface layer should be made defect-free. In addition, it may be formed as a layer that does not contain contaminating impurities.

そのため上記従来のIC法においては、シリコン基板に
対して、非酸化性雰囲気中において、例えば先ず110
0℃、1時間程度の第1次熱処理を行い、表層部の酸素
原子を外拡散させることによって該半導体基板の表層部
を無欠陥層となし、次いで600℃程度の温度で200
時間程の第2次熱処理を行って基板内部の酸素原子を欠
陥核として析出さた後、800〜1000°C程度の温
度で1時間程度の第3次熱処理を行い上記欠陥核を結晶
欠陥に成長せしめることによって、該半導体基板の内部
に多数の結晶欠陥を有する欠陥層が形成される。
Therefore, in the conventional IC method described above, the silicon substrate is first heated at 110 nm in a non-oxidizing atmosphere.
A first heat treatment is performed at 0°C for about 1 hour to make the surface layer of the semiconductor substrate defect-free by diffusing oxygen atoms in the surface layer, and then heat treatment is performed at a temperature of about 600°C for 200 minutes.
After performing a second heat treatment for about an hour to precipitate the oxygen atoms inside the substrate as defect nuclei, a third heat treatment for about an hour is performed at a temperature of about 800 to 1000°C to turn the defect nuclei into crystal defects. By growing, a defective layer having many crystal defects is formed inside the semiconductor substrate.

そして汚染不純物に対し上記結晶欠陥の有するゲッタリ
ング効果によって、該基板表層部の無欠陥層内の汚染不
純物が基板の内部側へ除去され、該基板表層部に形成さ
れる動作領域の不純物汚染による性能劣化が防止される
Then, due to the gettering effect of the crystal defects on the contaminant impurities, the contaminant impurities in the defect-free layer in the surface layer of the substrate are removed to the inside of the substrate, and due to the impurity contamination of the operating region formed in the surface layer of the substrate. Performance deterioration is prevented.

第4図は上記IG処理を施したシリコン基板51の断面
を模式的に示したもので、図中、52は酸素原子が外拡
散して基板表層部にできた無欠陥層、53は酸素原子に
より形成された結晶欠陥、54は酸素原子による結晶欠
陥が多数個存在せしめられている基板内部の欠陥層を表
している。
FIG. 4 schematically shows a cross section of a silicon substrate 51 subjected to the above-mentioned IG treatment. In the figure, 52 is a defect-free layer formed on the surface layer of the substrate by oxygen atoms diffused out, and 53 is an oxygen atom. 54 represents a defect layer inside the substrate in which a large number of crystal defects due to oxygen atoms are present.

以上のような手法による従来のIC法は、基板表層部に
形成される動作領域の重金属による汚染を回避する効果
は充分に備えていた。しかしながら上記代表例に示され
るように、熱処理工程が複雑であり、且つ極めて長時間
を要するという問題があった。
The conventional IC method using the method described above has a sufficient effect of avoiding contamination by heavy metals in the active region formed on the surface layer of the substrate. However, as shown in the above representative example, there was a problem that the heat treatment process was complicated and required an extremely long time.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明が解決しようとする問題点は、半導体装置の製造
プロセスにおける重金属汚染回避のために行われていた
従来のIC方法が、複雑で且つ長時間を要していたこと
である。
The problem to be solved by the present invention is that the conventional IC method used to avoid heavy metal contamination in the manufacturing process of semiconductor devices is complicated and takes a long time.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、半導体装置の製造に用いられる半導体基
板の処理方法であって、スライスされた半導体基板(1
)の表面をラッピングする工程(2)と、該ラッピング
された半導体基板(3)を、非酸化性雰囲気中において
1000℃以上の温度で熱処理して該半導体基板の表層
部に無欠陥層を形成すると共に、内部に欠陥層を形成す
る熱処理工程(4)と、該熱処理の終わった半導体基板
の無欠陥層を所要の厚さまでポリッシングする工程(5
)とを有する本発明による半導体基板の処理方法によっ
て解決される。
The above problem lies in the processing method for semiconductor substrates used in the manufacture of semiconductor devices.
), and the lapped semiconductor substrate (3) is heat-treated at a temperature of 1000°C or higher in a non-oxidizing atmosphere to form a defect-free layer on the surface layer of the semiconductor substrate. At the same time, a heat treatment step (4) for forming a defective layer inside, and a step (5) for polishing the defect-free layer of the semiconductor substrate after the heat treatment to a required thickness.
) is solved by a method for processing a semiconductor substrate according to the present invention.

〔作 用〕[For production]

即ち本発明の方法においては、非酸化性の雰囲気中にお
いて、半導体基板例えばシリコン基板を1000℃以上
の温度例えば1100℃で0.5時間程度熱処理するこ
とによって、基板結晶中の格子間(intersti 
tial)シリコン原子(以下r−3t原子と称す)を
、上記1100℃における該1−3i原子の拡散定数が
約10−’ [cm/sec”コであることから、次式
に基づいて、 (10−’x60” Xo、5 ) #130 [μm
l程度移動せしめる。
That is, in the method of the present invention, a semiconductor substrate, such as a silicon substrate, is heat-treated at a temperature of 1000° C. or higher, such as 1100° C., for about 0.5 hours in a non-oxidizing atmosphere, thereby removing interstitials in the substrate crystal.
Since the diffusion constant of the 1-3i atoms at 1100°C is approximately 10-' [cm/sec], based on the following formula, ( 10-'x60"Xo, 5) #130 [μm
Move it about l.

そして該移動により表面から約130μmの幅の層のl
−5i原子を外拡散させて該領域を無欠陥層とすると共
に、内部の層のl−5t原子を上記移動により集合せし
めて、該内部の層に積層欠陥を析出させる。
As a result of this movement, a layer with a width of about 130 μm is formed from the surface.
The -5i atoms are diffused out to make the region defect-free, and the l-5t atoms in the inner layer are aggregated by the above movement to precipitate stacking faults in the inner layer.

次いで上記のような熱処理を終わったシリコン基板の表
面即ち無欠陥層の表面を、該無欠陥層の表面部に半導体
素子を形成した際に、基板内部の欠陥層内の結晶欠陥に
よる汚染不純物のゲッタリング効果が該無欠陥層の表面
部まで及ぶ所要の無欠陥層幅例えば50〜60μmまで
ポリッシング法により鏡面研磨する。
Next, when a semiconductor element is formed on the surface of the defect-free layer of the silicon substrate that has been heat-treated as described above, that is, the surface of the defect-free layer, contaminating impurities due to crystal defects in the defect layer inside the substrate are removed. The defect-free layer is mirror-polished by a polishing method to a required defect-free layer width of, for example, 50 to 60 μm so that the gettering effect extends to the surface of the defect-free layer.

以上により従来同様のイントリンシック・ゲッタリング
効果を有する半導体基板が、従来に比べて簡略化され且
つ大幅に短時間化された処理工程により容易に形成され
る。
As described above, a semiconductor substrate having the same intrinsic gettering effect as the conventional one can be easily formed through processing steps that are simplified and significantly shortened compared to the conventional one.

〔実施例〕〔Example〕

以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.

第1図は本発明の原理を示す模式1程図、第2図は本発
明の一実施例の模式1程図、第3図(a)〜(′b)は
ポリッシング工程の模式断面図である。
Figure 1 is a schematic diagram showing the principle of the present invention, Figure 2 is a schematic diagram of the first embodiment of the present invention, and Figures 3 (a) to ('b) are schematic cross-sectional views of the polishing process. be.

本発明に係る半導体基板の処理方法の原理は第1図に模
式的に示す工程図のように、スライスされた半導体基板
例えばシリコン基板1を、該スライシングのダメージが
除去される深さに機械的に研磨除去するラフピング工程
2と、該ラッピングされたシリコン基板3を窒素(N2
)或いは希ガス等の非酸化性ガス中において1000℃
以上の温度で所定時間加熱し該基板表層部に存在するl
−3iを該拡散させて該基板の表層部に無欠陥層を形成
し、且つ内部に存在するl−5iを集合させて欠陥層を
形成する熱処理工程4と、該熱処理工程4を終わったシ
リコン基板を通常のメカニカル・ケミカルポリッシング
手段により所要の無欠陥層幅まで研磨し、且つ鏡面状シ
リコン基板6に仕上げるポリッシング工程5を含んでい
ることを特徴としている。なお本発明に係る処理を完了
した鏡面状半導体基板5は、次いでIC等の半導体装置
のプロセス工程7へ導入される。
The principle of the semiconductor substrate processing method according to the present invention is as shown in the process diagram schematically shown in FIG. Rough ping step 2 involves polishing and removing the silicon substrate 3, and nitrogen (N2
) or 1000℃ in non-oxidizing gas such as rare gas
When heated at a temperature above for a predetermined period of time, the l
-3i is diffused to form a defect-free layer on the surface layer of the substrate, and l-5i existing inside is aggregated to form a defective layer; a heat treatment step 4 of silicon after the heat treatment step 4; The present invention is characterized in that it includes a polishing step 5 in which the substrate is polished to a desired defect-free layer width by ordinary mechanical/chemical polishing means and finished into a mirror-like silicon substrate 6. Incidentally, the mirror-like semiconductor substrate 5 that has undergone the processing according to the present invention is then introduced into a process step 7 for semiconductor devices such as ICs.

実際の工程に適用する際には、例えば第2図に示す一実
施例のように、スライスされたシリコン基板1を、例え
ば9〜13μmφ程度の粒度を有する研磨材を用いる通
常のラッピング工程2によりスライスのダメージが除去
さ・れる程度まで研磨してラッピング済み半導体基板3
を形成する。
When applied to an actual process, for example, as in the embodiment shown in FIG. Semiconductor substrate 3 polished and lapped to the extent that slice damage is removed
form.

次いでトリクレン、アルコール、アセトン等による通常
の有機溶剤洗浄8を行って該基板面の油脂骨を除去した
後、該基板面をラッピングのダメージが除かれほぼ平坦
化されるまで、通常通り弗硝酸系の液によりエツチング
処理9し、次いで通常通りアンモニア水等による重金属
等の金属分除去用洗浄10を行った後、該ラッピング済
み基板3が熱処理工程4に送り込まれる。
Next, a normal organic solvent cleaning 8 using trichloride, alcohol, acetone, etc. is performed to remove the oil and fat bones on the substrate surface, and then the substrate surface is washed with fluoronitric acid as usual until the damage from lapping is removed and the surface is almost flat. After etching treatment 9 with a solution of 1 and then cleaning 10 for removing metal components such as heavy metals with aqueous ammonia or the like as usual, the wrapped substrate 3 is sent to a heat treatment step 4.

そして該熱処理工程4において、非酸化性ガス例えばN
t中にお゛いて1100℃で30分程度熱処理がなされ
る。この熱処理によって該基板3の表層部の1−Siは
前述したように外拡散して失われ該表層部に深さ即ち幅
が130μm程度の無欠陥層が形成される。またこれと
共に該基板の内部のl−5iは集合して前述したように
積層欠陥を生成し、該基板の内部領域に積層欠陥が多発
した欠陥層が形成される。
In the heat treatment step 4, a non-oxidizing gas such as N
Heat treatment is performed at 1100° C. for about 30 minutes during t. As a result of this heat treatment, the 1-Si in the surface layer of the substrate 3 is diffused out and lost as described above, and a defect-free layer having a depth, that is, a width of about 130 .mu.m, is formed in the surface layer. At the same time, the l-5i inside the substrate aggregate to generate stacking faults as described above, and a defective layer with many stacking faults is formed in the internal region of the substrate.

次いで該熱処理済みシリコン基板面はその表面を鏡面仕
上げする通常のポリッシング工程5に送り込まれ、該シ
リコン基板面を上記無欠陥層の表面部の半導体素子形成
領域に内部の欠陥層に存在する積層欠陥による汚染不純
物の捕捉効果が及ぶ厚さ即ち層幅例えば50〜60μm
まで通常のメカニカル・ケミカルポリッシング法により
化学研磨され且つ鏡面に仕上げられる。
Next, the heat-treated silicon substrate surface is sent to a normal polishing step 5 for mirror-finishing the surface, and the silicon substrate surface is polished to eliminate stacking defects existing in the internal defect layer in the semiconductor element formation region of the surface portion of the defect-free layer. The thickness at which the trapping effect of contaminant impurities is achieved, that is, the layer width, for example, 50 to 60 μm
It is chemically polished and finished to a mirror surface using normal mechanical/chemical polishing methods.

そして該ポリッシングを終わったシリコン基板6は図示
しない通常の洗浄、乾燥工程を経てIC等の半導体装置
の製造工程7へ送り込まれる。
After the polishing, the silicon substrate 6 is sent to a manufacturing process 7 for semiconductor devices such as ICs through normal cleaning and drying steps (not shown).

第3図は上記ポリッシングの工程を模式的に示した模式
断面図であるが、この図の(alに示すように前記熱処
理工程4により130μm程度の幅6に形成された無欠
陥N11は、その表面部に10μm以下程度の深さに形
成される半導体素子の動作領域に、内部の欠陥析出層1
2に存在する積層欠陥13による汚染不純物のゲッタリ
ング効果が及ぶよう、前述のように50〜60μm程度
の幅匈、にポリッシングされる。
FIG. 3 is a schematic cross-sectional view schematically showing the polishing process described above, and as shown in (al) of this figure, the defect-free N11 formed with a width 6 of about 130 μm by the heat treatment process 4 is An internal defect precipitation layer 1 is formed in the operating region of the semiconductor element, which is formed on the surface to a depth of about 10 μm or less.
As described above, polishing is performed to a width of about 50 to 60 μm so that the gettering effect of contaminant impurities caused by the stacking faults 13 existing in 2 is applied.

以上実施例に示したように本発明の方法によれば、半導
体装置の動作領域が形成されるシリコン基板の表層部に
無欠陥層を有し、且つ内部に重金属等の汚染不純物を捕
捉する積層欠陥を多数形成させた欠陥層を有してなり、
従来同様の汚染不純物のIC効果を有するシリコン基板
を、従来より簡略化され、且つ大幅に短時間化された熱
処理工程により形成することができる。
As shown in the embodiments above, according to the method of the present invention, a layered layer having a defect-free layer on the surface layer of the silicon substrate on which the operating region of a semiconductor device is formed, and trapping contaminant impurities such as heavy metals inside. It has a defect layer in which many defects are formed,
A silicon substrate having the same IC effect of contaminant impurities as in the past can be formed by a heat treatment process that is simpler and much shorter than the conventional one.

なお本発明におけるポリッシングは、図示のように両面
ポリッシングでなく、主面側のみの片面ポリッシングで
もよい。
Note that the polishing in the present invention is not double-sided polishing as shown in the drawings, but may be single-sided polishing only on the main surface side.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明の方法によれば、IC等の半導
体装置の性能を向上安定化せしめるうえに有効な、表層
部に無欠陥層を有し、且つ内部に欠陥層を有して汚染不
純物のイントリンシック・ゲッタリング効果を備えた半
導体基板の形成工程を、大幅に簡略化し、且つ短手香化
することができる。
As explained above, according to the method of the present invention, the surface layer has a defect-free layer and the interior has a defect layer, which is effective for improving and stabilizing the performance of semiconductor devices such as ICs. The process of forming a semiconductor substrate having an intrinsic gettering effect of impurities can be greatly simplified and made simpler.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理を示す模式1程図、第2図は本発
明の一実施例の模式1程図、第3図はポリソシング工程
の模式断面図、第4図は従来のIG処理を施したシリコ
ン基板の模式断面図 である。 図において、 工はスライス後のシリコン基板、 2はラッピング済程、 3はラッピング済みシリコン基板、 4は熱処理工程、 5はポリソシング工程、 6は鏡面仕上げシリコン基板、 7はrc製造工程、 8は有機洗浄工程、 9はエツチング工程、 10は金属不純物洗浄工程、 11は無欠陥層、 12は積層欠陥層、 13は積層欠陥 を示す。 亨1 @ 茶2 図
Fig. 1 is a schematic 1st step diagram showing the principle of the present invention, Fig. 2 is a schematic 1st step diagram of an embodiment of the present invention, Fig. 3 is a schematic cross-sectional view of the polysocing process, and Fig. 4 is a conventional IG process. FIG. 2 is a schematic cross-sectional view of a silicon substrate subjected to a process. In the figure, step is a silicon substrate after slicing, 2 is a wrapped silicon substrate, 3 is a wrapped silicon substrate, 4 is a heat treatment process, 5 is a polysocing process, 6 is a mirror finished silicon substrate, 7 is a RC manufacturing process, 8 is an organic 9 is an etching process, 10 is a metal impurity cleaning process, 11 is a defect-free layer, 12 is a stacking fault layer, and 13 is a stacking fault. Toru 1 @ Tea 2 Figure

Claims (1)

【特許請求の範囲】 半導体装置の製造に用いられる半導体基板の処理方法で
あって、 スライスされた半導体基板(1)の表面をラッピングす
る工程(2)と、 該ラッピングされた半導体基板(3)を、非酸化性雰囲
気中において1000℃以上の温度で熱処理して該半導
体基板の表層部に無欠陥層を形成すると共に、内部に欠
陥析出層を形成する熱処理工程(4)と、 該熱処理の終わった半導体基板の無欠陥層を所要の厚さ
までポリッシングする工程(5)とを有することを特徴
とする半導体基板の処理方法。
[Claims] A method for processing a semiconductor substrate used in manufacturing a semiconductor device, comprising: a step (2) of lapping the surface of a sliced semiconductor substrate (1); and a step (2) of lapping the surface of a sliced semiconductor substrate (3). a heat treatment step (4) of forming a defect-free layer on the surface layer of the semiconductor substrate and forming a defect precipitation layer inside by heat-treating the semiconductor substrate at a temperature of 1000° C. or higher in a non-oxidizing atmosphere; A method for processing a semiconductor substrate, comprising a step (5) of polishing the defect-free layer of the finished semiconductor substrate to a required thickness.
JP31168186A 1986-12-27 1986-12-27 Method of processing semiconductor substrate Pending JPS63166237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31168186A JPS63166237A (en) 1986-12-27 1986-12-27 Method of processing semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31168186A JPS63166237A (en) 1986-12-27 1986-12-27 Method of processing semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS63166237A true JPS63166237A (en) 1988-07-09

Family

ID=18020186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31168186A Pending JPS63166237A (en) 1986-12-27 1986-12-27 Method of processing semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS63166237A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294256A (en) * 2007-05-25 2008-12-04 Sumco Corp Production process of silicon single crystal wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294256A (en) * 2007-05-25 2008-12-04 Sumco Corp Production process of silicon single crystal wafer

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