JPS63164619A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the interference between adjacent channels, transmission error rate and mixed noise by adding a tap as a means eliminating at least one of a reference frequency and its harmonic ripple to a control signal line so as to reduce the side band spurious radiation. CONSTITUTION:A trap 1.13 is formed by a series connection comprising an inductance L1.15 and a capacitor C1.16. Moreover, a trap 2.14 is constituted by an inductor L2.17 and a capacitor C2.18 and it is inserted between a control signal line 10 and earth. In the trap as above, in selecting the constant L1.L2.C1.C2 is adjusted as equations I, II, then the impedance is much decreased in the vicinity of two points of fA, that is, fref, fB, that is, 2Xfref, then the attenuation is much increased. Thus, most parts of the primary and secondary side band spurious radiation is eliminated by the traps 13, 14 and the level is suppressed to a level without no problem.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a phase-locked loop circuit that can greatly increase the side pant spurious suppression effect and improve the C/N ratio, or as an application thereof. The invention relates to a frequency synthesizer.

BACKGROUND OF THE INVENTION In recent years, in radio communications such as satellite communications, mobile communication terminals, and amateur radio, phase locked loops (Phasia Locked Loops) are used to perform up-down conversion or to select channels for transmission and reception.
A circuit (referred to as LI) or a frequency synthesizer has become indispensable. In the future, the frequency band per channel will tend to become narrower in order to effectively utilize the limited frequency range in response to the increasing demand for radio waves.
Disturbance and interference with adjacent channels is likely to occur. Therefore, the PLL has high signal purity, low noise components such as sideband spurious, and good C/H.
Circuits and frequency synthesizers are required.

The conventional technology will be explained below. Figure 7 shows the conventional P
FIG. 2 is a block diagram of an LL circuit. 1 in the figure is V 00 (V
oltage Controlled 0scillat
or: Voltage controlled oscillator (hereinafter referred to as VOC), 2 is V
This is four, which is the output frequency of CO.1, that is, the output frequency of this PLL circuit. 3 is a frequency divider four2
It has a function of dividing the frequency by N to obtain the frequency f1·4.

Here, N is of course a positive integer. Reference numeral 5 denotes a reference frequency oscillator, which is usually obtained by using a crystal oscillator as the source oscillation and frequency-dividing it as necessary. 6 is the reference frequency frev which is its output. A phase comparator 7 compares the phases or frequencies of two input signals, fl.4 and fret.6, and outputs an error signal 8. Reference numeral 9 denotes a low-pass filter which converts the error signal 8 into a low-frequency p-wave to obtain a control signal 7.1o, which is a DC signal, and feeds it back to t-Vco.1 to form a closed circuit. PL like this
In the L circuit, vCo・1 so that L=frer
is controlled, so it is well known that foσr=”fret.Here, if Nt- is fixed, f, υ
A fixed PLL circuit (PLL oscillator).

On the other hand, if N is varied, four can also be varied accordingly, so it functions as a frequency synthesizer. In other words, a frequency synthesizer can be considered as an application of a PLL circuit.

In this simple PLL circuit, the control signal 7.1° is ideally a perfect DC voltage, but in reality it contains frequency components synchronized with the reference frequency fref included in the error signal 8 and its harmonics. The component leaks through the low-pass filter 9 and is superimposed on the control signal 1o as a ripple. In addition, the noise radiated from the signal line of the reference frequency fret・6 or the divided frequency f,・4 (frequency is equal to fret) may still be mixed into the control signal 10, or even be transmitted through the power supply or ground line. Noise is mixed into the control signal 1o through the low-pass filter. Through these various paths, the reference frequency fref and its harmonic components appear as noise as sideband spurious near the center frequency (carrier>fa) of the output four of this PLL circuit.

FIG. 8 shows a frequency spectrum waveform of the output frequency foute, with the center frequency (carrier 11) f.

Sideband spurious 12 (noise) on both sides near
It shows that is appearing. The higher the level of the sideband spurious 12, the lower the O/N and the greater the interference with adjacent channels, so it is desirable to reduce it. For example, 800MHz
The spurious suppression ratio for mobile communication terminals using broadband is -60.
It is necessary to set it to -7CXlBO or more. However, in the above example, since the channel spacing is 30 KHz, fret will inevitably be less than 30 KHz, and the sideband spurious 12 will be very close to the carrier 11. In such a case, as can be seen from FIG.
The phase noise is superimposed on the base of the phase noise of
2) becomes difficult.

Problems to be Solved by the Invention In such conventional examples, in order to reduce sideband spurious, an extremely large capacitor with good high frequency characteristics is added to the control signal line for ripple removal, and each circuit is It was necessary to introduce a strict shield in between, which caused the problem that paper cartons became larger and more expensive. Additionally, the addition of a large capacitance capacitor to the control signal line as described above may result in longer channel switching times, larger overshoots, or oscillations in the voltage of the control signal line. New problems arise, such as broadening the frequency of the carrier and increasing phase noise, so capacitors can only be added to the extent that these do not become a problem. Therefore, the sideband spurious remains to some extent, and as a result, there is a possibility of causing interference with adjacent channels, resulting in a reduction in the transmission error rate and generation of mixed sounds and noise.

Means for Solving the Problems In order to solve these problems, in the present invention, a trap is added to the control signal line as a means for removing at least one of the ripples of fref and its harmonic components. This is a reduction of

As a result, with the addition of only a few components, the sideband spurious suppression effect is extremely excellent, there is little interference between adjacent channels, the transmission error rate is low in data transmission systems, and the interference and noise is reduced in voice transmission systems.
A PLL circuit that can reduce noise can be provided.

Embodiment FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention. In the figure, 1 is the output frequency of vCO12/vco・1, that is, the output frequency of this PLL circuit fou
r, 3 is a frequency divider, 4 is a divided frequency f, 6 is a reference frequency oscillator, 6 is a reference frequency fr6f, 7 is a phase comparator, 8 is an error signal, 9 is a low-pass filter, 10 is a control signal V The above is the same as the conventional example.

13 is a first trap, 14 is a second trap,
Both are connected to control signal line /10. The basic operation of such PI and L circuits is also the same as that described in the conventional example, and four=k''fref.

FIG. 2 shows the frequency characteristics of the impedance of the control signal line 10 according to the embodiment shown in FIG. The impedance near frequency 0, that is, direct current, depends on the output circuit of the low-pass filter 9 and the input circuit of vCo·1, but is a relatively large value. As the frequency becomes higher, the impedance decreases due to the influence of the low-pass filter 9 and other directly or parasitically added capacitors. As can be clearly seen from the figure, the impedance rapidly decreases in a concave manner around the frequencies fret and 2×fr0f, and becomes almost 0 at the center frequencies CIA and fB. Due to the effect of

Figure 3 is a circuit diagram of trap 13 and trap 21140, with inductance L1.15 and capacitor C1.16.
A trap 13 is constructed by connecting the inductance L2.17 in series with the capacitor G2.18, and a trap 2.14 is constructed by the series connection of the inductance L2.17 and the capacitor G2.18, which are inserted between the control signal line 1o and the ground. This is a basic L(j) wrap. In such a trap, L is set so that b=1/2πfi=fref f, =1/2πl; [=2×fre, f
By adjusting l, Ll, G1, and G2 respectively, it is possible to make the impedance extremely small, that is, the attenuation amount extremely large, in the vicinity of the two points 8, fret, and fB, 2×fr6f.

FIG. 4 is a frequency spectrum waveform of the output frequency of a PLL circuit according to an embodiment of the present invention. Career 1 after all
Sideband spurious waves 20 appear on both sides near 9, but at frequencies fO±fret and f. ±2Xhjst
It can be seen that the spurious level at is extremely low. The higher-order spurious of fo±3×fret or higher is approximately at the same level as the conventional example. It should be noted that even though traps 13 and 14 are included, the −th order, that is, f. -! :fre, sideband spurs of f and quadratic or f. ±2X
The reason why the sideband spurious of fre and f is not completely removed is that it is caused by
Alternatively, this is because the radiation radiated from the fref and f signal lines directly mixes into vCO. but,
As mentioned above, its level is smaller than that mixed into the control signal line, so the trap 13 and trap 14 can remove the main part of the primary and secondary sideband spurious, and this is usually a level that does not pose a problem. can be suppressed.

Regarding high-order sideband spurious of third order or higher,
Generally, it only appears at a small level and can be ignored. Therefore, the number of traps to be added is usually one or two.

FIG. 6 is a modification of the trap (only one shown, LC in FIG. 3) wrap according to the second embodiment.

FIG. 6 shows a trap according to a third embodiment (also only one is shown), which is called a bridge trap. In such a trap, a low-pass filter and a vC
Although an inductance is inserted by interrupting the control signal line between O and O, there is no problem because the signal that must be transmitted through the control signal line is only a DC component.

Although other trap embodiments are conceivable, they all have the same function of removing fret and its harmonic components mixed into the control signal line.

The values that can be taken for the inductance and capacitor are generally those prepared as standard products, so the values are discrete. Although it may not exactly match '12 x fret, a certain amount of attenuation can be obtained by fanning at a close frequency. For example, in the trap shown in Figure 3, fr6(#1/2π4 2 /2 W u.

Furthermore, the first. Since the power consumption of the second trap 13.14 is very small, cheap and small parts such as chip capacitors and chip coils can be used, which makes the equipment expensive and large. There's nothing to do. It is also desirable to provide these first and second traps 13 and 14 as close to vCol as possible; in this case, the first trap 13 is placed closer to VCo1 than 14.

Further, it is preferable that the traps 13 and 14 of N1 are arranged in a direction perpendicular to each other to prevent interference.

In addition, although a trap was used in the above explanation, if it selectively attenuates /ref and its harmonic components,
Of course, anything is fine.

With the simple configuration described above, the sideband spurious level, which is a very important characteristic for a PLL circuit or a frequency synthesizer, can be made extremely small. Therefore, interference with adjacent channels is substantially eliminated, which contributes to reducing transmission error rates in data transmission systems and to reducing interference and noise in audio transmission systems.

In addition, there is no need to add an expensive, large-capacity capacitor with good high-frequency characteristics to the control signal line as in the past, which would result in an increase in channel switching time, overshoot, and phase noise. There are no problems such as an increase in the carrier frequency or a spread in the carrier frequency. Also,
Shielding between circuits does not have to be very strict, and the number of circuits that need to be added is very small, so in addition to the above points, it is possible to make the device smaller and lower in price while improving characteristics. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention, FIG. 2 is a frequency characteristic diagram of I/P/S of a control signal line in a PLL circuit according to an embodiment of the present invention, and FIG. A circuit diagram of a first example of a trap according to an embodiment of the invention, FIG. 4 is a frequency spectrum waveform diagram of an output frequency of a PLL circuit according to an embodiment of the invention, and FIG. 6 is a circuit diagram of a first example of a trap according to an embodiment of the invention. FIG. 6 is a circuit diagram of a third example of a trap according to an embodiment of the present invention;
FIG. 7 is a block diagram of a conventional PLL circuit, and FIG. 8 is a frequency spectrum waveform diagram of the output frequency of the conventional PLL circuit. 1... VCo, 3... Frequency divider, 6...
...Reference frequency oscillator, 6...Reference frequency, 7...Phase comparator, 9...Low pass filter, 1o...Control signal, 11 @19...
...Carrier, 12II20...Sideband spurious, 13-14...Trap, 1
5-17... Inductance, 16e18...
...Capacitor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 J Figure 4 Figure 5 Figure 7! Figure 8 Shuhiro

Claims (1)

[Claims] Either the output signal of the reference frequency oscillator or the signal obtained by dividing the output signal of the reference frequency oscillator is used as the reference frequency signal, and the phase of the signal obtained by dividing the output signal of the voltage controlled oscillator and the reference frequency signal is set as the reference frequency signal. The comparator performs a phase comparison, and the obtained error signal is filtered by a low-pass filter and fed back to the control signal line of the voltage controlled oscillator to form a closed circuit. A phase-locked loop circuit connected to at least one circuit means for selectively attenuating at least one frequency component among the frequency of a frequency signal or a frequency that is approximately an integral multiple of the frequency of the reference frequency signal.