JPS63163655A - Interruption processor - Google Patents
Interruption processorInfo
- Publication number
- JPS63163655A JPS63163655A JP31082986A JP31082986A JPS63163655A JP S63163655 A JPS63163655 A JP S63163655A JP 31082986 A JP31082986 A JP 31082986A JP 31082986 A JP31082986 A JP 31082986A JP S63163655 A JPS63163655 A JP S63163655A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- binary counter
- address
- data
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はマイクロコンピュータの割り込み処理装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an interrupt processing device for a microcomputer.
（従来例）
従来この種の割り込み処理方式に於いては、μｍＣ０Ｍ
への割り込みの数が複数の場合、μｍＣ０Ｍへの一つの
割り込み入力に複数の割り込み要因をＯＲＬ、て入力し
ていた。その為、割り込みの要因がどれであるかをソフ
トのポーリングにより識別することになる。その為、時
間を資す欠点があった。(Conventional Example) Conventionally, in this type of interrupt processing method, μmC0M
When there are multiple interrupts to μmC0M, multiple interrupt factors are input to one interrupt input to μmC0M using ORL. Therefore, the cause of the interrupt must be identified by software polling. Therefore, there was a drawback that it was time consuming.
又μｍＣ０Ｍの周辺チップとして割り込みコントローラ
が市販されているが、それらはせいぜい８人力であり、
それ以上の割り込み人力の場合はソフト、ハードの負荷
が大となった。Also, interrupt controllers are commercially available as peripheral chips for μmC0M, but they require at most eight people to operate.
In the case of more manual interrupts than that, the load on software and hardware would be heavy.
（目 的）
本発明の目的は上述従来例の欠点を除去するとともにマ
イクロコンピュータにかかる負荷を軽減することにある
。(Objective) The object of the present invention is to eliminate the drawbacks of the above-mentioned conventional example and to reduce the load placed on the microcomputer.
（実施例）
以下図面を参照して本発明の一実施例を詳細に説明する
。(Example) An example of the present invention will be described in detail below with reference to the drawings.
第１図は本実施例の構成を示した図であり、尚、第１図
では３２本の割り込み人力が有る場合を示す、、１はマ
イクロコンピュータ（μｍＣ０Ｍ）、２はプログラムが
格納されているＲＯＭ、３．４，５．６は各々割り込み
人力の８木のうち１木を出力する為のセレクター、７は
５ｂｉｔｓのバイナリカウンタである。Fig. 1 is a diagram showing the configuration of this embodiment. Fig. 1 shows the case where there are 32 interrupts. 1 is a microcomputer (μmC0M), 2 is a program stored therein. ROMs 3.4 and 5.6 are selectors for outputting one of the 8 interrupt trees, respectively, and 7 is a 5-bit binary counter.
８はμｍＣ０Ｍ １がベクターアドレスをアクセスに行
った時にゲートを開くトライステートバッファである。8 is a tri-state buffer whose gate is opened when μmC0M1 accesses a vector address.
つぎに上記構成に於いて、今セレクター３のＤ１人力に
割り込みが発生したとすると、μｍＣ０Ｍ１への割り込
み線は５ｂｉｔｓのパイナリカウンタフの値が１０００
０ （ＱＡ 、Ｑａ 。Next, in the above configuration, if an interrupt occurs in D1 of selector 3, the interrupt line to μmC0M1 has a 5-bit pinary counter value of 1000.
0 (QA, Qa.
ＱＣ，ＱＤ、ＱＣの順）のときのみにアクティブ（Ｌ”
レベル）となる。その後バイナリカウンタ７は出力ＱＡ
〜、は保持される。Active (L”) only when QC, QD, QC
level). After that, binary counter 7 outputs QA
~, is retained.
次にμｍＣＯＭＩは割り込み線を識別し、飛び先番地の
格納されているベクタアドレスのデータを読み出しに行
く。この時トライステートバッファ８がイネーブルとな
り読み出しデータとして該バイナリカウンタの出力ＱＡ
〜、を読み出し、そのデータに基づいたアドレスヘジャ
ンプし割り込み処理を実行する。Next, μmCOMI identifies the interrupt line and goes to read the data at the vector address where the jump destination address is stored. At this time, the tri-state buffer 8 is enabled and the output QA of the binary counter is read as read data.
..., jumps to the address based on the data, and executes interrupt processing.
以上説明したよう・に本実施例によれば、セレクタ、バ
イナリカウンタにより複数の割り込みを１木にし、ベク
ター・アドレスの内容をバイナリカウンタの値とする事
により、容易かつ安価に複数の割り込みを処理でき、μ
ｍＣ０Ｍの処理時間が最短にできる。As explained above, according to this embodiment, multiple interrupts are combined into one tree using a selector and a binary counter, and multiple interrupts are processed easily and inexpensively by using the contents of the vector address as the value of the binary counter. Possible, μ
mC0M processing time can be minimized.
尚、本実施例はマイクロコンピュータによりデータの処
理又は各種動作機器の制御を行う場合に適用することが
できる。Note that this embodiment can be applied to cases where a microcomputer processes data or controls various operating devices.
〔効 果）
以上の様に本発明によって割り込み処理時のマイクロコ
ンピュータにかかる負荷を軽減することが出来る。[Effects] As described above, according to the present invention, the load placed on the microcomputer during interrupt processing can be reduced.
第１図は本実施例の構成を示した図である。
１はμｍＣ０Ｍ、２はＲＯＭ、３，４，５゜６はセレク
タ、７は５ｂ ｔ ｔｓカウンタ、８はトライステート
バッファである。FIG. 1 is a diagram showing the configuration of this embodiment. 1 is μmC0M, 2 is ROM, 3, 4, 5° 6 is a selector, 7 is a 5b t ts counter, and 8 is a tristate buffer.
Claims (1)
する手段と、上記出力手段への割り込みの入力を選択す
る為の選択手段を有し、上記出力手段の割り込み信号が
イネーブルになった時に上記選択手段の出力を保持し、
マイクロコンピュータの所定アドレスとして上記選択手
段の出力値を与える事を特徴とした割り込み処理装置。It has means for inputting a plurality of interrupts and outputting them as one interrupt signal, and selection means for selecting the input of the interrupt to the output means, and when the interrupt signal of the output means is enabled, the selection means holds the output of
An interrupt processing device characterized in that the output value of the selection means is given as a predetermined address of a microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31082986A JPS63163655A (en) | 1986-12-26 | 1986-12-26 | Interruption processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31082986A JPS63163655A (en) | 1986-12-26 | 1986-12-26 | Interruption processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63163655A true JPS63163655A (en) | 1988-07-07 |
Family
ID=18009904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31082986A Pending JPS63163655A (en) | 1986-12-26 | 1986-12-26 | Interruption processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63163655A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58109958A (en) * | 1981-12-23 | 1983-06-30 | Hitachi Ltd | Transmission controller in function decentralizing system |
-
1986
- 1986-12-26 JP JP31082986A patent/JPS63163655A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58109958A (en) * | 1981-12-23 | 1983-06-30 | Hitachi Ltd | Transmission controller in function decentralizing system |
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