JPS631622B2 - - Google Patents

Info

Publication number
JPS631622B2
JPS631622B2 JP57121595A JP12159582A JPS631622B2 JP S631622 B2 JPS631622 B2 JP S631622B2 JP 57121595 A JP57121595 A JP 57121595A JP 12159582 A JP12159582 A JP 12159582A JP S631622 B2 JPS631622 B2 JP S631622B2
Authority
JP
Japan
Prior art keywords
circuit
page
addition
subtraction
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57121595A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5911451A (ja
Inventor
Teruaki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57121595A priority Critical patent/JPS5911451A/ja
Publication of JPS5911451A publication Critical patent/JPS5911451A/ja
Publication of JPS631622B2 publication Critical patent/JPS631622B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP57121595A 1982-07-13 1982-07-13 分岐制御方式 Granted JPS5911451A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57121595A JPS5911451A (ja) 1982-07-13 1982-07-13 分岐制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57121595A JPS5911451A (ja) 1982-07-13 1982-07-13 分岐制御方式

Publications (2)

Publication Number Publication Date
JPS5911451A JPS5911451A (ja) 1984-01-21
JPS631622B2 true JPS631622B2 (cg-RX-API-DMAC10.html) 1988-01-13

Family

ID=14815139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57121595A Granted JPS5911451A (ja) 1982-07-13 1982-07-13 分岐制御方式

Country Status (1)

Country Link
JP (1) JPS5911451A (cg-RX-API-DMAC10.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2026201A1 (en) * 2007-08-10 2009-02-18 Cortus S.A. Processor branch instruction encoding

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5788244U (cg-RX-API-DMAC10.html) * 1980-11-19 1982-05-31
JPS57193841A (en) * 1981-05-22 1982-11-29 Hitachi Ltd Program counter circuit

Also Published As

Publication number Publication date
JPS5911451A (ja) 1984-01-21

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