JPS63161670A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize an ultra high speed operation, by injecting minority carriers from an emitter layer to a base layer and making them receive a filter action in an emitter resonance layer so as to make uniform their high energy. CONSTITUTION:A n<+>GaAs collector layer 2, a P<+>-GaAs base layer 3, an undoped resonance layer 8 comprising three AlAs emitter barrier layers and two GaAs emitter well layers, and a n<->Al0.2Ga0.8As emitter layer 4 are made to grow serially on a n<+>-GaAs substrate 1. An emitter electrode 7 is formed by evaporating AuGe/Au on a surface of the emitter layer 4 and then by alloying. A base electrode 6 is formed by etching/removing the emitter layer 4 and the emitter resonance layer 8 which are on the base electrode part, and next by evaporation of AuZn/Au. A collector electrode 5 is made of In. In a hetero junction bipolar transistor HBT formed by this manufacturing method, 30 ps is obtained as a delay time per one stage of transistor. Hence, a base delay time is much decreased so that an ultra high speed operation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device capable of high-speed operation.

(Prior Art) One of the active semiconductor devices considered to be capable of high-speed operation is a terojunction bipolar transistor (HBT') having a wide bandgap emitter (WGE).

For example, International Ellen I. Ron Device Meeting (IEDM, Technical Digest, St.) by Asbeck et al.

629 pages, 1981), a prototype of HB'r was reported. This device: (1) can significantly reduce the pace resistance and narrow the base width without degrading the emitter injection efficiency;

(21) Since the impurity concentration in the emitter region can be reduced, the emitter-base capacitance can be reduced.

Because of this advantage, it is more suitable for high-speed operation than ordinary bipolar transistors made only of homojunctions.

FIG. 6 shows a schematic cross-sectional view of a bipolar transistor with a conventional structure. In FIG. 6, 1 is a semiconductor substrate, 2 is a collector layer having one conductivity type and made of a first semiconductor, 3 is a base layer having a conductivity type different from collector layer 2 and is made of a first semiconductor, and 4 is a collector layer made of a first semiconductor. an emitter layer made of a second semiconductor having the same conductivity type as the collector layer 2 and having a wider forbidden IF band width than the collector layer 2 and the base layer 3; 5 a collector electrode forming ohmic contact with the substrate 1 and the collector layer 2; 6 is a base electrode that forms ohmic contact with the base 3, and 7 is an emitter electrode that forms ohmic contact with the emitter layer 4.

The operation of this conventional structure is performed using n''-GaAs with a donor concentration of approximately I x 1018c+m-' as the semiconductor substrate 1;
Donor concentration as collector layer 2 is I x 10”C1)
n--GaAs with an acceptor concentration of about -', and p''-Ga with an acceptor concentration of about 1 x 1019 cm-3 as the base layer 3.
As, emitter layer 4 with donor concentration of 5 x 10
This will be explained using FIG. 7, which shows this band structure, using n-8L0.2GaO, RAS of about c+s-3.

FIG. 7 schematically shows a band structure spanning the emitter layer 4, base layer 3, and collector layer 2 shown in FIG.

In Figure 7, Ec is the conduction band width, Ev is the filling band width, and Ef
is the Fermi level, Web is the emitter-base voltage,
Vbc is the voltage between base and collector.

A forward bias of Veb is applied between the emitter and the base,
When a reverse bias of Vbc is applied between the base and collector, electrons are injected from the emitter to the base by diffusion.
Most of these electrons diffuse through the base layer and move toward the collector, are accelerated by the strong electric field in the depletion layer between the base and collector, and reach the collector. Since the amount of electrons injected from the emitter to the base varies depending on the web, the collector current is controlled by the base voltage. In a bipolar transistor that has only a normal homojunction, when electrons are injected from the emitter to the base, holes are injected from the base to the emitter, so the emitter injection efficiency (ratio of electron current to emitter current) decreases. However, in HBT, there is A Q 1) between the emitter and base. 2Ga08
Because of the presence of the As/GaAs heterointerface, there is a barrier of about 100 meV against holes when looking from the base side to the emitter side, and the injection of holes from the base to the emitter vines is suppressed. Therefore, the hole concentration in the base can be increased and the emitter electron concentration can be kept low to some extent without reducing the emitter injection efficiency. As a result, a structure suitable for high-speed operation with low base resistance, low emitter-base capacitance, and narrow base width can be obtained.

(Problems to be solved by the invention) However, although the conventional HBT has the above-mentioned advantages, sufficient speed-up has not been achieved because there are still elements that hinder speed-up. do not have. One of the factors that hinders speeding up is the structure of the base. As a result of containing a high concentration of impurities, the migration speed of minority carriers decreases due to impurity scattering, and the lifetime of minority carriers decreases due to an increase in recombination centers. Also,
Since minority carriers move within the base by diffusion, the base transit time increases as the temperature decreases, and the operating speed at low temperatures is slow.

An object of the present invention is to eliminate the drawbacks of conventional IBTs and to provide a semiconductor device capable of ultra-high-speed operation.

(Means for Solving the Problem) The semiconductor device of the present invention has a collector layer made of a semiconductor having one conductivity type, a base layer made of a semiconductor having a conductivity type different from the collector layer, and carriers escape through the tunneling effect. a high-purity emitter resonance layer having a laminated structure of an emitter barrier layer with a thickness of It is characterized by having a structure in which an emitter layer made of a semiconductor with a large forbidden band width is stacked. At this time, when the emitter layer is an n-type semiconductor, the conduction band edge energy of the emitter barrier layer is higher than the conduction band edge energy of the emitter well layer and the base layer, and when the emitter layer is a p-type semiconductor, the emitter barrier layer has a higher conduction band edge energy than the emitter well layer and the base layer. The band edge energy of the barrier layer is lower than the band edge energies of the emitter well layer and the base layer.

(Function) In the semiconductor device of the present invention, the minority carriers injected from the emitter layer to the base layer pass through the base layer at high speed because they are filtered in the emitter resonance layer and have uniform energy. This enables ultra-high-speed operation. Furthermore, by utilizing the negative resistance of the emitter resonance layer, it is also possible to use it as a functional device.

(Examples) Hereinafter, the present invention will be described in detail with reference to drawings showing examples.

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention. Components in FIG. 1 with the same numbers as in FIG. 6 are equivalent to those in FIG. 6 and perform the same functions. Reference numeral 8 denotes a high-purity emitter/vine resonance layer having a laminated structure of an emitter barrier layer 21 and an emitter well layer 22. As an example of each layer in the first embodiment, the emitter resonance layer 8 is made up of three undoped flAs emitter barrier layers 21 with a thickness of 40λ and two undoped GaAs emitter well layers 22 with a thickness of 20λ. However, the rest is the same as the conventional example described above.

The difference in operation of this first embodiment from the conventional example will be explained using the above-mentioned materials and using FIG. 2 showing the band structure.

FIG. 2 shows a schematic band structure spanning the emitter layer 4, emitter resonance layer 8, base layer 3, and collector layer 2 shown in FIG. ΔEceb is the difference between the resonance level in the emitter resonance layer 8 and the conduction band edge energy of the base layer 3, Δ
Ecee is the resonance level in the emitter resonance layer and the emitter layer 4
is the difference between the conduction band edge energy and the conduction band edge energy. In the emitter resonance layer, electrons with energy at the resonance level can pass through, but other electrons cannot.

When a forward voltage Web is applied between the emitter and base,
Electrons tend to flow from the emitter to the base by diffusion. However, while Veb is small, injection does not occur due to the existence of a barrier of ΔEcee. When Web becomes sufficiently large and ΔEcee becomes small, electrons begin to flow into the base. Since the electrons injected into the base have energy greater than ΔEceb, they can escape through the base at high speed as hot electrons. Even in conventional structures, electrons are injected with extra energy due to the presence of spikes between the emitter and base, but electrons can easily pass through these spikes through the tunnel effect even when Veb is small, resulting in a large amount of energy. It could not be a hot electron.

Now, in the structure of the present invention, most of the electrons injected from the emitter are hot (at an energy position higher than the conduction band edge), so the probability of capture to the recombination center is reduced, and the minority carrier lifetime is The decrease can also be suppressed.

As described above, according to the structure of the present invention, even though the impurity concentration of the base is high, the base transit time can be shortened and the decrease in the minority carrier lifetime can be suppressed. As a result, it has a high current amplification factor and can operate at ultra high speed.

Now, if Web is increased so that ΔEcee becomes negative, electrons will no longer be able to move through the resonance level. As a result, the base and collector currents decrease,
Negative resistance appears. Therefore, in addition to increasing the speed, it can also be used as a functional debugger having an exclusive non-OR (XNOR) function using one transistor, for example.

Next, a manufacturing method of the first embodiment described above will be explained. The crystal growth method is M[]E (Mo1ecuf
ar Beam Epitaxy), n”-Ga
On the As substrate 1 with a thickness of 0.5 μm and a donor concentration of lXl0
"cm" n-GaAs collector layer 2, P"-Ga with a thickness of 500 λ and an acceptor concentration of 2 x 10" cm
A5 base layer 3. Consisting of three 40λ'' ALAs barrier layers and two 20λ GaAs engineered barrier layers - 160 nm thick anddove emitter resonant layer 8, donor concentration 5 x 10" cLl-3 and thickness 0. 5,4c
n-^Q 1), 2 Gag, and gAs emitter layers 4 of rn were sequentially grown. Emitter electrode 7 is emitter layer 4
AuGe/Au is deposited and then alloyed on the surface, and the base electrode 6 is formed by removing the emitter layer 4 and emitter resonance layer 8 in the base electrode part by etching.
+1 was formed by vapor deposition. The collector electrode 5 was made of In. In the HBT manufactured by this manufacturing method, a delay time of 30 ρS per transistor stage was obtained.

FIG. 3 is a schematic diagram of the band structure of the second embodiment of the present invention. In Figure 3, items with the same numbers as in Figure 2 are
It is equivalent to a diagram and performs the same function. 9 is a graded base layer in which the forbidden band width gradually widens from the collector layer side to the emitter layer side.

The operation of this second embodiment is almost the same as that of the first embodiment, but the adoption of a graded base allows for even higher speed operation.

Since the graded base layer 9 is of P type, the difference in the forbidden band appears as a difference in the energy of the conduction band.

Therefore, for electrons, there is a potential difference corresponding to the difference in forbidden band width, and the electrons are accelerated by the internal electric field within the base. With the above material, the graded base layer 9 is changed from P”-GaAs to P”-A Q O,
If it changes to 1caO, gAs, the potential difference will be about 0.12V.

Further, if the thickness of the graded base layer is 1000λ, an electric field of 12 KV will be applied. Therefore, electrons injected from the emitter layer 4 to the graded base layer 9 are first affected by the difference ΔEcee between the resonance level of the emitter resonance layer 8 and the conduction band edge of the graded base layer 8 (approximately 0.2V for the above material). ) and further accelerated by the electric field in the graded base. As a result, the first
The base running time is also shortened by this embodiment.

The graded base layer 9 is made of GaAs with a thickness of 500λ from the collector layer side to the emitter barrier layer side.
look. , IGag, P' gradually changing to gAs
-AQXGal-gAs (P=2 X 1019C1
1-'), and the rest was the same as in the first embodiment.
As a result, a delay time of 25 ps was obtained per transistor stage.

In the first and second embodiments of the present invention described above, npn
Although only a type of HOT is shown, it is clear that the present invention is equally applicable to a pnp type semiconductor having the opposite conductivity type.

FIG. 4 is a schematic band structure diagram of a third embodiment of the present invention, in which the conductivity type of the first embodiment is reversed.

In FIG. 4, the same numbers as in FIG. 2 indicate materials with opposite conductivity types. ΔEveb is the difference in filling band edge energy between the base layer 3 and the emitter resonance layer 8, and ΔEvee is the difference in filling band edge energy between the emitter resonance layer 8 and the emitter layer 4. The operation of this embodiment differs only in that the carriers are holes.
This is similar to the embodiment. A delay time of 35 ps was obtained using the same materials and structure as in the first embodiment with the conductivity type reversed.

FIG. 5 is a schematic band structure diagram of a fourth embodiment of the present invention, in which the conductivity type of the second embodiment is reversed.

A delay time of 30 ps was obtained using the same materials and structure as in the second example in which the conductivity type was reversed.

As described above, the present invention provides npn and pnp type H
It is clear that it can be applied to BT. Although the emitter layer 4 has only a constant forbidden band width, it may be a graded emitter that gradually increases in width from the emitter barrier layer side. The forbidden width of the collector layer may also be larger than that of the base layer 3. Although only a triple barrier layer is shown as the Emi-ivy resonance layer, a double barrier layer, a quadruple barrier layer or more may be used. As for the element structure,
In addition to the mesa type, it may be a planar type using ion implantation or regrowth, or it may be a type in which the growth order of each layer is reversed and the collector layer is formed on the surface side. In addition, the growth of each layer was shown to be by MBE method, but by MOCVD method.
(Metal Organic Chemical
Other growth methods such as VaporDeposition, vapor phase growth, and liquid phase growth may also be used.

As a semiconductor, GaAs/A Q GaAs system was not shown, but GaAs/In using GaAs similarly
GaAsP/InGaP system and electron saturation velocity
InGaAs/using 1nGaAs which is larger than As
InGaA Q As/InA Q As system, InGa
As/InGaAsP/InP system, GaSb/A
Q I-V compound semiconductors such as GaSb/Au5b,
Elemental semiconductors such as Ge/5iGe/Si, CdTe/C
It is clear that the present invention can also be applied to 1-2 compound semiconductors such as dZnTe/ZnTe series and other various semiconductors. In addition, the materials shown above are combinations with almost the same lattice constant, but materials with different lattice constants and distortion (for example, InGaAs/InA Q
The present invention is also applicable to GaAs/A Q GaAs system).

(Effects of the Invention) The semiconductor device of the present invention significantly reduces the base delay time and enables ultra high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view of the first embodiment of the present invention, FIG. 2 is a band structure diagram thereof, FIGS. 3 to 5 are band structure diagrams of second to fourth embodiments, and FIG. The figure is a schematic cross-sectional view of a conventional heterojunction bipolar transistor, and FIG. 7 is a diagram of its band structure. 1...Semiconductor substrate 2...Collector layer 3...Base layer 4...Emitter layer 5...Collector electrode 6...Base electrode 7...Emitter electrode 8...Emitter resonance layer 9 ...Pre-dirad base layer Ec...Conduction band edge Ev...Full band edge Ef...Fermi level Web...Emitter-base voltage Vbc...Base-collector voltage ΔEb... Forbidden band width difference Δ in graded base layer
Eceb...Difference between the resonance level in the emitter resonance layer and the conduction band edge of the base ΔEcee...Difference between the resonance level in the emitter resonance layer and the conduction band edge of the emitter ΔEveb...In the emitter resonance layer Difference ΔEvee between the resonance level of and the edge of the filled band of the base... Resonance level in the emitter resonance layer and emitter Figure 1 Figure 2 Figure 3 Figure 5

Claims (3)

[Claims] (1) A collector layer made of a semiconductor having one conductivity type, a base layer made of a semiconductor having a conductivity type different from the collector layer, an emitter barrier layer having a thickness that allows carriers to escape by tunneling effect, and the de Broglie wavelength of the carriers. A high-purity emitter resonant layer having a laminated structure with an emitter well layer having a thickness of A semiconductor device characterized by having a structure. (2) The semiconductor device according to claim (1), wherein the emitter layer is an n-type semiconductor, and the conduction band edge energy of the emitter barrier layer is higher than the conduction band edge energies of the emitter well layer and the base layer. (3) The semiconductor device according to claim (1), wherein the emitter layer is a P-type semiconductor, and the emitter barrier layer has a filling band edge energy lower than that of the emitter well layer and the base layer.