JPS63161644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve adhesive properties with a protective film formed onto a wiring and an inter-layer insulating film, and to shape the film, in which the insulating film is not peeled and floated, easily even on the wiring in wide wiring width by forming an irregular section to the surface of the Au plating wiring. CONSTITUTION:A metallic thin-film 2 such as Ti/Au is shaped onto a substrate 1. A desired wiring pattern 4 is formed by a punching pattern from a photo- resist 3, and Au is shaped into the wiring pattern 4 through electroplating. An irregular section 6 is formed to the surface of Au plating 5 through dipping into the solution of KI:I2:H2O=5:3:80, the photo-resist 3 and the metallic thin-film 2 for a plating electrode except a wiring section are removed to shape a plating wiring 7, and a surface protective film 8 such as SiO2 is formed in 8000Angstrom . The irregular section is shaped to the surface of the plating wiring 7, thus improving adhesive properties with the surface protective film.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming wiring thereof.

2. Description of the Related Art In recent years, Ga and As have attracted attention as high-speed devices that can replace Si. GaAs has an electron mobility of 6 compared to SL.
It is possible to obtain ~6 times larger and faster devices.

As the degree of integration of devices increases, not only the high speed of the elements but also the delay due to wiring resistance becomes a big problem, so we need to reduce the wiring resistance.

It is essential to increase the thickness of the wiring. GaAs
In the IC process, wiring resistance is generally reduced by using Au-plated wiring.

FIG. 2 is a cross-sectional view of the manufacturing process for explaining the manufacturing method of 0+JJ Kintsugi using the conventional plating method. The entire surface of the substrate 11 (metal 12 that will become the plated electrode, for example, T i /A u
is formed by vapor deposition (FIG. 2(a)). Next, a desired wiring pattern is formed by punching out the photoresist 13 (FIG. 2(b)). Thereafter, Au plating 14 is selectively formed in the pattern openings of the photoresist 13 by electrolytic plating (FIG. 2 CC). Next, the photoresist 13 is removed, and the plated metal layer 4312 other than the coating pattern portion is removed by, for example, ion milling to form the Au plated wiring 16 (FIG. 2(d)).

Problems to be Solved by the Invention Generally, an insulating film such as a surface protection film or an interlayer insulation film is formed on the wiring. When an insulating film is formed on the thin Au-plated wiring shown in Figure 2, as the wiring width becomes wider, problems arise in that the insulating film on the Au is peeled off or lifted up, resulting in a decrease in reliability and two layers. There was a problem that the wiring @ line and short circuit occurred.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides that A
A step of forming a thin film of gold that will become a plating electrode,
A step of forming a desired wiring pattern as a punched pattern using a photoresist, a step of plating Au into the opening of the photoresist pattern by plating, and plating A.
The method consists of a step of forming irregularities on the U surface, a step of removing the photoresist, and a step of removing the metal thin film other than the plated wiring portion.

Effects The present invention has the above-described configuration, which makes the surface of the Au plating wiring pattern uneven, improves the adhesion between the +3V protective film or interlayer insulation film formed on the wiring, and the Au wiring, and improves the insulation on the wiring. It is possible to prevent the film from peeling off or floating.

Embodiment FIGS. 1(a) to 1(f) are schematic front views of manufacturing steps showing an embodiment of the method of manufacturing a semiconductor device of the present invention.

In Fig. 1, 1 is the substrate, 2 is gold PA7, 3 is photoresist, 4 is 6cJ pattern, 6 is Au plating,
6 is the uneven part, 7 is the mekuki moth, s j, : 4 surface stock protection membrane.

Metal thin film 2 on substrate 1? l” is T i / A u
600/1000 people (Figure 1(a)). Next, a desired symbol pattern 4 is formed as a cut-out pattern using the photoresist 3 (see Fig. 1 (3) (b)), and Au is formed inside the wiring pattern 4 by gentle plating (Fig.
)).

Next 1/-1-? ? , KI :, I, :T (2o=5
:3:8o) immersion in melting for about 6 seconds to form uneven parts 6 on the surface of the Au plating 5 (Fig. 1(d)), and then photoresist 3 and metal thin film 2 for plating electrodes other than the wiring parts. The plated wiring 7 is then removed (FIG. 1(e)).

Next, 8 layers of surface protection film and 500 layers of S 102 are formed (FIG. 1(f)).

By forming irregularities on the surface of the plating plate 7, the adhesion with the protective film on the first surface is improved. FIG. 3 compares the adhesion to the surface protective film with and without unevenness on the surface of the plated wiring, depending on the pattern width. From Figure 3, if there is no unevenness on the plated wiring surface, the pattern width is 20 μm.
If it exceeds 6, the legal theory 6 will float and the adhesion will deteriorate. 70
If it exceeds μm, peeling will occur. On the other hand, when unevenness was formed on the surface, the adhesion was good even if the pattern width was increased to about 100 μm or more.

In ``Practice of the Present Invention ν1'', the process of forming a surface protective film on the plating machine was explained, but this may be an interlayer insulating film in a multilayer arrangement H, for example.

In addition, in the present invention, formation of uneven portions on the surface of the plated wiring KK
Although the I-based solution is used, the present invention is not limited to this, and any method may be used as long as uneven portions can be formed.

Effects of the Invention As described above, according to the present invention, by forming uneven portions on the surface of the Au plating, the adhesion with the protective film and interlayer insulating film formed on the wiring is improved. , it is possible to easily form a film without peeling or floating of the insulating film even on wiring with a wide wiring width.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to 1(f) are process cross-sectional views showing a manufacturing method for a semiconductor device according to an embodiment of the present invention, and FIGS.
d) is a process sectional view showing a conventional manufacturing method, and FIG. 3 is a comparative explanatory diagram of this embodiment and a conventional example. 1...Substrate, 2...Metal thin film, 3...
... Photoresist, 4 ... Wiring pattern, 5 ... Au plating, 6 ... Concave and convex portion,
7...Plated wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person - 0
[F] Medium, ノ \, ノ , ノ [zu
Otsu

Claims (2)

[Claims] (1) A process of forming a metal thin film to become an Au plating electrode on the entire surface of the substrate, a process of forming a desired wiring pattern as a cutout pattern using a photoresist, and plating Au into the opening of the photoresist pattern by plating. A method for manufacturing a semiconductor device, comprising: a step of forming irregularities on a plated Au surface; a step of removing the photoresist; and a step of removing the metal thin film other than the plated wiring portion. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the plated Au surface is immersed in a KI-based etching solution to form irregularities on the plated Au surface.