JPS63161639A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a semiconductor integrated circuit having the high degree of integration by taking wirings among terminals set at blocking-channel ends into sections, which have not been used as wiring regions, on the insides of each block. CONSTITUTION:Terminals 5a are set at positions where the terminals enter only by the width sections of cells 4 for power supply for a block 1a and a block 1b respectively, and these terminals are wired by employing regions held by the cells for power supply. Since wiring layers different from a power line are used in the wirings, the wirings are bent freely within a range that the wirings are not in contravention of design rules among each wiring. Accordingly, the displacement of the positions of the terminals set into adjacent blocks can be absorbed in regions held by the cells for power supply in respectively cell, thus allowing wiring without employing wasteful wiring regions among the blocks.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to standard cell type semiconductor integrated circuits.

(Prior Art) In a standard cell type semiconductor integrated circuit, a large number of standard cells of multiple types, such as NAND or NOR, which are the minimum units of logic functions, are arranged in rows to form cell rows, and these cell rows are interconnected. Used as an area for wiring between standard cells as required. According to this method, the width of the channel, which is a region for wiring, is variable, and can be set as wide as necessary. Further, in order to supply power to these standard cells, dedicated cells for power supply are usually used at both ends of each cell column.

The second example is a general example of a semiconductor integrated circuit based on the standard cell method.
As shown in the figure. In this manner, a typical standard cell type semiconductor integrated circuit is comprised of a cell row 2 consisting of a row of standard cells 3, an area 7a for wiring, a power supply dedicated cell 4, and the like.

In addition, wiring is usually done using two-layer metal wiring, with separate layers being assigned to horizontal (parallel to the cell row) and vertical (perpendicular to the cell row) wiring, which connect external circuits. On the block edge composed of our standard cells for the connection of
Terminals 5 of the layer corresponding to the wiring layer are set. Power wiring 6
Similarly to general signal lines, separate layers are assigned to the horizontal and vertical directions.

On the other hand, when the scale of the circuit to be handled becomes larger, from the point of view of design efficiency, integration density, etc., a WI layered design method is generally used in which the design is divided into easily manageable circuit scales instead of handling the entire circuit at once. . In this method, the design usually proceeds in the following steps.

First, the circuit to be laid out is divided into easily manageable circuit scales, and the relative positional relationship of each circuit module is determined. Next, terminals are set on each circuit module side, taking into consideration the connection relationships between each circuit module and the connection relationships with peripheral circuits. Note that after the relative positional relationship of each circuit module is determined, the number of cell rows in each circuit module and the size of each circuit module after layout are usually estimated in advance. Place and route cells included in a circuit module according to given boundary conditions. After the placement and wiring of all the cells in the circuit module is completed and the physical shape of the block corresponding to each circuit module is determined, wiring is finally performed between blocks and between blocks and peripheral circuits. A general example of a semiconductor integrated circuit using such a method is shown in FIG. Wiring between blocks is also normally done with two-layer metal wiring, similar to intra-block wiring.1. Separate layers are assigned to horizontal and vertical wiring. Further, these wirings are performed using the wiring area 7b between each block. Reference numeral 8 in FIG. 1 represents a peripheral circuit block.

As is clear from Figure 4, which shows an enlarged part of this layout result, in the vertical wiring area sandwiched between blocks la and block 1b, there are two wiring tracks (vertical In Figure 6, which uses the number of wires (number of wires), this is just an example, but in reality, a considerable amount of wire tracks are usually required. This sets terminals on each block side during the layout planning stage, but in particular, the terminal positions set at the left and right channel ends of the block (both ends of the area used for wiring) are set using absolute coordinates. The reason is that it can only be set in a relative order relationship, and in order to eliminate the misalignment of terminal positions set on block sides to connect adjacent blocks, in the wiring area between blocks. , were forced to use these wiring trucks.

As the number of blocks used increases, the number of wiring areas between the blocks also increases, which aggravates the aforementioned problem and increases the final chip size.

(Problems to be Solved by the Invention) The present invention reduces the number of wiring tracks used to connect adjacent blocks, especially between terminals set at channel ends, unlike the conventional method described above. The purpose of this invention is to provide a standard cell type semiconductor integrated circuit with high integration.

[Structure of the invention]

(Means for Solving the Problem) In the present invention, the terminal position at the channel end of each block is located inside the block by the width of the power supply cell arranged at the end of each cell column in each block. Set to part. In this case, adjacent blocks that have a connection relationship are set at the same position as much as possible, and their relative positions are also adjusted. When connecting the corresponding terminal pair between adjacent blocks, the area sandwiched between the power supply cells placed at the end of the cell row is used to connect the terminal pair between adjacent blocks.
Wiring is performed using a wiring layer different from the wiring layer used for power supply line wiring.

(Function) According to the present invention, the area sandwiched between the power supply cells in each block can absorb the deviation of the terminal positions set inside the adjacent blocks.

It becomes possible to perform wiring without using unnecessary wiring areas between blocks.

(Example) The present invention will be described in detail below. FIG. 1 shows a part of the layout of a standard cell type semi-quadrilateral integrated circuit obtained in one embodiment, that is, the state of wiring between adjacent blocks.

Terminals 5a are set at positions that are within the width of the power supply cells 4 of blocks 1a and 1b, respectively, and the area sandwiched between the power supply cells is used to connect these terminals. Wiring is being done. Since the wiring uses a wiring layer different from that of the power supply line, the wiring can be bent freely as long as the design rules between each wiring are not violated.

In this example, terminals are set on each block side at the layout planning stage, but in this case, the terminals at the channel ends of the block are not set on the sides, but are used for power supply placed at both ends of the cell column. Set to a position that is inside the block from the side by the width of the cell.

In this case, for adjacent blocks that have a connection relationship, estimate the size of each block, set them to the same position as much as possible, and match the relative order. Next, arrange the cells in each block, Execute wiring processing.

When the layout within the block is completed, the terminal positions at the ends of each channel are also determined, so after this, the wiring between the relevant terminals is done using the area sandwiched between the power supply cells placed at the ends of the cell rows of each block. , the wiring layer used for these wirings is a different layer from the wiring layer used for the power supply line wiring, so the wiring can be bent freely as long as it does not violate the design rules between the wirings, and conventionally, The wasted wiring that occurs in the wiring area between blocks can also be absorbed in the area sandwiched between the power supply cells inside the block, making it possible to achieve high integration.

As described above, according to this embodiment, a highly integrated semiconductor integrated circuit can be obtained by incorporating the processing that was conventionally performed using the wiring area between blocks into a part of the area within the block. .

〔Effect of the invention〕

As described above, according to the present invention, high integration is achieved by incorporating wiring between terminals set at the end of a block channel into a part of each block that was not conventionally used as a wiring area. The circuit can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a part of the layout of a standard cell type semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the layout within a block, and FIG. The figure shows the layout results obtained using a one-layer design method.
Based on the conventional method. 0 is a diagram showing an example of wiring between blocks.
In fig. 1, la, Ib...block 2...cell column 3
... Cell 4 ... Power supply cell 5
．． 5a...terminal 6...power line 7a,
7b...Wiring area 8...Peripheral circuit agent Patent attorney Rule Chika Ken Yudo Takehana Toru Rein 1 Ward 2 Figure 3

Claims (2)

[Claims] (1) In a semiconductor integrated circuit that realizes a desired logic function by forming a plurality of logic cell rows each consisting of a plurality of logic cells on a semiconductor substrate and wiring each logic cell,
A power supply cell is arranged at the end of the cell column, wiring between the power supply cells is routed in a direction perpendicular to the cell column, the logic cell column group is divided into blocks, and the terminals of the block are connected. Among them, the terminal position at the channel end is set to a position that is inside the block by the width of the power supply cell placed at the end of the cell row, and the terminal position for the signal that has a connection relationship between adjacent blocks is set. A semiconductor integrated circuit characterized by being set at a position that matches a positional relationship and a sequential relationship. (2) Wiring between adjacent blocks is performed using a region sandwiched between power supply cells placed at the ends of cell rows in each block, using a wiring layer different from that of the power supply line. A semiconductor integrated circuit according to claim 1.