JPS63159846U - - Google Patents
Info
- Publication number
- JPS63159846U JPS63159846U JP5378787U JP5378787U JPS63159846U JP S63159846 U JPS63159846 U JP S63159846U JP 5378787 U JP5378787 U JP 5378787U JP 5378787 U JP5378787 U JP 5378787U JP S63159846 U JPS63159846 U JP S63159846U
- Authority
- JP
- Japan
- Prior art keywords
- base
- semiconductor
- lead frame
- lead
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 3
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体封止パツケージの一実
施例の組立前の分解斜視図、第２図は同じく一実
施例の組立後の斜視図、第３図は従来の半導体封
止パツケージの組立前の分解斜視図である。
１：ベース、２：集積回路半導体、３ａ：リー
ド端子付リードフレーム、４ａ：カバー、５：切
欠き。
Fig. 1 is an exploded perspective view of an embodiment of the semiconductor encapsulation package of the present invention before assembly, Fig. 2 is a perspective view of the same embodiment after assembly, and Fig. 3 is an assembly of a conventional semiconductor encapsulation package. It is a front exploded perspective view. 1: Base, 2: Integrated circuit semiconductor, 3a: Lead frame with lead terminal, 4a: Cover, 5: Notch.
Claims (1)
集積回路半導体と、この集積回路半導体と接続さ
れ、かつ外部配線と接続を行うリード端子付リー
ドフレームと、前記ベースの上部を覆うカバーと
を備えた半導体封止パツケージにおいて、前記リ
ード端子付リードフレームの一部を前記ベースの
上部に設けたことを特徴とする半導体封止パツケ
ージ。 (2) 前記カバーが、前記ベースの上部に設けた
リード端子付リードフレームと対向する部分に切
欠きが設けられたものである実用新案登録請求の
範囲第１項記載の半導体封止パツケージ。[Claims for Utility Model Registration] (1) A base, an integrated circuit semiconductor mounted in a recess of the base, a lead frame with lead terminals connected to the integrated circuit semiconductor and connected to external wiring, and 1. A semiconductor sealed package comprising a cover for covering an upper part of a base, wherein a part of the lead frame with lead terminals is provided on the upper part of the base. (2) The semiconductor encapsulation package according to claim 1, wherein the cover is provided with a notch in a portion facing a lead frame with lead terminals provided on the upper part of the base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5378787U JPS63159846U (en) | 1987-04-09 | 1987-04-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5378787U JPS63159846U (en) | 1987-04-09 | 1987-04-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63159846U true JPS63159846U (en) | 1988-10-19 |
Family
ID=30880174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5378787U Pending JPS63159846U (en) | 1987-04-09 | 1987-04-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63159846U (en) |
-
1987
- 1987-04-09 JP JP5378787U patent/JPS63159846U/ja active Pending