JPS63158659A - Processing speed difference adjusting interface - Google Patents

Abstract

PURPOSE:To transmit and receive data between other circuits by a high speed processing CPU by making a three-state bus driver active when is discriminated that a low speed processing CPU is selected by a chip enable signal. CONSTITUTION:When data is fed to the high speed processing CPU 10 side from the low speed processing CPU 12 side, the CPU 10 instantaneously reads it and there is an allowance in time until next data is received. At that time, the CPU 10 temporarily changes the chip enable signal to bring the three-state bus driver 30 into a high impedance state to use a data bus between other circuits. When the data is fed from the CPU 10 side to the CPU 12 side, the driver 30 is initially brought into the high impedance state and the CPU 10 can temporarily change the chip enable signal to deliver the data between other circuits.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is used, for example, in cameras to adjust processing speed differences when transmitting and receiving data between CPUs with different processing speeds. Concerning the interface.

[Background of the Invention] In recent years, the electronicization of cameras has been remarkable, and one camera is equipped with multiple one-chip microcomputers (hereinafter referred to as CP).
It's called U. ) is used.

Here, it is more convenient to keep the power on for display circuits, etc., and CMOS CP, which has low power consumption,
It is preferable to have U share in the processing.

In display circuits, etc., CPUs with slow processing speeds (low-speed processing
U ) is sufficient, and therefore power consumption can be further reduced.

On the other hand, it is necessary to use a CPU that has a relatively high processing speed (high-speed processing CI) U for controlling the entire system.

Here, the processing speed of the high-speed processing CPU is, for example, 30 times that of the low-speed processing CPU.

When transmitting and receiving data between these high-speed processing Cl) U and the low-speed processing CPU, the data is reliably transmitted and received in synchronization.

[Problem to be solved by the invention] However, for high-speed processing CPUs, the time required to send and receive each data is too long, and data cannot be sent and received with other circuits while this data is being sent and received. Processing may become difficult.

In order to avoid this, if a high-speed processing CPU is added, the hardware and software configuration will become complicated and the circuit board will become large, making it unsuitable for incorporating a camera. In addition, a high-speed processing CPU is used instead of a low-speed processing CPU.
If this method is used, the cost will be high and the power consumption will be large.

In view of the above-mentioned problems, the present invention provides that high-speed processing CI (high-speed processing CI)
The object of the present invention is to provide an interface for adjusting the processing speed difference between U and other circuits to send and receive data.

[Means for solving the problem] In the processing speed difference adjustment interface according to the present invention, in a device that transmits and receives data between a high-speed processing CPU and a low-speed processing CPU via a data bus, the input terminal is connected to the low-speed processing CPU. a three-state path driver connected to the processing CPU side and interposed in each data bus line; a signal line that supplies a chip enable signal as an interrupt signal from the high-speed processing CPU side to the low-speed processing CPU side; and the low-speed processing CPU side. A data direction control signal indicating the data transmission/reception direction is supplied from the processing CPU side, a chip enable signal is supplied from the high-speed processing CPU side, and an enable signal is supplied to the control terminal of the three-state bus driver in accordance with both signals. and a gate circuit that determines that the data transmission/reception direction is from the low-speed processing CPU side to the high-speed processing CPU side, and that the low-speed processing CPU is selected by the deep enable signal. In this case, the three-state bus driver is activated.

When transmitting and receiving data between both CPUs, an interrupt is generated from the high-speed processing CPU side to the low-speed processing CPU side using the chip enable signal. In this way, high-speed processing CPU
can start transmitting and receiving data at a time when there is relatively sufficient time.

In interrupt processing, interrupts are masked to prohibit re-interrupts.

When data is sent from the low-speed processing CPU side to the high-speed processing CPU side, the high-speed processing CPU instantly reads it,
There is plenty of time before receiving the next data. At this time, the high-speed processing CPU temporarily changes the chip enable signal to place the three-state bus driver in a high impedance state, allowing the data bus to be used with other circuits. The low-speed processing CPU can learn from changes in this chip enable signal that the high-speed processing CPU is transmitting and receiving data with other circuits.
Sending the next data is held off until the deep enable signal returns to its original state. Since the processing speed of the low-speed processing CPU is slow, this suspension may not be necessary in some cases. Even if the chip enable signal returns to its original state, the interrupt is disabled, so the low-speed processing CPU is not interrupted again and data can continue to be transmitted and received.

When data is being sent from the high-speed processing CPU side to the low-speed processing CPU side, the three-state bus driver is in a high impedance state from the beginning, and the high-speed processing CPU
The PU can send and receive data to and from other circuits by temporarily changing the chip enable signal.

The low-speed processing CPU can learn from changes in this chip enable signal that the high-speed processing CPU is transmitting and receiving data with other circuits, and if the latch is not manually operated, it may be a chip enable signal. Ignores data sent until the state is reached.

[Example] The present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, an interface 14 is interposed in the signal line connecting the CPU IO and the CPU 12.

The CPU 2 is used to control a display circuit (not shown), etc., and is constantly in operation as it is supplied with the terminal voltage VDD of the battery 16 without going through a switch. battery +
The terminal voltage VDD of No. 6 is approximately 6 volts, and gradually decreases with time.

This CPUI2 is configured with 0MO9, and its processing speed is relatively slow (for example, 1% of the processing speed of CPU10).
/30), so the power consumption is extremely low, and there is no problem even if it is kept in continuous operation. In addition, since the operating voltage range of 0MO8 is wide, even if the terminal voltage of battery I6 is directly used, CP
There is no risk of malfunction of the UI 2 itself, and a circuit (not shown) connected to the CPU 2 is selected so as to avoid the problem of malfunction.

On the other hand, the terminal voltage of the battery 16 is supplied to the switching regulator 20 via the switch I8, and a constant voltage of +5 volts is supplied from the switching regulator 20 to the CPU1.
By opening and closing switch 18, CI) Ulo is activated only when necessary. C.I.
) U IO controls the entire system including CI) U I 2, and one with a fast processing speed is used.

The chip enable terminal of CI'UIO is connected via a control signal line SIO to the gate of an N-channel MO824 that constitutes an inverter 22 as a level adjustment means. A grounded N-channel MO324, one end connected to the drain of the N-channel MO924, and the other end connected to the battery!
The drain of the N-channel MO824 is connected to the control signal line S2.
1 of CP tJ I 2 through 0. NT (interrupt input)
connected to the terminal. Therefore, when the CE terminal becomes a low level potential (L), the fNT terminal becomes a high level potential (
11). At this rising edge, an interrupt is applied to the CPUI2, and processing for transmitting and receiving signals between the CPU10 and the CPUI2 is performed. That is, the starting point of signal transmission/reception is determined by CPU10, and CPtJ12 follows this.

Here, the power source of the inverter 22 is the battery 16,
When the terminal is at I, the INT terminal becomes approximately 0 volts, and when the terminal is at L, the INT terminal becomes Voo volts. As a result, the noise margin of the signal applied to the INT terminal increases1, and the DC/
Even if large noise is emitted from the DC converter, receiving and receiving erroneous signals can be prevented.

The ACK terminal of the CPU IO is connected to the output terminal of the inverter 28 via the control signal line S11, and the input terminal of the inverter 28 is connected to the ACK terminal of the CPU 12 via the control signal line S21. . This signal line is used as follows. CPU
Send data from I O to CPU I2,
If CI2 accepts this, CI) U12 outputs a pulse from the terminal 80 to notify CPU10. CPUl0 receives this (uses J to send the next data to CPUl2)
send to On the contrary, from CT' U l 2 to CPU
When sending data to IQ, output a pulse from terminal 80 every time data is sent and notify CPU10.

In other words, when CPUI2 receives data from CPUIO, an acknowledge signal is supplied from the ACK terminal to CPUl0, and Cr'U is sent from CPtJ12.
When sending data to IO, a synchronization signal that distinguishes each data is supplied from the ΔCK terminal to CPU10.

In this way, since the timing of transmission and reception is determined using a single signal line regardless of the data transmission direction, there is an effect that the number of signal lines can be reduced.

The inverter 28 is equipped with a level switch as a level adjusting means, and the power source of the inverter 28 is the switching regulator 20.

Therefore, even if the voltage output from the ACK terminal is around 5 volts, it will be shifted to 5 volts and go to GK.
Supplied to the terminal. Furthermore, even if the output from the ACK terminal is a little high, the output voltage of the three-state path driver 30 will be approximately 0 volts.

Therefore, the noise marnon of the signal applied to the lower terminal at F becomes large.

Data is sent and received using the data input/output terminal DIA of CPU10.
4-bit parallel data is supplied from -D4A to the data input/output terminal DIR-D413 of the CPU 12, and vice versa.
Data input/output terminal DIB-D4B of CPU12 to CP
4-bit parallel data is supplied to the data input/output terminal DIA-D4A of Ul0.

That is, the data input/output terminal DIA of CPUl0 is connected to the output terminal of the three-state bus driver 30 via the data bus line S12, and the input terminal of the three-state bus driver 30 is connected to the data input/output terminal of the CPUI2 via the data bus line S22. Connected to terminal DIB.

This three-state bus driver 30 connects the inverter 2
Similarly to 8, since a level switch is provided as a level adjusting means and the power supply of the three-state bus driver 30 is the switching regulator 20, the noise margin of the signal applied to the data input/output terminal DIA becomes large.

Data bus line S12 is also connected to one input terminal of NOR gate 32. A data bus line 326 is connected to the other input terminal of the NOR gate 32 from the CNT terminal of the CPU 12 via a buffer gate 34 . The output terminal of the NOR gate 32 is an N-channel MOS 3 that constitutes an inverter 36 as a level adjustment means.
It is connected to gate 8. This inverter 36 has the same configuration as the above-mentioned inverter 22, and has an N-channel MO
One end of a pull-up resistor 40 is connected to the source of S38. Further, the source of the N-channel MOS 38 is connected to the data input/output terminal DIB of the CPU I 2 via the data bus line S22.

Here, when sending data from the CPU 10 to the CPU 12, the CNT (input/output control) terminal of the CPU 2 is set to L, the NOR gate 32 is opened, and the signal output from the data input/output terminal DIA is inverted. TeN
The signal is transmitted to the gate of the channel MOSa8, further inverted by the inverter 36, and sent to the data input/output terminal DIB of the CPU I2.

The power source of the inverter 36 is the battery 16, and the voltage level is adjusted as in the case of the inverter 22, so that the noise margin of the signal applied to the data input/output terminal DIB is increased.

Data bus line 326 is also connected to one input terminal of Nant gate 42. A control signal line S10 is connected to the other input terminal of the Nant gate 42.
Connected via 4.

The output terminal of this Nant gate 42 is the data bus line S.
27 to the control terminal of the three-state bus driver 30.

Therefore, only when the n terminal is L and the CNT terminal is 11, the control terminal of the three-state bus driver 30 becomes active, and the three-state path driver 30 becomes active. In this case, the NOR gate 32 is closed and the N-channel MOS 38 is in an off state, so the data transmission direction is from the CI) U 12 side to the CPU10 side.

Data input/output terminals D2A-D4A and data input/output terminal D
The circuit configurations interposed in the signal lines between 2 B and 4 B are the same as the above circuit configurations interposed between the data input/output terminal DI and the data input/output terminal DIB, respectively. Data bus lines S13 to S15 correspond to bus line SI2, three-state bus drivers 46 to 50 correspond to three-state bus driver 30, and data bus lines S23 to S22 correspond to data bus line S22.
S25 corresponds to Noah gate 32 and Noah gate 52 to 5
6 corresponds to the inverter 36, and inverters 58 to 62 correspond to the inverter 36.

Here, since the processing speed of CPUl0 is faster than CPUI2, CPUl0 sets the C terminal to H to activate the three-state bus driver 30 after receiving data from CPUI2 until a pulse is sent from the ACK terminal. It is possible to set it in a high impedance state, supply a chip enable signal to other circuits, and send and receive data to and from the other circuits using a data bus. In this case, the CPU 12's ■
N T terminal is set to L, CPU12j; 1cPU
Since it is possible to know that IO is transmitting and receiving data with other circuits, if it takes a long time for the CPU 2 to transmit and receive data with other circuits, the INT terminal becomes
After confirming that , a pulse is output from the ACK terminal.

On the other hand, when sending data from CPU 10 to CPU 12, the CNT terminal is connected to the Noah gate 32.52.
~56 is open and the CPU 12 is interrupt processing.
Even if l0 sends and receives data to and from a circuit other than the CPU 12, this data is transferred to the data input/output terminal D I of the CPU 12.
It is also sent to n-D4r3. However, in this case, the CPU O sets the C terminal to If, and the I
N T J, m'Q child has been written, so even if an interrupt is being processed, the CPUI2 will use this data as CPtJIO.
You can know that it is not intended to be sent to the CPU 12, and after the rNT terminal becomes 11, the CPU
Receives data from O.

Then, a pulse is output from the ACK terminal to prompt the CPU 10 to output the next data.

Next, an example of interrupt processing of the CPUI 2 will be explained.

FIG. 2 is a flowchart of this interrupt processing, and FIG. 3 is a timing chart of signals in the interrupt processing.

The voltage at the INT terminal rises and Cr' [J I 2
When an interrupt occurs, the contents of the register are saved in step +00, and then in step +02, the interrupt is masked and the interrupt is disabled.

Here, the CPU10 sets the C terminal to the low level, and at the same time outputs the data M to the data input/output terminal DIA-D4A.The value of this data M determines the data transmission direction, the type of data to be sent and received, and the The number is determined.

In step 103, read this data M, and in step 1
In step 04, the processing content is selected according to the value of data M. That is, if the value of data M is 0 or I, CPU I2 receives data from CPU I0, and if the value of data M is 2 to 4, CPU I2 sends data to CPU IO. In addition, as shown in FIG.
The write address and number of data sent to CPU12 are determined, and the write address and number of data sent to CPU12 are determined.
The read address and number of pieces of data to be sent to are determined.

Therefore, there is no need to separately use a signal line indicating the direction of signal transmission/reception and a signal line indicating the end of sent data, resulting in an effect that the number of signal lines can be reduced.

If M=0, the CNT terminal is set to 11 in step 106.
to close NOR gates 32.52-56 and activate three-state bus drivers 30.46-50. Next, in step 108, a pulse is output from the terminal 80 to inform it that data 8 will be sent from the CPUI2 to the CPU10. Next, step +10 and CPU +2
The data A written in i is read out to a predetermined address of the riFAM and sent to the CPU10. CI) U
Since the processing speed of IO is fast, this data can be read immediately, and the remaining time can be used effectively by sending and receiving data with other circuits until the next pulse is supplied from the ACK terminal. I can do it.

In this case, as shown in FIG. 3, I of CI) U l 2
The NT terminal is closed for a certain period of time. In the flowchart shown in Figure 2, CPU2 does not confirm that the INT terminal has become low, but if this low period is long for CPUI2, it confirms this and changes the INT terminal to high. A pulse may be output from the ACK terminal later.

Next, in step +12, a pulse is output from the ACK terminal, and in step +14, data B written in the specified address of the RAM of CPUI2 is read out and the CPU t
Output to o. Next, in step 116, a pulse is output from the ACK terminal. The CPU 10 knows the type and number of data to be received from the CPU 12 from the value of the data M outputted first, and knows that the data sent from the CPU 2 has ended due to the pulse from the ACK terminal.

Next, in step 11g, the CNT terminal is set to L to open the NOR gates 32, 52-56, and the three-state bus drivers 30, 46-50 are placed in a high impedance state. This allows CPU10 to send and receive data to and from other circuits using the data bus. Next, in step 120, the interrupt disabled state is canceled. Next step 122
The contents of the register immediately before the interrupt are restored and the processing before the interrupt is resumed.

If M=1, the process advances to step 124 and the same process as described above is performed.

In the case of M=2, since the CNT terminal is already set to L, there is no need to set the CNT terminal to L again, and step 12
At step 6, a pulse is output from the ACK terminal to notify CPU10 that data M has been received. Then step 128
Then, it is determined whether the INT terminal is 4 or not.

If the three-state bus driver 30.
46 to 50 are in a high impedance state, and C
PU10 can use the data bus to send and receive data to and from other circuits. After this use, the CPU10 closes the GE terminal and the data output terminal DIA-D4A.
Data E is output to.

The CPU 12 waits for the INT terminal to become H, then proceeds to step 130, reads data E, and writes it to a predetermined address in the RAM. Next, in step 132, a pulse is output from the ACK terminal to indicate that the data has been received.
Inform Ul0. Then, in steps 134-138, the next data is received in the same manner as steps 128-132, and this is notified to CPU10. Next, step 118~! After performing the processing in step 22, the processing before the interrupt is resumed.

If M=3, proceed from step 104 to step 136; if M=4, proceed from step +04 to step 1.
The process advances to step 38, and the same processing as in the case of M=2 described above is performed.

In this way, by using as few control signal lines as possible considering the special characteristics of the camera, CPU10 and C
In addition to transmitting and receiving data to and from the PU 12, in a CPU having a high processing speed, other processing can be performed during the data transmission and reception, thereby making effective use of waiting time.

Well, if you make the data input of CPUI2 a latch input,
Step +28.134 can be omitted.

[Effects of the Invention] In the processing speed difference adjustment interface according to the present invention,
A chip enable signal is supplied as an interrupt signal from the high-speed processing CPU side to the low-speed processing CPU side, and the data transmission/reception direction is from the low-speed processing CPU side to the high-speed processing CPU side, and
Only when the low-speed processing CPU is selected by the chip enable signal, the three-state bus driver is activated and data is sent in the corresponding transmission/reception direction. If the three-state bus driver is being sent, the high-speed processing CPU can read it instantly and temporarily change the chip enable signal to put the three-state bus driver in a high-impedance state, thereby disconnecting the data bus from other circuits. On the other hand, low-speed processing CP
U performs high-speed processing C due to changes in this chip enable signal.
Since it is possible to know that the PU is sending and receiving data with other circuits, it is possible to hold off sending the next data until the chip enable signal returns to its original state, or to reduce the processing speed of a low-speed CPU. is slow, so in some cases, do not suspend this process, and even if the chip enable signal returns to its original state, if you disable interrupts, the low-speed processing CPU will not be interrupted again, so data transmission and reception will continue. In addition, when data is being sent from the high-speed processing CPU side to the low-speed processing CPU side, the three-state bus driver is in a high impedance state from the beginning, so the high-speed processing CPU receives the chip enable signal. Data can be sent and received from other circuits simply by temporarily changing the . It has the excellent effect of being able to send and receive data in real time, making effective use of waiting time and adjusting processing speed differences.

In addition, the hardware configuration is simple, making it suitable for cameras that are required to be multi-functional and compact.

[Brief explanation of the drawing]

1 to 4 relate to embodiments of the present invention, in which FIG. 1 is a circuit diagram mainly showing an interface 14 interposed in a signal line between a high-speed processing CPU and a low-speed processing CPU, and FIG. Flowchart showing interrupt processing of CPUI2, Figure 3 is a timing chart during signal transmission and reception, Figure 4 is a flowchart showing CPU12 interrupt processing.
FIG. 2 is a diagram showing a storage area of transmitted and received data written to or read from a RAM built in the computer. 22.44: Inverter 42: NAND gate 30.46.48.50 Nisly state bus driver CE: Chip enable signal output terminal INT: Interrupt signal input terminal S26: Signal line that supplies a signal indicating the data transmission/reception direction

Claims (1)

[Scope of Claims] In a device that transmits and receives data between a high-speed processing CPU and a low-speed processing CPU via a data bus, an input terminal is connected to the low-speed processing CPU side, and a three-way a state bus driver; a signal line that supplies a chip enable signal as an interrupt signal from the high-speed processing CPU side to the low-speed processing CPU side; and a data direction control signal that indicates the data transmission/reception direction from the low-speed processing CPU side. , a gate circuit that is supplied with a chip enable signal from the high-speed processing CPU side and supplies an enable signal to the control terminal of the three-state bus driver in accordance with both signals, and the gate circuit is configured to operate in the data transmission/reception direction. is from the low-speed processing CPU side to the high-speed processing CPU side, and the three-state bus driver is activated when it is determined that the low-speed processing CPU is selected by the chip enable signal. Interface for adjusting processing speed difference.