JPS63156418A - Reset pulse generation circuit - Google Patents

Abstract

PURPOSE:To stably and surely generate a reset pulse, by generating the reset pulse by detecting the change from the absence to the presence of the input of a clock pulse. CONSTITUTION:When no clock pulse (a) is inputted exceeding the period of the time constant of a monostable multivibrator 17, the output signal (b) of the monostable multivibrator 17 falls from a high level to a low level. Next, when the clock pulse (a) begins to be inputted again, the monostable multivibrator 17 is triggered by the leading edge of the clock pulse (a), and begins to output the signal (b) of high level. A monostable multivibrator 18 is triggered by the leading edge of the signal (b). Thus, when the change from the absence to the presence of the clock pulse (a) occurs, the reset pulse having constant pulse width T is generated at and outputted from an output terminal 14.

Description

[Detailed Description of the Invention] [Summary] The present invention detects that the input clock to the digital circuit to be reset changes from zero to the right in a circuit that generates a reset pulse for resetting a digital circuit. By generating a reset pulse, you can stabilize the digital circuit even if the power supply of the digital circuit does not change from off to on and remains on.
This allows for reliable reset.

[Industrial application field]

The present invention relates to a reset pulse generation circuit, and more particularly to a reset pulse generation circuit that resets a digital circuit to which a clock pulse is applied.

In differential pulse code modulators, variable length code modulators, and other digital circuits with feedback loops, storage elements such as memory retain the results of the previous operation, and the next operation is performed based on this. Because it has a configuration,
It is necessary to set the digital circuit to an initial state at the time of starting, and generation of a reset pulse for this purpose is important.

[Conventional technology]

FIG. 4 shows a circuit diagram of an example of a conventional reset pulse generating circuit. In the figure, a resistor 1 and a capacitor 2 constitute an integrating circuit, and supply the inverter 3 with the terminal voltage of a capacitor 'j2, which is successively charged by supplying the power supply voltage Vcc. When the input voltage (ie, the terminal voltage of the capacitor 2) approaches a predetermined threshold value, the inverter 3 outputs a reset pulse that changes from high level to low level to the output terminal 4.

Therefore, according to this conventional reset pulse generation circuit,
After the power is turned on, a heliset pulse at the output terminal 4 is generated and outputted after a delay period determined by the charging time constant of the capacitor 2.

(Problems to be Solved by the Invention) The conventional reset pulse generation circuit described above generates a reset pulse when the power is turned on from off, so that the digital circuit to be reset is The digital circuit could not be reset unless i changed from off to on.

For example, as shown in FIG. 5 (final diagram), printed circuit boards 5 and 6 having a common power supply circuit are housed in one housing, and a clock generation circuit 7 is mounted on the printed circuit board 5. When the printed circuit board 6 is equipped with a digital circuit 8 and a reset pulse generation circuit 9 configured as shown in FIG. 6
The signal is supplied to the upper digital circuit 8.

In such a configuration, if only the printed circuit board 5 is removed from the casing and then reinstalled into the casing,
Since the power to the printed circuit board 6 remains on regardless of whether the printed circuit board 1 or the printed circuit board 5 is inserted or removed, the reset pulse generation circuit 9
Then, the reset pulse is not generated when the printed circuit board 5 is reinstalled into the housing as described above, and the digital circuit 8 receives an irregular lock pulse due to chattering or the like, and even if it falls into an unsteady state, it cannot be reset. It was not possible to restore it to normal condition.

The present invention was created in view of the above points, and an object of the present invention is to provide a reset pulse generation circuit that can reliably generate a reset pulse based on changes in the presence or absence of a clock pulse.

(Means for solving the problem) Fig. 1 shows a principle block diagram of a reset pulse generation circuit according to the present invention. In the figure, 12 is a clock presence/absence detection circuit, and 13 is a pulse generation circuit. The detection circuit 12 detects a change in the clock pulse from the input terminal 'F11 from absent to present.The pulse generating circuit 13 generates a pulse and outputs it to the output terminal 14.

A clock pulse from input terminal 11 is applied via output terminal 15 to a digital circuit (not shown). This digital circuit receives a pulse from the output terminal 14 as a reset pulse, and is reset.

[Effect]

When a clock pulse starts to be input from a state where no clock pulse was input to the input terminal 11, the clock presence/absence detection circuit 12 detects this and generates a detection signal with a different logical value from the previous one to generate a pulse. Supplied to circuit 13. As a result, the pulse generating circuit 13 is triggered by the detection signal, generates a pulse, and supplies this pulse as a heliset pulse to the digital circuit via the output terminal 14.

On the other hand, during the period when the reset pulse is input or when there is no clock pulse input, the clock presence/absence detection circuit 12 continues to output a signal with a predetermined logic value, but the pulse generation circuit 13 outputs the logic value of the input signal. Since the configuration is such that a 1-trigger is triggered by a predetermined change (for example, a rise) in , the trigger is not triggered, and therefore, no pulse is taken out from the pulse generating circuit 13. This also applies when the clock pulse changes from presence to absence.

Therefore, a reset pulse is generated at the output terminal 14 only when the clock pulse from the input terminal 11 changes from zero to right.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the reset pulse generating circuit according to the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted.

In FIG. 2, the clock presence/absence detection circuit 12 is composed of a retrigger type monostable multivibrator 17, and an external capacitor C1 and a resistor R+ forming a time constant circuit. The time constant of the monostable multivibrator 17 is set to be sufficiently longer than one period of the clock pulse a from the input terminal 11.

On the other hand, the pulse generation circuit 13 includes a monostable multivibrator 18 and an external capacitor C2 that constitutes a time constant circuit.
and a resistor R2. The time constant of this monostable multivibrator 18 is set to a value that allows a predetermined pulse width T to be obtained.

The monostable multivibrators 17 and 18 are built in, for example, one one-shot IC (for example, 74LS123), and are configured to be triggered by the rising edge of an input pulse at its clock terminal (trigger terminal).

Next, the operation of the embodiment circuit shown in FIG. 2 will be explained with reference to FIG. 3. A clock pulse a of a constant period as shown in FIG. 3(A) enters the input terminal 11 and is applied to the clock terminal of the retrigger type monostable multivibrator 17. During the period when this clock pulse a is continuously input as a pulse train, the time constant of the monostable multivibrator 17 is set sufficiently longer than the period of the clock pulse a, so the output of the stable multivibrator 17 is A high level signal is taken out from the terminal as shown in FIG. 3(B).

This output signal is applied to the clock terminal of the monostable multivibrator 18.
8 is triggered at the rising edge of the input signal as described above, so it is not triggered in this case, and its output signal is at a low level as shown in FIG. 3(C).

Thereafter, when the clock pulse a is interrupted for a period longer than the time constant of the monostable multivibrator 17, the output signal of the monostable multivibrator 17 changes from high level to low level at time tI, as shown in FIG. 3(B). Go down.

Therefore, the monostable multivibrator 18 is not triggered and its output signal C remains at a low level, as shown in FIG. 3(C).

Next, when the clock pulse a starts to enter again at time t2, the monostable multivibrator 17 is triggered by the rising edge of this clock pulse a, and as shown in FIG. Starts outputting signals.

The monostable multivibrator 18 receives this signal at time t.
Since it is triggered at the rising edge at 2, the signal C is at a high level for a period of time T as shown in FIG. 3(C) from time t2.
is output to the output terminal 14.

In this way, when the clock pulse a changes from nothing to the right, a reset pulse C having a quantitative pulse width T is generated and outputted to the output terminal 14 as shown in FIG. 3(C).

According to the reset pulse generation circuit of this embodiment, even when the printed circuit board 5 on which the clock generation circuit 7 shown in FIG. 5 is mounted is removed and then reinstalled, a reset pulse can be reliably generated.

It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that the clock presence/absence detection circuit 12 and the pulse generation circuit 13 can be constructed by combining timers, gate circuits, and the like.

〔Effect of the invention〕

As described above, according to the present invention, the reset pulse is generated and output by detecting the change in the input of the clock pulse from absent to present, so that the power of the digital circuit to which the clock pulse is applied is turned on. This device has features such as being able to generate reset pulses stably and reliably even when a printed circuit board that generates clock pulses is attached.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of the circuit shown in FIG. Figure 4 is a circuit diagram of an example of a conventional circuit. FIG. 5 shows the connection relationship of the printed circuit board. In the figure, 11 is a clock pulse input terminal; 12 is a clock presence/absence detection circuit; 13 is a pulse generation output terminal; 14 is a reset pulse output terminal; 15 is a clock pulse output terminal.

Claims (1)

[Claims] A reset pulse generation circuit that generates a reset pulse for resetting a digital circuit to which a clock pulse is applied, comprising a clock presence/absence detection circuit ( 12); and a pulse generation circuit (13) that generates a pulse based on the change detection signal from the clock presence/absence detection circuit (12) and outputs it as a reset pulse to the digital circuit. Pulse generation circuit.