JPS63155372A - Filtering circuit - Google Patents

Abstract

PURPOSE:To attain satisfactory expansion to adjacent picture element data with a small number of filtering frequencies by rewriting the filtering result in a feedback mode and carrying out successively the filtering processes according to said rewriting result. CONSTITUTION:The picture element data are inputted to line buffer memories 1-1-1-3 and then outputted from these memories. These picture element data are held temporarily by latch circuits 2-1-2-3 and converted into the matrix- shaped picture element data to be supplied to an arithmetic circuit 3. The circuit 3 performs a filtering process, that is, the value of the center picture element data is changed to '1' from '0' to expand so-called recess/projection parts. The result of this filtering process is outputted to the next stage and at the same time rewritten in a feedback mode in the circuit 2-2 and the memory 1-3, etc., for application to the next filtering process. In such a way, the filtering process is carried out at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention provides a plurality of line buffer memories that sequentially store pixel data for one line in the horizontal direction in a serial manner, and a pixel data output from each of the plurality of line buffer memories. a latch circuit that temporarily stores pixel data in a sequentially delayed manner to generate adjacent pixel data in a matrix; and an arithmetic circuit that performs two-dimensional filter processing on the matrix of pixel data output from the latch circuit. is provided, outputs the result of the two-dimensional filter processing performed by this arithmetic circuit, and feeds this result back to the line buffer memory and the latch circuit to process the next pixel data. This is to improve the efficiency of filter processing.

[Industrial application field]

The present invention relates to a filtering processing circuit configured to perform two-dimensional filter processing on pixel data and feed back the results to process the next pixel.

[Conventional technology]

Conventionally, for sequentially input pixel data (image signals), 2
There is an image processing apparatus that includes a filtering processing circuit that performs dimensional filter processing to extract image features, remove noise, improve image quality, and the like.

This filtering processing circuit performs, for example, preprocessing for labeling to identify multiple areas scattered in an image.
In order to reduce the number of labels temporarily attached during labeling, it is essential to expand the shape of the region so that its irregularities are reduced. FIG. 7 shows a configuration diagram of a conventional filtering processing circuit, and FIG. 8 shows an explanatory diagram of the operation when this is used. A brief explanation will be given below.

In FIG. 7, line buffer memories 11-1 to 11-3 are for storing pixel data one line at a time in a serial manner. The pixel data output from these line buffer memories 11-1 to 11-3 are latched by latch circuits 12-1 to 12-9, respectively, and adjacent pixel data in a so-called matrix is supplied to the arithmetic circuit 13. The arithmetic circuit 13 that has received this matrix-like pixel data is configured to perform the first calculation so that the unevenness of the shape of the region is reduced, for example, when pixel data as shown in FIG. 8(a) is supplied. Through the filtering process, one pixel of the rectangular area fpl shown with diagonal lines in FIG. 8(b) is expanded. By the second filtering process, one pixel of the rectangular area fq shown by diagonal lines in FIG. 8(C) is expanded. When the labeling process is performed after these two filtering processes, two labels, a label a and a label b, are attached to a region with one unevenness, as shown in FIG. 8(d).
In order to give one label to this region, two stages of filtering processing are not sufficient, so more filtering processing circuits are connected.

[Problem that the invention seeks to solve]

A conventional filtering processing circuit as shown in FIG.
Since the values of pixel data determined by filtering were sequentially output, depending on one filtering process, the rectangular area (Pi in FIG. 8(b) or FIG.
Only one pixel shown in the rectangular area fQl in c) can be expanded adjacent to each area. Therefore, in order to sufficiently increase the effect of filtering processing, this filtering processing circuit must be connected in a pipeline of several tens of stages and filtering processing must be repeated, which poses the problem that it is difficult to perform processing efficiently and at high speed. there were.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a
A plurality of line buffer memories 1 sequentially store pixel data for lines in a serial manner, and the pixel data outputted from each of the plurality of line buffer memories 1 is temporarily stored in a sequentially delayed manner and stored in a matrix form. A latch circuit 2 that generates adjacent pixel data, and an arithmetic circuit 3 that performs two-dimensional filter processing on a matrix of pixel data output from the latch circuit 2 are provided. In addition to outputting the results of the filter processing, the results are also fed to the line buffer memory 1 and the latch circuit 2.

FIG. 1 shows a basic configuration diagram of the present invention. Line buffer memories 1-1 to 1-3 in the figure are for storing pixel data one line at a time in a serial manner.

The latch circuits 2-1 to 2-3 temporarily store pixel data output from the line buffer memories 1-1 to 1-3, and supply pixel data arranged in a matrix to the arithmetic circuit 3. The arithmetic circuit 3 is the latch circuit 2
A predetermined filtering process is performed based on the pixel data arranged in a matrix and supplied from -1 to 2-3. This processing result is output to the next stage processing module, and is rewritten by the BPJ which feeds back to the latch circuit 2-2, line buffer memory 1-3, etc. for use in processing the next pixel data.

[Effect]

Next, the operation will be explained.

In FIG. 1, pixel data is input to line buffers 1-1 to 1-3, and these line buffer memories 1
The pixel data output from -1 to 1-3 is temporarily held by latch circuits 2-1 to 2-3, converted into pixel data in a matrix, for example, a 3x3 matrix, and supplied to the arithmetic circuit 3. Ru. The arithmetic circuit 3 that receives this matrix-like pixel data performs a filtering process, for example, in the case of a pattern as shown in FIG. The results of this filtering process, which expands the uneven parts of the filter, are output to the next stage, and
In order to use it for the next filtering process, rewriting is performed by Mr. B who feeds it back to the latch circuit 2-2, line buffer 1-3, etc.

As described above, by adopting a configuration in which the results of the filtering process are rewritten in a manner that feeds back the results, and the filtering process is sequentially performed using the rewritten results, the filtering process can be performed with sufficient expansion for adjacent pixel data, etc. It is possible to do this several times.

〔Example〕

Next, a detailed description will be given of the configuration and operation of an embodiment in which 3×3 matrix pixel data is extracted from pixel data and filtering processing is performed.

In FIG. 2, line buffer memory 1-1 to 1
-3 stores pixel data for one line as described above, and latch circuits 2-11 to 2-19 temporarily store pixel data and generate pixel data in a 3×3 matrix. , the arithmetic circuit 3 performs filtering processing.

FIG. 3 shows an overall configuration diagram for performing labeling processing on an image. The filtering processing circuit 4 in FIG. 9 is related to the present invention, and the local area of the image is If any one of the diagrams (d) applies,
The central pixel data "O" is rewritten to 61" and output to the next processing module, and the result of this calculation is written to the latch circuit 2-16 using the signal line (al) in Figure 2, and the line Writing is performed from the beginning of the buffer memory 1-3. As a result, the results of filtering operations performed on certain pixel data in the image are fed back, and can be used when performing operations on adjacent pixel data. For example, if there are "1" areas like "a" and "b" in the image as shown in Figure 6 (a), the first processing will result in the areas shown in Figure 6 (b).
The rectangular areas shown using diagonal lines are sequentially rewritten to "l", and in the second process, the rectangular areas shown using diagonal lines in FIG. 6(c) are sequentially rewritten to "l". The result shown in FIG. 6 (-c) is output to the temporary labeling section 5.

In this way, by adopting a configuration in which the results of filtering processing are fed back and processing is performed sequentially, any two different regions existing in an image can be contiguous during filtering processing to the extent that adjacent regions are not combined. It is possible to expand the area and reduce the unevenness of the area as much as possible.

Incidentally, FIG. 8(B) shows the circuit after the first processing using the conventional circuit shown in FIG. 7, and FIG. 8(C) shows the circuit after the second processing. As can be seen by comparing the results related to the present invention shown in FIG. 6(C) and the results related to the conventional circuit shown in FIG. It is possible to perform sufficient expansion against the target and obtain good results.

Hereinafter, the operation when performing labeling processing using the filtered results according to the present invention will be briefly described.

The provisional labeling section 5 in FIG. 3 gives a provisional label to the human-powered image shown in FIG. 6(C) as a result of processing by the filtering processing circuit 4. For example, a window having a shape as shown in FIG. 5(a) is provided, and the input image is sequentially scanned using this window.
For the diagrams a, b, c, d, and
” At the same time, execute the procedure to add it to the position shown in Figure 5 (
A provisional level connection relationship is extracted based on the logic shown in c). The clustering unit 6 is notified of information regarding these provisional labels and connection relationships.

The clustering unit 6 tracks labels based on the connection relationships extracted by the provisional labeling unit 5, and groups all provisional labels that are connected to each other, whether directly or indirectly. Using the connection relationship extracted by the logic shown in c), a provisional label a is assigned to the filtered result shown in FIG.
It is applied as shown in FIG. 6(d).

The label updating unit 7 updates the temporary label based on the label tracking result, and attaches a uniquely corresponding label to each region in the image.

The original image extraction unit 8 restores the shape of each region to its original shape by calculating the logical product of the updated label image and the original image, thereby generating a final label image.

〔Effect of the invention〕

As explained above, according to the present invention, after the filtering results are fed back, adjacent image data are sequentially processed, so that the filtering results for a certain pixel in the image are It can be used when performing calculations on adjacent pixels, and the number of stages for filtering can be reduced to perform filtering processing efficiently and quickly.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle of the present invention, Figure 2 is a diagram showing the configuration of one embodiment of the present invention, Figure 3 is a diagram showing the overall configuration of labeling processing, and Figure 4 is a diagram showing the overall configuration of the labeling process.
5 is an explanatory diagram of the operation of the arithmetic circuit according to the present invention, FIG. 5 is an explanatory diagram of the operation of the temporary labeling section, FIG. 6 is an explanatory diagram of the operation of the present invention, FIG. 7 is a configuration diagram of the conventional circuit, and FIG. 8 is an explanatory diagram of the operation of the arithmetic circuit according to the present invention. shows an explanatory diagram of the operation of a conventional circuit. In the figure, 1.1-1 to 1-3 represent line buffer memories, 2.2-1 to 2-3 represent latch circuits, and 3 represents an arithmetic circuit.

Claims (1)

[Claims] A filtering processing circuit that filters pixel data generated by scanning an image includes a plurality of line buffer memories (1) that sequentially store pixel data for one horizontal line in a serial manner; , a latch circuit (2) that temporarily stores pixel data outputted from the plurality of line buffer memories (1) in a sequentially delayed manner to generate adjacent pixel data in a matrix; and this latch circuit (2). ) is an arithmetic circuit that performs two-dimensional filter processing on the matrix of pixel data output from (
3), outputting the result of the two-dimensional filter processing performed by the arithmetic circuit (3), and feeding back this result to the line buffer memory (1) and the latch circuit (2). A filtering processing circuit characterized in that it is configured to perform processing by rewriting with.