JP2550967B2 - Reverse pattern creation device - Google Patents

Description

The present invention relates to a pattern formed on a mask or reticle (collectively referred to as “mask” in this specification) used for manufacturing a semiconductor device. The present invention relates to an apparatus for inspecting a pattern defect by comparing it with design data of a pattern, and more particularly to an inversion pattern creating apparatus for obtaining a bit image pattern by synthesizing a plurality of inversion patterns having overlapping portions from the design data.

(Prior Art) Conventionally, an apparatus for creating an image pattern from design data for inspecting a mask pattern for defects has one or two memories. This is a method in which all the image patterns obtained based on the above are drawn in the memory and then the image data is read in synchronization with the mask scanning to determine the defect. In order to absorb the above, a method is used in which while drawing a series of image patterns in one memory, the already drawn image data is read from the other memory to make a defect judgment.

In such a system, the design data that numerically expresses the pattern of the entire mask is format-converted into a unit that can be expressed as an image pattern in the memory and stored in a storage medium such as a magnetic disk or magnetic tape. Incidentally, the image data read out from the storage medium at the time of the defect inspection shows "0" or "1" representing the pattern portion.
If the image is a positive image in which the bit representing the pattern is "1", the image data is output as it is and drawn in the memory, while the bit that represents the pattern is displayed. When the image is an inverted image of "0", the inverted image data is output so that the image is drawn as an inverted image in the memory to obtain an image pattern based on the target design pattern data.

(Problems to be Solved by the Invention) However, in such a conventional method of obtaining an image pattern from design pattern data, all images of a mask to be inspected are represented by a single design data. In this case, there was no particular problem, but in recent years, the design data has become modularized as semiconductor devices have become highly integrated and complicated, and as a result, a plurality of design data have The whole image of one mask is formed.

In particular, in a mask pattern formed by a plurality of design pattern data, there is a case where a pattern represented by a plurality of design pattern data is inverted and a plurality of inverted image patterns have an overlapping portion.

In the defect inspection when the image pattern based on such a plurality of design pattern data is a combination of a plurality of inverted images and has an overlapping portion, all the design pattern data are combined in advance by the software of the electronic computer, and especially inverted. In the thing, the process of obtaining an inversion pattern from the design pattern data is required, and the process of obtaining this inversion pattern requires several times the processing time compared to the case of obtaining a positive pattern even when using a large computer.
In addition, there is a problem that a very large and high speed electronic computer is required to reduce the processing time.

As another means for obtaining an inversion pattern, a positive pattern is first obtained from design pattern data and drawn in a memory, and when reading the drawn data, bit output “0” is set to “1” and “1” is set to “1”. Some flip it to "0". However, in such bit inversion, all the bits of the image data drawn in the memory are inverted, so that it is difficult to invert only a part of the pattern. In particular, as described above, the entire image of a single mask is formed by design pattern data of multiple files, some of these patterns are inverted, and the inverted image has an overlapping part and the entire image is Since it may have been formed, simple bit inversion cannot deal with it.

(Means for Solving Problems) The present invention has been made in view of such conventional problems, and is an image pattern based on design pattern data of a plurality of files formed with overlapping portions of inverted images. Even if there is, it is an object of the present invention to provide an inversion pattern creating apparatus that can obtain an inversion pattern for defect inspection in a processing time and a processing load that are substantially the same as those in obtaining a positive pattern from design pattern data.

To achieve this object, in the present invention, a plurality of design pattern data (Pa ₁ , Pa ₂ , Pa ₃ , Pa ₄ ) in which the mask patterns A, B, C are numerically expressed, (Pb ₁ , Pb ₂ , Pb ₃ , Pb ₄ ),
When (Pc ₁ , Pc ₂ ) forms image data for each divided area divided along the mask 1 scanning line by the sensor, at least two patterns A and B are inverted and overlap each other. In the reverse pattern creation device where image data is formed, prior to defect inspection,
By the first processing means, the design pattern data (Pc ₁ , Pc ₁
A positive image flag is added to c ₂ ) and design pattern data (Pa ₁ , Pa ₂ , Pa ₃ , Pa ₄ ) of patterns A and B to be inverted (Pb
₁ , Pb ₂ , Pb ₃ , Pb ₄ ) is provided with a flag of a reverse image, and the area including the pattern C of the normal image or the area including patterns A and B of the reverse image is further processed by the second processing means. treat as a single pattern, along with subjecting area setting data Pa ₀ to the design pattern data of the pattern, Pb _0, Pc ₀ respectively, areas of reversed image setting data Pa _0, Pb ₀
Is added with a flag of a normal image (however, the area setting data Pc ₀ of the design pattern data of the pattern C which is not inverted is not necessarily required).

Next, at the time of defect scanning, two of the image forming means having at least three storage means are used, and a divided image one position ahead of the mask scanning position by the sensor is first processed by the second processing means to form a positive image. The entire set area that forms the pattern A based on the area setting data Pa ₀ of the flagged pattern, for example, the inverted pattern is rewritten to the flag-specified normal image, and then the area rewritten to the normal image by the flag specification is changed. Data of the first processing means, that is, pattern data Pa with an inverted image flag
_A memory process for rewriting an inverted image by ₁ , Pa ₂ , Pa ₃ , Pa ₄ to create an inverted pattern is performed by two different patterns, which are divided for each B, and two types of inverted patterns to two storage means. After the memory formation is completed, the logical sum of the memory data of both is calculated to store the image data of the combined pattern in either one of the memory means, and the remaining one memory means at the time of the mask scan of the previous divided area. The image data of the composite pattern whose storage has been completed is read out to the defect determining means in synchronization with the data obtained by the mask scanning, and the storage formation of the image data is completed every time the mask scanning of one divided area is completed. The operation of switching one of the storage means to the read state and the operation of switching the other two storage means to the storage formation state of the image data of the next divided area is alternately repeated.

(Operation) According to such a configuration of the present invention, even if the image pattern for each mask division region based on the plurality of design pattern data is a composite pattern of a plurality of inverted image patterns and has an overlapping portion, the design pattern When creating the image data for expressing the mask pattern from the data, a reverse image flag is attached to the design pattern data that will be the reverse image,
Since the area setting data that treats the area including the inverted image pattern as one pattern is added,
By creating an inversion pattern using the design pattern data with the inversion image flag and the area setting data thus created, a plurality of inversion image patterns can be combined with a processing time and a processing load that are substantially the same as those of the normal image. , Which includes a combination with a positive image pattern), can be used to create an image pattern serving as a criterion for defect inspection.

Furthermore, in order to create an inversion pattern based on a plurality of design pattern data, three storage means are used. Of these, two storage means are used to create an inversion pattern of a divided area one ahead of the mask scanning position, and the remaining storage means. Since the reverse pattern created by the previous process is stored in, the comparison process of defect judgment is performed by reading the pattern data synchronized with the data obtained by the mask scanning by the sensor. It is possible to continuously perform the creation process of the reference inversion pattern and the defect determination process in real time in synchronization with the mask scanning.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.

In the following description, the case of obtaining a mask pattern as shown in FIGS. 3 and 4 will be described as an example. That is, the mask pattern shown in FIG. 3 is a composite pattern in which patterns C and C are overlapped so that their boundaries are in contact with each other, and are created based on the design pattern data DA, DB and DC, respectively. Pattern, is design pattern data D
It is an inversion pattern of A and DB, and in particular, in the central divided area (X2, Y2) divided as shown by the dotted line, it partially overlaps with the inversion pattern.

In FIG. 1, reference numeral 23 is a magnetic tape reader for reading design pattern data DA, DB, DC. As shown in FIG.
Design pattern data DA, DB, and DC are stored in 23b and 23c. For example, the design pattern data DA of pattern A is
As shown in FIG. 5, it includes a plurality of pattern data (Pa _{1 to} Pa ₄ ) forming a pattern A, and these pattern data (Pa _{1 to} Pa ₄ ) are numerical data representing the end points and slopes of line segments. Becomes The same applies to the design pattern data DB and DC, and the design pattern data DB includes pattern data (Pb _{1 to} Pb ₄ ) for forming the pattern B. Further, the design pattern data DC includes pattern data (Pc ₁ , Pc ₂ ) for forming the pattern C as numerical data.

In this way, the design pattern data DA, DB, shown in FIG.
By setting the magnetic file storing DC in the magnetic tape reader 23 shown in FIG. 1, each design pattern data is read into the mini computer 24, and the numerical data of the design pattern data is read by the arithmetic processing by the mini computer 24. The format is converted into a unit that can be expressed as an image pattern in the memory that will be clarified in the description, and the design pattern data is written on the magnetic disk 25 as a storage medium.

Specifically, the three design pattern data DA, DB, DC read from the magnetic tape reader 23 to the minicomputer 24.
Is a divided area (X1, Y1) (X1) divided by a dotted line obtained by dividing one scanning line of the line sensor 30 for scanning the mask 32 as shown in FIG. 6 by the software of the minicomputer 24.
2, Y2), ... (X2, Y2), ... (X3, Y3) are converted and stored in the magnetic disk 25.

Here, the divided area (X2, Y2) in FIG. 3 will be described as an example of the design pattern data for each divided area stored in the magnetic disk 25 by the minicomputer 24. , for example, the pattern data (Pa ₁ ~Pa ₄₎ of the pattern a shown in FIG. 5, the pattern data (Pb ₁ ~Pb ₄₎ for the pattern B, further pattern C
For, the pattern data (Pc ₁ , Pc ₂ ) is stored.

Further, regarding the design pattern data DA and DB that give the minicomputer 24 a reverse pattern when storing the design pattern data of the area (X2, Y2), a process of adding a flag of a reverse image and a design pattern data of a pattern C that is not reversed The DC is processed as a first processing means for adding a flag of a positive image.

Further, when storing the design pattern data on the magnetic disk 25, the minicomputer 24 defines one area that includes a positive pattern (area of pattern C) or an area that includes an inverted image pattern (areas of patterns A and B) as one pattern. Processing as the second processing means for adding the setting data Pa ₀ , Pb ₀ , Pc ₀ of the pattern forming area to the design pattern data of this pattern. The positive pattern C
The area setting data Pc ₀ does not have to be added to the area.

FIG. 7A shows the divided areas (X1, Y1) to (X3, Y3) shown in FIG. 6 stored in the magnetic disk 25 by the minicomputer 24.
The storage state of the design pattern data P (X1, Y1) to P (X3, Y3) is shown. The details of the design pattern data P (X2, Y2) of the divided area (X2, Y2) are also shown on the right. It is taken out and shown as FIG. 7 (b).

The design pattern data P (X2, Y2) of the divided area (X2, Y2) shown in FIG. 7 (b) corresponds to the design pattern data shown in FIG. Design pattern data DC, DA, and DB are stored in this order.

First, the design pattern data DC is the pattern data (Pc ₁ ,
Pc ₂ ) and the pattern C based on the design pattern data DC becomes a pattern of a normal image, and therefore a flag of the normal image is added to each of the pattern data Pc ₁ and Pc ₂ .

The pattern data (Pc
₁ , Pc ₂ ) is followed by the pattern data (Pa ₁
~ Pa ₄ ) is stored. These pattern data (Pa ₁ ~
Since the pattern A based on Pa ₄ ) is a reverse pattern, a reverse image flag is added to each of the pattern data Pa _{1 to} Pa ₄ . Further, at the head position of the pattern data (Pa _{1 to} Pa ₄ ) to which the reverse image flag is added, area setting data (Pa ₀ ) for handling the area including the pattern A of the reverse image as one pattern is newly added. In addition, a normal image flag is also attached to this area setting data Pa ₀ .

Following the design pattern data DA consisting of pattern data (Pa _{1 to} Pa ₄ ) including such area setting data Pa ₀ ,
Design pattern data DB via memory change flag MC
Pattern data constituting the (Pb ₁ ~Pb ₄₎ is stored, and the area setting data (Pb ₀₎ for handling region including the pattern data (Pb ₁ ~Pb ₄₎ at its head position as one pattern Since this DB is an inverted image, a positive image flag is added to the area setting data (Pb ₀ ) and an inverted image flag is added to each of the pattern data (Pb _{1 to} Pb ₄ ). Has been done.

Further, the design pattern data P (X
END data is stored in the final position of (2, Y2) and indicates the end position of the data stored for each divided area.

Referring to FIG. 1 again, the storage of the design pattern data for each divided area in the magnetic disk 25 by the minicomputer 24 described above is performed in advance before the inspection of the mask 32. During the defect inspection by scanning the line sensor 30 with respect to the mask 32, the minicomputer 24 reads the design pattern data of the divided area, which is one area ahead of the mask scanning position by the line sensor 30, from the magnetic disk 25 and transmits the pattern via the raster conversion circuit 26. Bit pattern memory as forming means
27, and the inversion pattern as shown in FIG.
Then, an image pattern by synthesizing the positive pattern C is created in the bit pattern memory 27.

The writing of the pattern to the bit pattern memory 27 and the scanning of the mask 32 by the line sensor 30 are performed in synchronization with the clock pulse from the clock generator 28, and the bit pattern memory 27 scans the previous divided area. At this time, the pattern already formed is output to the defect comparison / determination circuit 31 in synchronization with the bit data of the mask 32 output from the line sensor 30, and at the same time, the mask detected by the line sensor 30 via the binarization circuit 29. Since 32-bit data is also given, the defect comparison / determination circuit 31
Is compared with the presence or absence of a defect in synchronization with the scanning of the mask 32 by the line sensor 30.

FIG. 2 is a circuit block diagram showing a concrete embodiment of the bit pattern memory 27 in the embodiment of FIG. 1, and the bit pattern memory 27 is provided with three rewritable memories 16, 17, 18 In forming the pattern of the areas (X2, Y2) shown in FIGS. 3, 4 and 5, for example, two memories 16 and 18 out of the three memories are used, and the remaining memory 17 is the same as the previous one. The pattern data already formed at the time of scanning the area is used for reading to the defect determining means in synchronization with the scanning of the mask 32 of the line sensor 30.

In the bit pattern memory shown in FIG. 2, 1,
Reference numerals 3 and 4 are latch circuits for latching the address of the pattern data obtained via the raster conversion circuit 26, and reference numeral 2 is a latch circuit for latching the pattern data obtained via the raster conversion circuit 26. The outputs of the latch circuits 1, 3 and 4 that latch the addresses are the memories 16, 17 and 18 respectively.
Is connected to the address ports A _{0 to} A _14, and the output of the latch circuit 2 for latching the pattern data is the buffers 12, 13,
Data write ports WE _{0 to} F of memories 16, 17, and 18 via 14
It is connected to the.

Reference numeral 10 is a counter that generates an address for data transfer and clearing between the memories 16 to 18, and the output of the counter 10 is via the buffers 5, 6 and 7 and address ports A _{0 to} A of the memories 16 to 18, respectively. Connected to ₁₄ . Further, 11 is a read counter, which generates a read address for reading the pattern data formed in one of the memories 16 or 17, and the output of the read counter 11 is passed through the buffers 8 and 9 to the memory 16 and It is connected to each address port a ₀ ~ ₁₄ 17.

Furthermore, the memory 1 used for reading the pattern data
The output ports DO _{0 to} F of 6, 17 are connected to the selector 22 via the latches 19, 20, and the selector 22 sends the pattern data as serial data to the defect comparison / determination circuit 31. Data output is naturally performed in synchronization with the scanning of the mask 32 by the line sensor 30.

On the other hand, memory used only for creating pattern data
The 18 output ports DO _{0 to} F are supplied to the latch circuit 21,
The output of the latch circuit 21 is stored in the memory via the buffers 12, 13, and 14.
It is fed back to the data write ports WE _{0 to} F of 16, 17, and 18. Further, the output of the buffer 15 is given to the data write ports WE _{0 to} F of the memory 2, and the input of the buffer 15 is connected to the power supply line to output the bit “0” by the inverted output. Bit "0" from buffer 15
Is written in the memory 18, so that the pattern data once written in the memory 18 can be erased.

 Next, the operation of the above embodiment will be described.

First, as described above, the three design pattern data DA, DB, DC are stored in the magnetic files 23a-23c shown in FIG. 5 set in the magnetic tape reader 23 of FIG. Then, when these magnetic files 23a to 23c are set in the magnetic tape reader 23 and the design pattern data DA, DB, DC are read into the minicomputer 24, the minicomputer 24 reads the design pattern data D.
Division areas (X1, Y1) in which A, DB, and DC are divided in the one-line scanning direction of the line sensor 30 with respect to the mask 32 shown in FIG.
Format conversion is performed for each (X3, Y3) and stored on the magnetic disk 25 as shown in FIG.
2, Y2), the pattern C, as shown in FIG.
The design pattern data arranged in the order of A and B will be stored.

Subsequently, at the time of mask defect inspection, the design pattern data of the divided area immediately preceding the corresponding divided area from the magnetic disk 25 in the scanning order of the line sensor 30 is read to the minicomputer 24 and sent to the raster conversion circuit 26. The raster conversion circuit 26 creates a 16-bit unit bit pattern as shown in FIG. 8 from the figure-represented numerical values, and X addresses 0 to 63 and Y addresses 0 to 511 on the memory, and the bit pattern of each XY address " Whether the part of "1" is drawn with bit "0" (inverted image) or "1" (normal image)
Is generated from the flag information attached to the pattern data shown on the right side of FIG. 7 and sent to the bit pattern memory 27. Of course, at this time, the memory change flag MC and END information shown in FIG. 7B are also sent.

Next, the pattern creation processing based on the pattern data of the area (X2, Y2) obtained by the raster conversion circuit 26 will be described with reference to the specific circuit configuration of the bit pattern memory 27 shown in FIG.

The pattern data of the area (X2, Y2) is converted to the raster conversion circuit 26.
2 is obtained, the memory 17 in the bit pattern memory of FIG. 2 already stores the pattern of the area (X3, Y2) formed at the time of scanning the previous divided area. Use memory 18 to divide the area (X2, Y
Perform the pattern creation process of 2).

The pattern creation processing of the divided areas (X2, Y2) using the memories 16 and 18 is performed through the processing steps 1 to 3 shown in FIG.

First, first because the pattern data for drawing a pattern C (Pc _1, Pc ₂₎ is provided, shown in Figure 9 the pattern data (Pc _1, Pc ₂₎ as a positive image from the raster conversion circuit 26 To write to memory 16.

Next, the pattern data of pattern A (Pa ₀ , Pa _{1 to} Pa ₄ )
Therefore, all the setting areas are set to the bit "1" in the area where the pattern A is formed based on the area setting data (Pa ₀ ) first obtained for the memory 18, as indicated by the shaded area in the memory 18. Write the pattern Next, since the pattern data (Pa ₁ ) is obtained, the bit pattern portion indicated by the dotted line corresponding to the pattern data (Pa ₁ ) is rewritten from the bit “1” to the bit “0” as indicated by in the memory 18. It In the same manner, bit inversion is performed by the pattern data (Pa _{2 to} Pa ₄ ) sequentially obtained as shown in the memory 18 to, and finally the memory 18
Rewrite so that the part of the bit "1" that gives the inversion pattern remains in.

When the writing of the inverted pattern to the memory 18 is completed by the processings in this way, the pattern data of the memory 18 is transferred to the memory 16 storing the pattern C, and given by the logical sum of both as shown in Creates the memory state of the bit pattern to be captured. Of course, the memory 18 is erased at the same time when the pattern data is transferred from the memory 18 to the memory 16.

Next, since the pattern data (Pb _{0 to} Pb ₄ ) of the pattern B is obtained, the memory 18 in the erased state is used again, and the pattern B is formed based on the area formation data (Pb ₀ ) as shown in The bit pattern of the bit "1" is written in the formation area of, and the bits of the area of the pattern data (Pb _{1 to} Pb ₄ ) are rewritten to "0" as shown in An inverted pattern is obtained in memory 18 as shown.

If an inverted bit pattern is stored and formed in the memory 18 as shown in, the pattern data of the memory 18 is read and added and stored in the memory 16, and the inverted pattern in the final divided area (X2, Y2) is shown in. , And the positive pattern C are combined and stored.

Here, writing of pattern data to the memories 16 to 18 shown in FIG. 2, memory transfer processing of reading the pattern data written in the memory 18 and adding and storing it in the memory 16 or 17, and further from the memories 16 and 17 The pattern data read process will be described in detail below.

First, taking the memory 16 as an example, the writing of pattern data will be described.
By setting the control signal DI ₀ to the write control port DI of DI ₀ = 0, the memory 16 enters the write mode and the latch circuit 1
The address data latched by enables output of the address data to the address ports A _{0 to} A ₁₄ of the memory 16, and the bit pattern data latched by the latch circuit 2 enables output and buffers.
By enabling 12 outputs at the same time, the memory 16
Data is input to the data write ports WE _{0 to} F of the memory and data bit “1” or “0” is input to the designated address of the memory 16.
Is written.

Next, the addition storage process for the memory 16 performed when the writing of the pattern data to the memory 18 is completed is as follows.

When the memory change flag MC is sent from the raster conversion circuit 26, a controller (not shown) adds the contents of the memory 18 to the contents of the memory 16 and clears the memory 18. That is,
The outputs of the latch circuits 1 and 2 are disabled, and the buffer 5 while counting the counter 10 from 0 to 7FFFH
And to enable the output of 7 simultaneously accesses the address port A ₀ ~ ₁₄ address port A of the memory 16 ₀ to A ₁₄ and the memory 18. As a result, the output data read from the memory 18 at the same address as the memory 16 is latched.
The output from the same address of the memory 18 latched by the latch circuit 21 is stored in the memory 16 by enabling the outputs of the buffers 12 and 15 and disabling the outputs of the buffers 13 and 14 at this time. All bits 0 are written in the memory 18 because the data is written and the output of the buffer 15 is enabled at the same time. That is, the memory 18 is cleared. Of course, at this time, DI ₀ to the write control port DI of the memory 16 is set to DI ₀ = 1 and DI ₂ to the write control port DI of the memory 2 is set to DI ₂ = 0.
Set to.

Next, for example, when reading the pattern already stored in the memory 17, the output of the buffer 9 is enabled so that the address data obtained by the read counter 11 is stored in the memory.
17 bits are input to the address ports A _{0 to} A ₁₄ , the contents of the memory 17 are read, the output data is latched by the latch circuit 20, and the selector circuit 22 selects 1 bit from the 16-bit data obtained via the latch circuit 20. The data is sequentially taken out and read out as serial data to the defect comparison / determination circuit.

Of course, the reading of the already-stored pattern data from the memory 17 is performed in parallel with the process of creating and storing new pattern data shown in FIG. The data is read in synchronization with the bit data obtained by 30 scans.

Pattern formation for each divided area in the bit pattern memory 27 and reading of the formed pattern are
The same applies to the other divided areas. When the scanning position of the mask 32 by the line sensor 30 moves from the divided area (X3, Y2) to the next divided area (X2, Y2), for example, the memory 16 shown in FIG. Is switched to the read state and the pattern formation state of the new divided areas by the memories 17 and 18 is changed, and pattern formation and reading by the memory switching are alternately repeated for each divided area to be formed based on the design pattern data. The serial data obtained by reading the pattern data is continuously supplied to the defect comparison / determination circuit 31.

In the bit pattern memory as the pattern forming means shown in FIG. 2, three independent memories 16 and 1 are used.
7 and 18 are used to form a pattern and read the formed pattern.

Further, the method of dividing the pattern forming region described above is also arbitrary, and the pattern forming region can be appropriately divided as necessary.

Furthermore, the present invention is not limited to the mask pattern inspection device,
It can also be applied to manufacturing equipment.

(Effect of the Invention) As described above, according to the present invention, a reverse pattern creating process in which a plurality of patterns are inverted and image data is created in an overlapping manner is substantially the same as a normal image pattern. This has the effect that it can be generated by real-time processing, the processing time can be shortened, and a composite inversion pattern can be easily created by combining overlapping inversion patterns.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit block diagram showing a concrete embodiment of the bit pattern memory of FIG. 1, and FIGS. 3 and 4 are mask forming patterns. Explanatory diagram shown, FIG. 5 is an explanatory diagram showing the contents of design pattern data and the final formation pattern, FIG. 6 is an explanatory diagram of divided areas along the mask scanning line, and FIG. 7 is an embodiment of FIG. 8 is an explanatory view showing a data structure of design pattern data stored in the magnetic disk, FIG. 8 is an explanatory view showing a storage process of the raster conversion circuit of FIG. 1, and FIG. 9 is a bit pattern memory of FIG. FIG. 8 is an explanatory diagram showing a pattern creation process by the. 1,2,3,4,19,20,21: Latch circuit 5,6,7,8,9,12,13,14,15: Buffer 10: Counter 11: Read counter 16,17, 18: Memory 22 : Selector 23: Magnetic tape reader 23a-23c: Magnetic file 24: Minicomputer (first processing means and second processing means) 25: Magnetic disk 26; Raster conversion circuit 27: Bit pattern memory (pattern creation means) 28: Clock generation 29: Binarization circuit 30: Line sensor 31: Defect comparison judgment circuit 32: Mask

Claims (1)

(57) [Claims] 1. Inversion of at least two patterns when forming image data for each divided area divided along one mask scanning line by a sensor from a plurality of design pattern data in which a mask pattern is expressed numerically. In the reversal pattern creating apparatus in which the image data is formed by overlapping with each other, the design pattern data of the non-reversed pattern among the design pattern data is attached with a flag of a positive image,
First processing means for attaching a flag of an inverted image to the design pattern data of the inverted pattern; of the patterns, a region including the pattern of the normal image or a region including the pattern of the inverted image is treated as one pattern. A second processing means for attaching the setting data of the area to the design pattern data of the pattern and attaching a flag of the positive image for the area setting data of the reverse image; and a mask scanning by a sensor having at least three storage means. For the pattern data of the divided area one position ahead of the position, two of the storage means are used to first convert the entire set area into an image flagged by the second processing means based on the area setting data. Based on the data of the first processing means, the rewritten area, and then the area rewritten into the image with the flag specified is rewritten. Instead, the process of storing and forming the image data of each pattern is divided into two different patterns, and the logical sum of the two stored data is calculated after the storage of the image data in the two storage means is completed. Then, from one remaining storage means, the remaining one storage means synchronizes the image data, which has been stored at the time of the previous mask scanning, with the data obtained by the mask scanning by the sensor, and the defect determination means. Every time the mask scanning of one divided area is completed, one of the storage means in which the storage of the image data has been completed is switched to the read state, and the other two storage means are changed to the image of the next divided area. An inversion pattern creating apparatus, comprising: an image forming unit that alternately repeats an operation of switching to a data storage forming state.