JPS63155084A - Image memory accessing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image memory access method, and in particular,
This invention relates to a method for displaying the contents of an image memory in a part of a large-scale TV readable area.

[Prior Art] Conventionally, the image memory of this type of image display is
It has the total effective screen image capacity required for TV reading. TV read constantly and regularly scans both sides of the effective area, and in order to perform positioning and reduction processing during writing, the write start address is shifted or 2 spaces removed.

[Problems to be Solved by the Invention] The above-mentioned conventional method uses the image memory of the entire effective screen capacity.
Even if you want to display one image data in one window that is part of the image.

The disadvantage is that it requires a large amount of memory.

SUMMARY OF THE INVENTION In view of the above drawbacks, an object of the present invention is to provide an image memory access method that does not require a large capacity memory when displaying two image data in one window that is a part of the screen.

[Means for Solving the Problems] According to the present invention, a write address generation circuit accesses within a valid write range, a read address generation circuit repeatedly accesses the write valid range, and a TV read valid range. An image memory access method is obtained, comprising a window key memory having a capacity of , and a dart means for gating the repeatedly accessed write valid range based on the television read valid range.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

101 is a converter, 102 is a write address generation circuit,
103 is a TV read address generation circuit, 104 is an image memory, 105 is a window key memory, 106 is a mask goo (106), 107 is a D/A converter, and 108 is a CRT.

The video signal quantized by the ADD converter 101 is as follows.

Write address generation circuit 1 that accesses the write effective range
It is written into the 2-image memory 104 at 02.

For example, the effective range of 2 screens is 1280 PIXELx
The effective range of the video signal output from the A/D converter 101 is 640 PIXEL x 480 lines.

When displaying from the coordinates of the display effective screen (300, 300), the X direction of the write address starts from 300 and ends at 63.
When it reaches 9, it returns to 0 and counts up to 2994. The Y direction of the write address starts from 300 and 479
When it reaches 0, it returns to 0 and counts up to 299. The screen at this time will look like the one shown in Figure 2.

When this image data is read from address O by the TV read address generation circuit 103 which repeatedly accesses the write effective range, the image shown in FIG. 3 is obtained. A key signal is read from the window key memory 105 for this image at the TV read cycle, and the image signal is gated by a mask gate 106. This conceptual diagram is shown in FIG. As shown in FIG. 5, the signal passing through this mask gate 106 is masked in the shaded area and is 640 pixels from the display coordinates (300, 300).
You can get PIXEL X 480 line video.

[Effects of the Invention] As explained above, the present invention has a write address generation circuit that accesses within an effective write range, a read address generation circuit that repeatedly accesses the write effective range, and a capacity corresponding to the effective TV read surface area. By having window key memory and.

Since the TV read effective range is larger than the write effective range, it has the effect of being able to display it on any display screen with the memory capacity within the write effective range, so one image data can be displayed in one window that is part of the screen. When displaying, there is no need to have a large capacity memory.

The present invention is particularly advantageous in that when simultaneously displaying a signal generated by a character generator or the like and the contents of an image memory, the image memory can be displayed at any location within the effective range of one display with the minimum image memory capacity. It is valid.

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[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a conceptual diagram showing the contents of the image memory 104 in FIG. Figure 4 is a conceptual diagram of the mask goo (106) shown in Figure 1, and Figure 5 is a conceptual diagram of the mask goo (106) shown in Figure 1.
FIG. 2 is a conceptual diagram showing the contents of an image output from the D/A converter 107 shown in the figure. 101...-Xi converter, 1o2... Write address generation circuit, 103... Read address generation circuit,
-104...Image memory, 105...Window key memory, 106...Mask goo), 107...
・Converter to ). Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. A write address generation circuit that accesses within the valid write range; a read address generation circuit that repeatedly accesses the valid write range; a window key memory having a capacity of the valid TV read range; and repeated access. and gate means for gating the write effective range based on the television read effective range.