JPS63153553U - - Google Patents
Info
- Publication number
- JPS63153553U JPS63153553U JP4836187U JP4836187U JPS63153553U JP S63153553 U JPS63153553 U JP S63153553U JP 4836187 U JP4836187 U JP 4836187U JP 4836187 U JP4836187 U JP 4836187U JP S63153553 U JPS63153553 U JP S63153553U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor
- semiconductor elements
- resistor
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図ａ，ｂ，ｃは本考案にかかる半導体集積
回路素子を示す図、第２図ａ，ｂは従来の半導体
集積回路素子を示す図である。
図において、１はシリコン基板、２は埋没層、
３はコレクタコンタクト領域、４はベース領域、
５はエミツタ領域、６は絶縁膜、７はＵ溝分離帯
、７１は絶縁膜、７２は多結晶シリコン層、１０
，１１は抵抗体の両端の電極、Ｃはコレクタ電極
、Ｂはベース電極、Ｅはエミツタ電極、を示して
いる。
1A, 1B and 1C are diagrams showing a semiconductor integrated circuit device according to the present invention, and FIGS. 2A and 2B are diagrams showing a conventional semiconductor integrated circuit device. In the figure, 1 is a silicon substrate, 2 is a buried layer,
3 is a collector contact area, 4 is a base area,
5 is an emitter region, 6 is an insulating film, 7 is a U-groove separation band, 71 is an insulating film, 72 is a polycrystalline silicon layer, 10
, 11 are electrodes at both ends of the resistor, C is a collector electrode, B is a base electrode, and E is an emitter electrode.
Claims (1)
体素子を分離しているＵ溝内の多結晶シリコン層
を、集積回路の抵抗体として構成せしめたことを
特徴とする半導体集積回路。 1. A semiconductor integrated circuit, characterized in that a plurality of semiconductor elements are provided on a semiconductor substrate, and a polycrystalline silicon layer in a U-groove separating the semiconductor elements is configured as a resistor of the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4836187U JPS63153553U (en) | 1987-03-30 | 1987-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4836187U JPS63153553U (en) | 1987-03-30 | 1987-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153553U true JPS63153553U (en) | 1988-10-07 |
Family
ID=30869819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4836187U Pending JPS63153553U (en) | 1987-03-30 | 1987-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153553U (en) |
-
1987
- 1987-03-30 JP JP4836187U patent/JPS63153553U/ja active Pending
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