JPS63151203A - Digital fm demodulator - Google Patents

Abstract

PURPOSE:To suppress the bit length of a counter to a required minimum value in response to the frequency deviation of an inputted FM signal and to simplify an address decoder by using a counter with an initializing data set function end setting a proper value as the initial value of the counter. CONSTITUTION:A quantized FM signal is given to a zero cross detector 3, where zero cross points are detected. Its detection signal (z) sets the initial value of a counter 4 with an initializing data set and inputted to a storage device as an output value (a) of the counter 4 just before the setting, that is, a load signal to store the period of the inputted FM signal or a measured value at a half period. Storage devices 6, 7 function similarly as conventional circuits. Thus, the scale of the address decoder circuit of the storage device converting a bit length of the counter 4, the period or half period measured value of the FM signal into a demodulated data is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital FM demodulation device that can be used to demodulate FM signals such as television audio multiplex signals.

BACKGROUND TECHNOLOGY 2 - 7 Conventionally, a zero crossing detection device detects a zero crossing point of a quantized FM signal, a counter directly measures a period or a half period from the output of the zero crossing detection device, and a counter of the counter. a first storage device that stores an output; a ROM that uses the output value of the first storage device as an address value;
There have been digital FM demodulators with a second storage device for storing the output of the OM. Below, referring to the drawings,
The digital FM demodulator as described above will be explained.

FIG. 3 is a block diagram showing the circuit configuration of a conventional digital FM demodulator. FIG. 4 is a timing chart showing the zero-crossing detection signal output from the zero-crossing detection device and changes in the value of the counter.

In Figure 3, 11 is an input terminal, 12 is an output terminal, 1
3 is a zero crossing detection device, 14 is a counter with a reset function,
16 is a first storage device; 16 is a ROM;

17 is a second storage device.

The quantized FM signal is input to a zero crossing detection device 13 via an input terminal 11, and a zero crossing is detected (3t, -7). The zero crossing detection signal 2 output from the zero crossing detection device 13 resets the counter 14. i.e. counter 1
4 to zero, and is input to the first storage device 15 as a load signal for storing the output value A1 of the counter 14 immediately before reset, that is, the measured value of the cycle or half cycle of the input FM signal. Ru. Data D corresponding to the value A stored in the first storage device 15 is stored in the ROM 16.
The output value of the ROM 16 is stored in the second storage device 1 at a timing corresponding to the output of the zero crossing detection signal Z.
7 and the output of the second storage device 17 is output to the output terminal 1.
It is extracted from 2.

Further, as shown in FIG. 4, the counter 14 changes its value every cycle of the master clock that operates the counter 14 from when it is reset when the zero-crossing detection signal is output until when the next zero-crossing detection signal is output. Increase by 1.

Problems to be Solved by the Invention However, in the digital FM demodulator described above,
As shown in Figure 4, the counter value starts from zero and the next zero crossing detection signal is output by counting.
Since the cycle or half cycle of the input FM signal is measured, the problem is that the bit length of the counter used for measurement and the address decoder of the ROM associated with it become large.

The present invention has been made in view of the above problems, and uses a counter with an initialization data set function and sets an appropriate value as the initial value of the counter, thereby adjusting the bit length of the counter to the value of the input FM signal. In addition to keeping the size to the minimum necessary according to the frequency deviation width, the address of the storage device that converts measured values to demodulated data, which conventionally uses ROM, can be started from any value, simplifying the address decoder. The present invention provides a digital FM demodulator that can perform the following functions.

Means for Solving the Problems To achieve this objective, the digital FM demodulator of the present invention includes a zero-crossing detection device for detecting zero-crossing points of a quantized FM signal, and an output of the zero-crossing detection device. Based on the signal, the period of the FM signal or 5, heh.

is a counter with an initialization data set function for measuring a half cycle, and a first counter for storing the output of said counter.
a second storage device that takes the output value of the first storage device as an address value and outputs data corresponding to the address value; and a third storage device that stores the output value of the second storage device. , and is configured to take out the output value of the third storage device from the output terminal.

According to the present invention, the circuit of the address decoder of the counter storage device can be simplified and the scale can be reduced by the above-described configuration.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a digital FM demodulator according to an embodiment of the present invention. FIG. 2 shows a zero-crossing detection signal output from a zero-crossing detection device,
This is a timing nayat indicating a change in the value of a counter.

In Figure 1, 1t/i input terminal, 2 is output terminal, 6
,,-/ 3 is a zero crossing detection device, 4 is a counter with an initialization data set, 5 is a first storage device, 6 is a second storage device, 7
is the third storage device. The quantized FM signal is input to a zero crossing detection device 3 via an input terminal 1, and zero crossing points are detected. The zero crossing detection signal 2 output from the zero crossing detection device 3 sets the initial value of the counter 4, and also sets the output value a1 of the counter 4 immediately before setting, that is, the input FM
It is input to the first storage device 5 as a load signal for storing the measured value of the period or half period of the signal. 1st
Data d corresponding to the value a stored in the storage device 5 is output from the second storage device 6, and the output value d of the second storage device 6 is outputted at a timing corresponding to the output of the zero crossing detection signal 2. The data is stored in the third storage device 7, and the output of the third storage device 7 is taken out from the output terminal 2. In addition, the counter 4 is
When the zero crossing detection signal is not output, the master clock 1. which operates the counter 4. Increase the value by 1 every cycle.

Now, if the frequency of the FM signal is within the range fs±Δf8, 7 1
,-.

The master clock frequency that operates the counter 4 changes to f. If this is the case, when the period is directly measured as in the conventional example, a counter that can count up to at least Cmax-fC/(rS-ΔfS) is required. Also, Cm
Since a count value less than 1n'' fc/(fs+△f8) has no meaning, a ROM for this portion is unnecessary, but as an address decoder, a focus number corresponding to the maximum value of the counter is required.

On the other hand, the counter in this embodiment has at least C=f
If o/(2, Δfs) has a bit length that can be counted, and the maximum number of counts that can be counted with that bit length is C', then, for example, n*c'+(c'-X)=fo/(fS+AfS ), if (C'-x) is the initialization data for count 4, then
When the maximum frequency of the FM signal is fs+Δfs, the count value becomes zero, and the address of the second storage device 6 that outputs demodulated data corresponding to the measured value of the period or half period of the FM signal also starts from zero, The maximum value is C'. however,
In the above equation, n is an integer, and is the value obtained by subtracting 1 from m, the number of times the counter 4 overflows and the counter value increases again from zero in FIG.

Effects of the Invention The present invention provides a zero-crossing detection device for detecting zero-crossing points of a quantized FM signal, and an initial stage for measuring the period or half period of the FM signal based on the output signal of the zero-crossing detection device. a counter with a data set function; a first storage device for storing the output value of the counter; the output value of the first storage device is taken as an address value, and data corresponding to the address value is outputted. a second storage device;
a third storage device for storing the output value of the storage device;
By configuring the output of the third storage device to be taken out from the output terminal, the address 9 of the storage device that converts the bit length of the counter and the measured value of the period or half period of the FM signal into demodulated data 8-7 The scale of the decoder circuit can be reduced. Further, the present invention provides F
This is particularly effective for demodulating TV audio multiplex broadcasting where the carrier frequency of the M signal is low and the frequency shift width is relatively small.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital FM demodulator according to an embodiment of the present invention, Fig. 2 is a timing chart showing changes in the zero crossing detection signal and the counter, and Fig. 3 is a block diagram of a conventional digital FM demodulator. , FIG. 4 is a timing chart showing changes in the zero crossing detection signal and the counter. 1...Input terminal, 2...Output terminal, 3
. . . Zero crossing detection device, 4 . . . Counter with initialization data set, 5 . . . First storage device, 6 . . . Second storage. Device, 7...
Third storage device.

Claims (1)

[Claims] A zero crossing detection device for detecting zero crossing points of a quantized FM signal, and a counter with an initialization data set function for measuring the period or half period of the FM signal based on the output signal of the zero crossing detection device. a first storage device that stores the output value of the counter; a second storage device that takes the output value of the first storage device as an address value and outputs data corresponding to the address value; and a third storage device that stores the output values of the second storage device.
Demodulator.