SU1628217A2 - Digital frequency-shift demodulator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the accuracy of demodulation by detecting a priori information about the amplitude of the received signal. For this, the device contains a controllable key 1, ADC 2, registers 3, 4, 5, 6 and 24 shift, pulse generator 7, multipliers 8 and 11 into two, adders 9, 10 and 21, prohibition blocks 12 and 13, block 14 determining the modulus of the number, digital comparator 15, divider 16, decoding unit 17, subtracting unit 18, divider 19 by two. In addition, the device includes quadrants 20 and 30, a decoder 22, multipliers 23 and 26, a delay unit 25, a cosine converter 27, keys 28, 31 and 34, an OR element 29, a counter 32, an inverter 33 and a storage unit 35. The device for five polling intervals enter the operating mode at which the threshold of operation of the digital comparator 15 becomes optimal due to the adjustment of this threshold at each interval, 1 or 0 and 0 s

Description

The invention relates to radio engineering, can be used in receivers of discrete information.

The purpose of the invention is to increase the accuracy of demodulation by identifying a priori information about the amplitude of the received signal.

The drawing shows a structural electrical diagram of the proposed device.

The device contains a controlled key 1, ADC 2, the third, first, second, fourth shift registers 3-6, the pulse generator 7, the first multiplier 8 by two, the first, second adders 9, 10, the second multiplier 11 by two, the first, second blocks 12, 13 prohibition, block 14 determining the number module, digital comparator 15, divider 16, decoding block 17, subtracting block 18, divider 19 by two, first square 20, third adder 21, decoder 22, first multiplier 23, fifth shift register 24 , delay unit 25, second multiplier 26, cosine converter 27, first key 28, element OR 29, a second quadrator 30, a second key 31, a counter 32, an inverter 33, a third key 34, a storage unit 35.

The device operates as follows.

With the arrival of the next strobe at the device’s inlet for five polling intervals, the device enters the operating mode. Upon entering the operating mode, the results of calculating the frequency f appearing at the output of the device will be unreliable, and, therefore, the formation of values | cos 2 (? f / f _a /, which participate in the formation of the threshold of the digital comparator 15, is unacceptable. The counter 32 is set to the zero position by the front of the sync gate and starts counting the clock pulses received at the input of the account through the key 31 opened by the sync gate). Until the counter 32 is full at its output there is a low potential that _e passing inverter 33 opens switch 34. a value written in the memory unit 35 through the switch 34 and the OR gate 29 is supplied to a second input of the multiplier 23. ₍

At the same time, the signals!. · V and V from the outputs of shift registers 3 and 5 are fed to the second input (decremented) and the first input of the (subtracted) subtractive unit 18. The resulting difference after dividing by two in divider 19 by two and squaring in squared 20 as a signal. 2.

And _c is fed to the first input of the adder 21. The second input of the third adder 21 receives the signal A ^, which is formed in the quadrator 30 from the sample V] supplied to its input from the output of the shift register 4. The sum A ^ + Ad is fed to the input of the decoder 22, from the output of which the signal A ₀ * k goes to the first input of the multiplier 23. At the output of the multiplier 23, a threshold value h = kA _a £ appears, which is written down by the delayed time for calculating h in the delay block 25 a clock pulse to the shift register 24 and is fed from its output to the second input of the digital comparator 15. Thus, when entering the operating mode in the threshold expression in each clock cycle, only the value A _{о <} will change. After filling the shift registers 3-6 with samples Vj, the value of A _о will correspond exactly to the amplitude of the received signal, therefore, all calculations of the frequency f, starting from the fifth interval Т _о , performed under the condition + V ^ (> h, will be reliable, but in them the error due to the non-optimal threshold h will also be contained (£ differs from / cos2 "fT _b /). By this time, counter 32 is filled (its capacity is selected so that the output signal appears after a number of clock cycles of no less than five, for example , 8), appearing on its output high potential, which, having passed the inverter 33, closes the key 34 and opens the key 28. In the future, this position of the keys is maintained until the front of the next sync gate arrives, that is, until the next information symbol is received. cos2HfT ₀ |, which is formed from the output signal of the device f using the multiplier 26 and the cosine converter 27. The signal j cos2 "fT ₀ | the key 28, the OR element 29 passes sequentially and is fed to the second input of the multiplier 23 instead of the signal (5 · Therefore, in the future, the threshold of the digital comparator 15 will be optimal->

1628th The correction of the threshold h will be made at each interval T _in . Moreover, the comparison of the value of [V _z + + [in the current interval T _{about is} made with a threshold h formed according to the results of the previous polling interval.

Claims (1)

Claim Device for demodulation of digital signals with frequency modulation by autosw. No. 1552397, characterized in that, in order to improve the accuracy of demodulation by identifying a priori information about the amplitude of the received signal, a subtracting unit, a divider by two, a first quadrator, a third adder, a decoder, a first multiplier and a fifth shift register are connected in series, connected in series second multiplier, cosine, converter, first key and OR element connected in series! 17 second key, counter, inverter and third key, as well as a delay unit, a second quadrator and a storage unit, moreover, the output of the pulse generator is connected to the first input of the second key and through the delay unit with the second input of the fifth shift register, the output of which is connected to the second input of the digital comparator, the output of the decoding unit is connected to the input of the second multiplier, the output of the storage unit through the third key is connected to the second input of the element OR, the output of which is connected to the second input of the first multiplier, the output of the third; the shift register is connected to the first input of the subtracting unit, the second input of which is connected to the output of the second shift register, the output of the first shift register through the second quadrator is connected to the second input of the third adder, the counter output is connected to the second input of the first key, the second 25 inputs of the second key and counter are the sync input of the device.