JPS61192105A - Digital fm demodulator - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by constituting the title demodulator with a counter measuring the period or half period of an FM signal, a storage device storing the counter output, a ROM having an output of the storage device as the address and a storage device storing the output of the ROM. CONSTITUTION:A zero cross detection output signal clears the counter 2 and a storage device 3 stores the count just before the counter is cleared. The stored value is given as the address of the ROM 4. A data corresponding to the address is written in addvance in the ROM 4. Thus, a demodulated output is obtained from the ROM 4 when the address is given. In order to eliminate the distortion in the demodulation output, storage devices 7a, 7b, 7c are provided and the zero cross detection output signal is frequency-divided by a frequency division circuit 10 to generate W1, W2, W3 as the write timing. Read signals R1, R2, R3 are formed by retarting the W1, W2, W3 at a counter 11 by Td and fed to an output enable terminal of tri-state buffers 8a, 8b, 8c. Then the data in the W1 is read by the R3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital FM demodulator that can be used to demodulate an FM signal of a television audio multiplex signal.Prior Art Generally, analog television audio multiplexing These methods can also be used in digital signal processing of OFM demodulation, in which the PLL method and the pulse count method are used as demodulation methods for FM signals.

Problems to be Solved by the Invention However, in the FMgMg method, in the PLL system, the limiter can be easily constructed using analog technology, but in the digital system, the limiter is complicated because the signal is integrated. If you try to obtain the S/N ratio, you will need large hardware, and in the pulse counting method, as shown in Figure 3, the output of the mono multivibrator 6 triggered by the output of the zero cross detector 1 will be lowered. A bass filter (LPF) e is used to obtain a filter t and a terrobit output, but since this low-pass filter 6 filters a 1-bit signal, a large-scale filter is required. In this way, any method has the disadvantage that the hardware becomes large when trying to obtain the necessary S/N ratio and distortion characteristics.The present invention eliminates such disadvantages and uses relatively simple hardware. The present invention provides a digital FM demodulator that can be configured using hardware.

Means for Solving the Problems The digital FM demodulator of the present invention includes a counter that measures the period or half period of an FM signal by counting clocks, and temporarily stores the output of this counter. It is composed of a storage device, a ROM whose address is the output of the storage device, and a multi-word storage device that stores the output of the ROM.

Function: The digital FM demodulator of the present invention measures the cycle using a counter, converts this value directly into a demodulated output in a ROM, and sequentially stores the demodulated output in a storage device of at least 2 words or more. The stored data is controlled and read out at correct time intervals, and the distortion rate of the FM demodulated signal can be reduced.

Embodiment A digital FM demodulator according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the zero-cross detector 1 outputs a zero-cross detection output signal as shown in FIG. 2 when the FM signal passes through an AC zero point.

This signal is given to counter 2 and clears counter 2, but at the same time it is also connected to storage device 3, so
The storage device 3 stores the value of the counter 2 immediately before the counter 2 is cleared. Since the value stored in the storage device 3 indicates the half period of the FM signal counted by the clock f, this value is given as the address value of the ROM 4. R.O.
Data for the address is written in M4 in advance, for example, the address value is A, the output data is D,
If the carrier of the FM signal is f and the maximum frequency deviation of the FM signal is fd, then if the value of the relationship D=(f/2A-1,)/fd is written in ROM4, the address A
If is given, a value normalized to ±1 is taken out as a demodulated output as a ROM output. However, as shown in Figure 2, the ROM output corresponding to the T1 period is D
l, T2 is delayed with respect to Tn, such as D2, and the delay time is not constant (it depends on the period of the FM signal, so if the ROM output is used as the demodulated output, distortion will increase. To eliminate this drawback, ROM4
There are three storage devices 7a in the rear stage.

7b and 7a are connected, and the zero-cross detection output signal is frequency-divided by the frequency dividing circuit 10 to set the write timing to the storage device. W2. Create W3 and use this signal to write memory device 7a.
, yb.

7C, the read numbers are Wl, W2. W3 is delayed by Td by each counter 11 and R1, R'2 . R
3) is applied to the output enable terminals of the three-state buffers sa, ab, and ac connected to the outputs of the storage devices 7a, 7b, and 7c, but at this time, the data written in Wl is read out in R3, and the data written in W2 is If R4 and W3 are shifted such as R2, the demodulated output will be delayed by Td, but it will no longer depend on the period of the FM signal, so no distortion will occur.

Here, three storage devices 7a, 7b, and 7c are used, and if this number is N, the minimum value of N is the maximum frequency deviation fd of the FM signal and the carrier frequency f. , and N takes a value within the range of the following formula.

N> (fc+fd)/(fo-fd) In the TV audio multiplex signal, fd=10 KHz, fc=31
．． Since it is 468 KHz, N) is 1.93, but N=a is set in consideration of overmodulation.

In the embodiment shown in FIG. 1, the storage device? a, 7b.

Although it is placed on the output side of the 7ct t-ROM 4, the same effect can be achieved on the input side (address side) of the ROM 4 using a similar concept.

Effects of the Invention As described above, the digital FM demodulator of the present invention can
It consists of a storage device that stores the output value of a counter that measures the period of the signal, a ROM connected to this, and a multi-word storage device connected to the ROM output. The demodulated output can be directly obtained and the distortion of the demodulated output can be reduced.

[Brief explanation of the drawing]

FIG. 3 is a block diagram of a conventional pulse count type FM demodulator. 1...Zero cross detector, 2...-Counter, 3...Storage device, 4...-RO
M, 5... Mono multivibrator, 6...
...Low pass filter, 7a. Yab, 7c...Storage device, 8a, ab, 8
c... Three-state buffer, 9...
・・Storage device, 1゜・・・・Frequency dividing circuit, 11・・・・
...Name of Counter 0 Agent Patent Attorney Toshi Nakao I'! Figure 1j, 744. (7--- 11 is also 1.1tfjtL=
Bc-・-three chi Y) 1゛・ノ7a11・-η
Kunter

Claims (2)

[Claims] (1) A storage means for storing the output of a counter that measures the period or half period of a quantized FM signal, and a ROM whose address value is the output value of the storage means are provided, and the output data of the ROM is stored. Digital FM demodulator with multiple word storage. (2) A digital FM demodulator according to claim 1, wherein a plurality of word storage device for storing output data of the ROM is disposed at the input stage of the ROM to store address values of the ROM.