JPS63148650A - Face-down bonding - Google Patents
Face-down bondingInfo
- Publication number
- JPS63148650A JPS63148650A JP29713486A JP29713486A JPS63148650A JP S63148650 A JPS63148650 A JP S63148650A JP 29713486 A JP29713486 A JP 29713486A JP 29713486 A JP29713486 A JP 29713486A JP S63148650 A JPS63148650 A JP S63148650A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip element
- infrared
- bonding
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000005855 radiation Effects 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000002594 fluoroscopy Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75283—Means for applying energy, e.g. heating means by infrared heating, e.g. infrared heating lamp
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
リード端子をもたないリードレスチップに組立てられた
ＩＣチップ素子と、これを実装する回路基板との接合に
用いられるフェースダウン方式は。[Detailed Description of the Invention] [Summary] The face-down method is used to bond an IC chip element assembled into a leadless chip that does not have lead terminals and a circuit board on which it is mounted.
ボンディング時の位置合わせが困難なことから赤外線に
よる透視法を用いてＩＣチップ素子の位置決めをするこ
とによって該素子と回路基板相互間の位置合わせを容易
とするものである。Since positioning during bonding is difficult, by positioning the IC chip element using infrared perspective, it is possible to easily align the IC chip element and the circuit board.
本発明は、フリップチップの接続方法に係るフェースダ
ウンボンディング法に関する。The present invention relates to a face-down bonding method related to a flip chip connection method.
フリップチップ組立になるＩＣチップ素子は１Ｍ面側に
導出されたはんだ付は用バンプ電極（またははんだ付は
パッド電極）と回路基板側の同接続用バンプ形成部を対
接させてはんだ付けする。かような素子実装方法はチッ
プ内の接続配線及び回路基板側との接続配線長が短いこ
とによる高速化が図られること、実装スペースが小さく
、また実装コストが低い等の利点があることから、近時
の高速・高密度実装が要求される中央処理装置の回路組
立技法として広く使用されている。The IC chip element to be assembled by flip chip is soldered by bringing the soldering bump electrode (or soldering pad electrode) led out on the 1M surface into contact with the connection bump forming portion on the circuit board side. This element mounting method has advantages such as high speed due to short connection wiring within the chip and connection wiring to the circuit board side, small mounting space, and low mounting cost. It is widely used as a circuit assembly technique for modern central processing units that require high-speed, high-density packaging.
第３図はＤＩＰ型、ＴＯ−５型フラツトパツケージ構造
のＩＣチップの断面図である。FIG. 3 is a sectional view of an IC chip having a DIP type or TO-5 type flat package structure.
従来構成のパンケージは、金属のフレーム２４と上蓋２
５で気密封止されたセラミック筐体２０の内部に取付け
られたＩＣチップ２１に対してボンディングワイヤ２２
の装着やメタライズ電極の形成等にパッケージコストが
高く、またこれを実装する回路基板は、リード端子２３
に対する接続用ホールを必要とするため回路基板の配線
収容能力が限定される。The conventional pan cage has a metal frame 24 and an upper lid 2.
The bonding wire 22 is connected to the IC chip 21 mounted inside the ceramic casing 20 which is hermetically sealed at 5.
The package cost is high due to the installation of the lead terminal 23 and the formation of the metallized electrode, and the circuit board on which this is mounted is not suitable for the lead terminal 23.
Since a connection hole is required for the circuit board, the wiring capacity of the circuit board is limited.
このため、第４同断面図に示す如きフリップチップ接合
が用いられる。For this reason, flip-chip bonding as shown in the fourth cross-sectional view is used.
【Ｃチップ素子１５には、はんだ付は用バンブ電極１４
が裏面に形成され、該電極１４と５回路基板１０側の突
起電極１２とを対接せしめてリフロー加熱法によっては
んだ付けがされる。[The C-chip element 15 has a bump electrode 14 for soldering.
is formed on the back surface, and the electrode 14 and the protruding electrode 12 on the side of the fifth circuit board 10 are brought into contact with each other and soldered by a reflow heating method.
フリップチップ接合によるボンディング時において、
ＩＣチップ素子１５のバンプ電極１４ならびに対接する
突起電極１２間の位置決めが、直接、目視または顕微鏡
視野に入らない。このためボンディング接合前、予め設
けた位置合わせマークを用いて。When bonding by flip chip bonding,
The bump electrodes 14 of the IC chip element 15 and the positioning between the opposing protruding electrodes 12 are not directly within the visual or microscopic field of view. For this reason, use pre-prepared alignment marks before bonding.
先ず顕微鏡の視野内に１回路基板上の位置合わせマーク
によって該基Ｆｉ、１０を位置付けし１次いでその位置
に基づいて該基板１０上に移送されたＩＣチップ素子１
５の素子背面側の位置合わせマークを照合することによ
って位置決めする。該照合による位置決めは、精度の高
い機械的送り装置等が必要となる。First, the substrate Fi, 10 is positioned within the field of view of a microscope by the alignment mark on the circuit board, and then the IC chip element 1 is transferred onto the substrate 10 based on the position.
Positioning is performed by comparing the alignment marks on the rear side of the element No. 5. Positioning based on this verification requires a highly accurate mechanical feed device or the like.
本発明はチップ素子１５と回路基板ＩＯの相互を直接、
光学的に位置決めを行うことである。The present invention directly connects the chip element 15 and the circuit board IO to each other.
This is to perform positioning optically.
第１図は本発明の基本的構成手段を示す斜視図である。 FIG. 1 is a perspective view showing the basic constituent means of the present invention.
図において
赤外線に対し透光性のチップ形成基板２と該基板２から
導出される不透光性パッド電極３を備えるＩＣチップ素
子１と、該チップ素子１を搭載する回路基板１０．の相
対的位置決めを赤外線透視による検知手段で行い、然る
後、フェースダウンボンディングするものである。In the figure, an IC chip element 1 includes a chip forming substrate 2 that is transparent to infrared rays, a non-transparent pad electrode 3 led out from the substrate 2, and a circuit board 10 on which the chip element 1 is mounted. The relative positioning of the two is performed using a detection means using infrared fluoroscopy, and then face-down bonding is performed.
相対的位置決めがＩＣチップ素子を透光する赤外線によ
って、該素子裏面側の不透光性パッド電極のパターンが
透視されること、併せてパッド電極と当接させる突起電
極も透視されるので、従来。For relative positioning, the pattern of the non-transparent pad electrodes on the back side of the IC chip element can be seen through by the infrared rays that pass through the IC chip element, and the protruding electrodes that come into contact with the pad electrodes can also be seen through, which is different from conventional methods. .
必要とされた高精度の機械的送り装置が不要となる。従
ってボンディング時の相対的位置決めが極めて簡易にか
つ安価に行うことが出来る。The required high precision mechanical feed device is no longer required. Therefore, relative positioning during bonding can be performed extremely easily and at low cost.
第１図のフリップチップ等を形成するチップ形成基板２
としては赤外線に対して透明または透光性の砒化ガリウ
ム（ＧａＡｓ） 、あるいはシリコン（Ｓｉ）等の厚さ
０．５ｍｍ〜１ｍｍ程度の基板が用いられる。Chip forming substrate 2 for forming the flip chip etc. shown in Fig. 1
As the substrate, a substrate having a thickness of about 0.5 mm to 1 mm, such as gallium arsenide (GaAs) or silicon (Si), which is transparent or transparent to infrared rays, is used.
る従来のシリコン系基板もまた赤外線に対して透光性が
ある。Conventional silicon-based substrates are also transparent to infrared rays.
そして、該チップ形成基板２から導出されるクロム（Ｃ
ｒ）電極パッドは厚さ約５０μｍの低融点はんだが被着
されて、矢印方向の赤外線４に対して不透光性となる。Then, chromium (C
r) The electrode pad is coated with a low melting point solder having a thickness of about 50 μm, making it opaque to infrared rays 4 in the direction of the arrow.
即ち、素子表面側からの赤外線によってパッド電極３を
透視することが出来る。That is, the pad electrode 3 can be seen through by infrared rays from the element surface side.
以下、フェースダウンボンディング時、赤外線透視を顕
微鏡によって、 ＩＣチップ素子１の回路基板上の位置
決め実施例について第２図を参照して説明する。Hereinafter, an example of positioning the IC chip element 1 on the circuit board during face-down bonding using an infrared ray microscope will be described with reference to FIG.
第２図装置はその構成として、光源７を備える赤外線顕
微鏡８．該顕微鏡８によるパッド電極３の透視パターン
を可視像に変換する赤外線カメラ９、及び！！２置され
た回路基板１０の位置を制御するためのＸＹ座標テーブ
ル６から構成される。The apparatus shown in FIG. 2 has the following configuration: an infrared microscope 8 equipped with a light source 7; An infrared camera 9 that converts the see-through pattern of the pad electrode 3 by the microscope 8 into a visible image, and! ! It is composed of an XY coordinate table 6 for controlling the position of two circuit boards 10 placed therein.
赤外線顕微鏡８はフェースダウンしたＩＣチップ素子１
のパッド電極３．該電極３に対接する回路基板１０側の
突起電極との相互パターンを検知する。The infrared microscope 8 shows the IC chip element 1 face down.
Pad electrode 3. A mutual pattern between the electrode 3 and the protruding electrode on the side of the circuit board 10 that is in contact with the electrode 3 is detected.
赤外線カメラ９は前記検知のパターンは目視像に変換す
る。The infrared camera 9 converts the detected pattern into a visual image.
そしてＸＹ座標テーブル６は、吸着保持具５で把持する
ｒｃチップ素子１に対して回路基板１０を移動させて相
互パターンの位置合せを目視によって行う。回路基板１
０とＩＣチップ素子１の目視による位置合わせは、単素
子光たり、少なくとも二回行う必要がある。Then, the XY coordinate table 6 moves the circuit board 10 relative to the rc chip element 1 held by the suction holder 5, and visually aligns the mutual patterns. circuit board 1
The visual alignment of the IC chip element 1 and the IC chip element 1 needs to be performed at least twice with a single element beam.
前記の位置合わせ後、チップ素子１は仮止めされ、この
後リフロー加熱炉によるはんだ付は接続となる。After the above alignment, the chip element 1 is temporarily fixed, and then soldered in a reflow heating furnace for connection.
本発明のフェースダウンポンディング実施例によれば、
ＩＣチップ素子の表面からの赤外線によって、該素子
裏面側の不透光性パッド電極のパターンが透視されるこ
と、併せてパッド電極と当接させる突起電極も透視され
ることから、従来２問題とされた高精度の機械的位置決
め装置が不要となる。従ってＩＣチップ素子の基板実装
が極めて筒易に行われる。According to a face-down pounding embodiment of the invention:
The infrared rays from the surface of the IC chip element can see through the pattern of the non-transparent pad electrode on the back side of the element, and also see through the protruding electrodes that come into contact with the pad electrode. This eliminates the need for highly accurate mechanical positioning devices. Therefore, the IC chip element can be mounted on the board extremely easily.
第１図は本発明の基本的構成手段を示す斜視図。 第２図はＩＣチップ素子の位置決め実施例図（側面図） 第３図はフラットパッケージ構造のＩＣチップ断面図。 第４図はフリップチップ接合の断面図。 図中、ｌはＩＣチップ素子、２はチップ形成基板。 ３は不透光性のパッド電極。 ４は赤外線。 及び１０は回路基板である。 ＩＣカノヂ素干ｑ４立置ンξ、ρ東施例圀享２ 図 FIG. 1 is a perspective view showing the basic constituent means of the present invention. Figure 2 is an example of positioning the IC chip element (side view) Figure 3 is a cross-sectional view of an IC chip with a flat package structure. FIG. 4 is a cross-sectional view of flip-chip bonding. In the figure, 1 is an IC chip element, and 2 is a chip forming substrate. 3 is a non-transparent pad electrode. 4 is infrared. and 10 is a circuit board. IC Kanoji plain drying q4 standing ξ, ρ east example area 2 diagram
Claims (1)
２）から導出される不透光性のパッド電極（３）をそな
えるＩＣチップ素子（１）と、ＩＣチップ素子（１）を
搭載する回路基板（１０）、の相対的位置決めを赤外線
（４）による透視手段により行った後、接合することを
特徴とするフェースダウンボンディング法。A chip-forming substrate (2) that is transparent to infrared rays and the substrate (
The relative positioning of the IC chip element (1) equipped with the non-transparent pad electrode (3) derived from 2) and the circuit board (10) on which the IC chip element (1) is mounted is performed using infrared rays (4). A face-down bonding method characterized by bonding after bonding is performed using a see-through method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29713486A JPS63148650A (en) | 1986-12-12 | 1986-12-12 | Face-down bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29713486A JPS63148650A (en) | 1986-12-12 | 1986-12-12 | Face-down bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63148650A true JPS63148650A (en) | 1988-06-21 |
Family
ID=17842648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29713486A Pending JPS63148650A (en) | 1986-12-12 | 1986-12-12 | Face-down bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63148650A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169034A (en) * | 1987-01-07 | 1988-07-13 | Hamamatsu Photonics Kk | Semiconductor device assembling apparatus |
| JPH0518189U (en) * | 1991-08-13 | 1993-03-05 | 日本電子精機株式会社 | Mounting microphone for Hermet |
-
1986
- 1986-12-12 JP JP29713486A patent/JPS63148650A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169034A (en) * | 1987-01-07 | 1988-07-13 | Hamamatsu Photonics Kk | Semiconductor device assembling apparatus |
| JPH0518189U (en) * | 1991-08-13 | 1993-03-05 | 日本電子精機株式会社 | Mounting microphone for Hermet |
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