JPS63147274A - Data processing system - Google Patents

Abstract

PURPOSE:To process data with large capacitance at high speed by using a means which stores the input data of the fixed word length read out of a write/ read enable memory and a data processing means. CONSTITUTION:The input data of the fixed word length read out of a write/read enable memory is stored in an input data storing means 6. This input data is held by the means 6 until it undergoes the magnifying, thinning and other processes through a data processing means 1. The processed data is stored in a 1st output data storing means 3 by an amount equal to the fixed word length, while the data exceeding the fixed word length is stored in a 2nd output data storing means 4 respectively. A selection means 5 selects the data stored in both means 3 and 4. These selected data are merged with the data processed by the means 1 by a merging means 2. Thus the data with the large capacitance can be processed at high speed.

Description

[Detailed Description of the Invention] [Summary] The present invention includes input data storage means, and selects the data stored in two output data storage means before writing the data into memory and merges the data with new data. By doing this, data processing can be performed in a pipeline manner by accessing the memory for each fixed word length. Therefore, large amounts of data such as image data can be processed at high speed and without being affected by the bit position.

[Industrial application field]

The present invention relates to a data processing system, and in particular, each bit information of image data, image data, etc. stored in a writable/readable memory has a meaning. The present invention relates to a data processing method that processes data (different from code information in units of multiple bits) by moving, enlarging, thinning, etc. in units of a fixed word length.

[Conventional technology]

Conventionally, in the data processing method described in Japanese Patent Publication No. 61-29016, for example, a data shift processing means is used to move (shift) input data of a fixed word length read from a writable/readable memory, as schematically shown in FIG. 51, and first and second data storage means 52 and 53 connected in series to each other for storing the moved data in units of fixed word length.
and a selection means 54 that selects data stored in the storage means 52, 53 and writes it into the writable/readable memory.

In this method, when data recorded in a read/write memory in units of fixed word length is moved to the middle of the fixed word length, a fixed word containing the data to be moved recorded in the memory is used. The length data is read out from the memory in units of word length.

The read data is shifted by a predetermined number of bits by the data shift processing means 51. Generally, when moving data of a certain word length, storage means for at least two word lengths are required, and the moved data is stored in the first data storage means 52 and the second data storage means 53 connected in series. It is divided and stored. Thus, the first and second storage means 52.
One of the 53 divided data is selected by the selection means 54 and sequentially written into the write/readable memory.

[Problem that the invention seeks to solve]

By the way, in the conventional data processing method, data of a fixed word length that has been moved is stored in the first and second data storage means 52 and 53 for two word lengths, and these data can be written and read every fixed word length. Since the in-memory processing means 51 can only move in units of a fixed word length, if the object to be moved exceeds the fixed word length, it is necessary to move the word a plurality of times and sequentially write it into the memory. That is, when the shift processing means 51 moves the data for the initial fixed word length, the data after the movement is stored in the first and second data storage means 52.
．． After being divided into 53 parts and stored, each part is written to the memory. Subsequently, the shift processing means 51 performs a second shift processing for a certain word length.

When the movement is performed, the data for a certain word length that was stored in the second data storage means 53 and written to the memory by the first movement is read again in order to connect the first movement and the second movement. The data is read out, combined with the data generated by the second movement, and written into the memory again as data with a constant word length.

As described above, in conventional data processing methods, when moving data exceeding a certain word length, data at the same address must be read or written redundantly from read/write memory, which is an inconvenience. occurs.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and is intended to provide a data processing method that does not require redundant accesses from readable/writable memory. .

[Means for solving problems]

As shown in FIG. 1, the present invention is a data processing method that uses a writable and readable memory to process data in units of predetermined word length. An input data storage means 6 for storing input data, a data processing means 1 for processing the data such as enlarging, thinning, moving, or a combination thereof, and processing the processed data for each word length unit. a first output data storage means 3 for storing, a second output data storage means 4 for storing a certain word length exceeding a certain word length caused by processing by the data processing means l, and a first or second output It comprises at least a selection means 5 for selecting data stored in the data storage means 3.4, and a merging means 2 for merging the data selected by the selection means 5 and the data processed by the data processing means 1. The data stored in the output data storage means 4 of 1 can be written into the memory.

[Effect]

In the present invention, input data of a fixed word length read from the readable/writable memory is stored in the input data storage means 6, and the input data is moved by the data processing means l (
shift) or expand the data (for example, data 101 to 2
Double expansion means 110011), thinning! i(
For example, data of 11101 is stored in the input data storage means 6 until it is processed such as 101) or a combination thereof. In other words, if the word length of the processed data exceeds a certain word length due to processing such as enlarging or enlarging the input data, multiple processing steps will be performed on the input data until the data to be finally written to the memory is determined. In the present invention, the data in the input data storage means 6 is held and the processing is performed on the data until the processing on the data is completed. This is not necessary; in this way, arbitrary processing of the data can be performed in one readout.

A certain word length of the processed data is stored in the first output data storage means 3, and a certain word length exceeding the certain word length is stored in the second output data storage means 4. if,
If the word length of the data after processing is large and the content of the data to be finally written to the memory cannot be determined by only one processing, the second processing is performed consecutively after the first processing.・It is necessary to perform processing such as. At this time, the data stored in the first output data storage means 3, which has already been determined, is recorded as is in the memory. In addition, when performing the second processing, the selection means 5 is set to 1 in order to connect the data.
The data stored in the second data storage means 4 is selected by the second processing, and the data processing means 1 selects the data stored in the second data storage means 4.
The merging means 2 merges the newly processed data with the data to be stored in the first output data storage means 3 and sends it to the first output data storage means 3. The data stored in the second output data storage means 4 is written to the memory, and the data stored in the second output data storage means 4 that exceeds a certain word length is written to the memory. It is merged with the data by the merging means 2 and sent to the first output data storage means 3. In this way, depending on the type of processing,
Even if a third, fourth, etc. processing is required, by repeating the above steps sequentially, you can avoid duplication from the same location (address) in the memory for any processing. Data can be processed without performing read/write operations.

On the other hand, since data processing such as thinning and movement was performed by the data processing means l, the word length of the data after processing was too small to reach a certain word length with just one processing, so the final There may be cases where the contents of data to be written into memory are not determined. In such a case, the selection means 5 selects the data stored in the output data storage means 3 of ml, and the new input data is merged with the merging means 2 until the word length of the data reaches a certain word length. If writing is performed after this, the 35 lengths can be read and written at once without duplication.

〔Example〕

Next, embodiments according to the present invention will be described.

FIG. 2 shows the data processing system according to this embodiment.

It is assumed that the data processing according to this embodiment is performed using a constant word length of, for example, 8 bits or 16 bits.

(Configuration of the embodiment) The wooden sword type includes data processing means 1, merging means 2, output data storage means 3 of :5f, second output data storage means 41 selection f stage 5, input register 16, control section 7 and calculation section It consists of 41.

The input register 16 corresponds to an input data storage means 6 that temporarily stores input data read out with a certain word length from the write/read collapsible memory for a certain word length, and the input data 21 is processed by the data processing means l. The data 21 is held until the end.

The data processing means 1 processes the input data 21 read out from the write/read convoluted memory at a constant word length and stored in the input register 16 by moving (shifting), enlarging, thinning out, or a combination thereof. . The data processing means 1 includes an enlargement unit 23 that enlarges input data 21, a thinning unit 24 that thins out data sent from the enlargement unit 23, a thinning unit 25 that moves data sent from the thinning unit 24, etc. configured. The enlarging section 23 is controlled by an enlarging control section 44, and the thinning section 24 sends the data to the thick 25 in a left-justified form, leaving only the bits that are valid in the thinning pattern out of the input data 21. be.

The SHICK 25 is a right shifter in which the input data capacity is, for example, 8.16 bits and the output data capacity is 16.32 bits, and the data is shifted to the right by the amount instructed and output. The value of the adder (ACC) 37 is used as the shift amount.

The control section 7 controls the data processing section 1, and includes an enlargement section 23, a thinning section 24, and a shifter 25.
A selection pattern generator 33 that generates a pattern to be followed when processing data (for example, when the raw turn representing the valid bits of input data has a data width of 16 bits and the fifth bit from the left is valid) is 000
0111111111111), a selected pattern register 42 that temporarily stores the selected pattern, an enlargement section 43 that enlarges the selected pattern, and an enlargement section 2
3. Enlargement control unit 4 that controls enlargement in 43
4, the data expanded by the expansion unit 43 and the pattern data stored in the pattern register 36 are merged into the thinning unit 24 as selection data of bits to be thinned out.
A merge circuit (OR circuit) 35 that sends the data to the data, a pattern register 34 that stores the thinning pattern, a shift register 36 that stores the data movement pattern, and the merge circuit 35 merges the pattern stored in the shift register 36. An adder (
ACC) 37.

Multiplexer (MPX) 29 as selection means 5
is the left register 27 as the first output data storage means 3.
A merging circuit 26 serves as a merging means 2 by selecting data for a fixed word length stored in the data storage unit 2 and data for a fixed word length stored in the right register 28 serving as the second output data storage means 4. It is sent to

The merging means 2, that is, the merging circuit 26 merges the data in the left register 27 or the right register 28 selected by the multiplexer 29 and the new data from the data processing means 1 to be stored in the left register 27. (for example, performs a logical sum) and sends it to the left register 27.

Left register 27 as first output data storage means 3 and right register 28 as second output data storage means 4
are connected in series, and of the data stored in the thick 25, each stores data for a certain word length and data for a certain word length exceeding the certain word length. If the adder 37 determines that the next shift amount exceeds a certain word length such as 16 bits, the data stored in the left register 28 is used as memory write data. It is sent to the arithmetic unit 41 as .

The arithmetic unit 41 performs logical operations on the processed input data and the data at the write position t in the memory, and performs processing such as cutting out the data.
0 consisting of a data register 31 and an arithmetic unit 32
The selection pattern generator 30 generates a pattern for processing, such as cutting out data at a predetermined write position 51 where processed data is written, and
is for storing data at a predetermined write position δ where processed data is written, and the arithmetic unit 32 performs various logical operations on the data sent from the left register 27 based on the pattern and the data at the predetermined write position. The data is written to a readable/writeable memory.

(Effect of Example) Next, the operation of this embodiment will be explained.

As shown in the timing chart of the processing according to the present embodiment in FIG. 3 and the pattern of processing data in FIG. As such, the input register 16
is temporarily stored. The input data 21 is stored in the register 16 until processing such as enlargement is completed. Now, consider a case in which the data is processed by excluding the first two bits of a constant word length (8 bits for simplicity), doubling the length of the remaining data, and shifting the word by a predetermined number of bits.

As shown in FIGS. 3 and 4, the data stored in the input register 16 is enlarged by the enlarger 22, including unnecessary portions. Since we are considering a case where the constant word length is 8 bits, the part equivalent to 4 bits of the input data cannot be handled in one process due to the expansion, so it is stored in the input register 16 and is It will be expanded the next time. That is, the input register 16
Therefore, when enlarging data 21 exceeding a certain word length, there is no need to read input data 21 again from the same address portion of the writable/readable memory.

The data enlarged by the enlarging section 23 is thinned out in the thinning section 24 according to the pattern output by the merging circuit 35 of the control section 7, unnecessary portions are dropped, and the data is shifted to the left. The data obtained in this way is Sick 25
, and is moved (shifted) by a predetermined length.

At this time, control of processing such as enlargement and thinning is performed as follows.

For example, data of a pattern as shown in FIG. 4 generated from the selection pattern generator 33 (unnecessary bits are designated with O, necessary etc. -2 bits are designated with 1) is stored in the selection pattern register 42, and the enlargement control is performed. 44, the pattern is enlarged in the enlarger 43. The enlarged pattern is merged with the thinning pattern stored in the pattern register 34 by the merging circuit 35, and the thinning unit 24 thins out data according to the pattern.The pattern is transferred to the shift pattern register 36 by the adder 37. The data is added to the stored shift pattern and the data is moved according to the added pattern.In this way, 8 bits of fixed word length out of the moved data stored in the thick 25 are merged into the merge circuit 26 as 1,000 r2. By early I-°te “ooooooooo”/71
Combined (logical sum) 7 Left register 27 c-+tt
The amount exceeding the predetermined word, ie, 8 points, is stored in the right register 28. If the adder 37 detects that there is data to be stored in the right register, the data initially stored in the left register 27 is sent to the arithmetic unit 41, and the selection pattern generator 30 and memory write The arithmetic unit 32 calculates the data based on the data register 31 storing the data at the location, and the result of the calculation is written as output data in a readable/writable memory.

On the other hand, the data stored in the right register 28 is the thick 25
When the second new data outputted from is outputted, the multiplexer 29 serving as the selection means 5 selects C and merges it with the data to be stored in the left register 27 among the new data. The words are merged by n6 and stored in the left register 27, and those exceeding the certain word length are stored in the right register 28. At this time, if the adder 37 determines that the second data exceeds a certain word length, the data stored in the left register 27 is sent to the arithmetic unit 41. In the calculation unit 41, the data is stored in the data register 31 at the writing position of the data and the pattern generator 30.
The data is calculated based on the patterns generated by the data processing system, and is written into a readable/writable memory. Here, since the present embodiment includes the data register 31, if a plurality of arithmetic operations are required, there is no need to read data from the writable/readable memory each time.

Subsequently, the data stored in the right register 28 among the second data is selected by the multiplexer 29 and merged with the data to be input into the left register among the third new data from the thick 25 by the merging circuit 26. is,
The data is stored in the left register 27, sent to the arithmetic unit 41, and written into the read/write memory. In this way, various processing processes can be performed by repeating the above steps.

Note that if the word length of the data is reduced due to data thinning, etc., the processed data will only be stored in the left register 27.
Stored. In this case, it is determined that the data processed by the adder 37 does not exceed a certain word length, and the data stored in the left register 27 is not immediately sent to the arithmetic unit 41. The existing data is selected by the multiplexer 29 as the selection means 5, merged with new processed data by the merge circuit 26, and sent to the left register 27.

The data stored in the left register 27 is sent to the arithmetic unit 41 and written into the read/write memory only when the adder 37 determines that the newly processed data has reached a certain word length.

(Effects of the Embodiment) In this embodiment, by providing the data register 31 in the arithmetic means 41, the number of data reads can be reduced and the processing time can be shortened when performing arithmetic operations on data at a write position in a writable/readable memory. I can do it.

In this way, in this embodiment, large amounts of data such as image data can be processed at high speed with a simple configuration.

〔Effect of the invention〕

According to the present invention, since input data storage means is provided,
When processing data such as enlarging data that exceeds a certain word length, and the data cannot be processed at once, read the same address from the read/write memory again. You can process data without any hassle. Therefore, the number of times and time required to read the memory will be reduced.

In addition, when processing data such as moving, enlarging, or thinning out, the word length of the data to be processed exceeds a certain word length or is insufficient, and the processing cannot be completed in one processing. requires connection with the second process. In this case, since the present invention has a merging means, the connection part with the second processing that occurs due to the first processing is temporarily stored in the output data storage means without being immediately written to the memory. .

The connection portion is written after being merged by the merging means with the connection portion to be connected to the portion of the data generated in the second processing process.

Therefore, reading and writing to the memory at the connection portion will not be performed redundantly.

In this way, according to the present invention, the number of accesses and processing time for processing various data is reduced.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a timing chart of the embodiment, Fig. 4 is a data processing diagram, and Fig. 5 is a conventional block diagram. FIG. 2 is a block diagram according to an example. l... Data processing means 2... Merging means 3... First output data storage means 4... Second output data storage means 5... Selection means 6... Input data storage means 7 ...Control unit 41...Arithmetic unit Patent applicant: Fujitsu Limited 1-', 1st Il! Q: Timing chart of data processing, 3rd vA data (24 is also missing) Example I; related data processing is 1 Figure 4

Claims (1)

[Scope of Claims] In a data processing method in which data is processed in units of a predetermined word length using a readable/writable memory, an input data storage means for storing input data of a given word length read from the memory. (6); a data processing means (1) for processing the input data by enlarging, thinning, moving, or a combination thereof; and a first data processing means (1) for storing the processed data in units of word length.
output data storage means (3); a second output data storage means (4) for storing a certain word length exceeding a certain word length resulting from processing by the data processing means (1); a selection means (5) for selecting data stored in the output data storage means (3) and (4) of the output data storage means (3) and (4); a merging means (2) for merging the first output data storage means (4), and the data stored in the first output data storage means (4) can be written into the memory.